JP4759717B2 - Synchronous nonvolatile memory and memory system - Google Patents

Description

  The present invention relates to a synchronous memory and a memory system that perform a synchronous operation in a normal access operation but perform an asynchronous operation in a predetermined period after startup, and in particular, an address supply from the outside is not required in the asynchronous operation. The present invention relates to a synchronous memory and a memory system.

  Conventionally, a memory capable of switching an operation mode of either a synchronous operation or an asynchronous operation with respect to an external clock has been proposed.

  The synchronous nonvolatile memory device of Patent Document 1 has a main memory block and an asynchronous boot block that operate in synchronization with a system clock. The boot block can be activated to operate asynchronously upon initial power up.

Further, in the semiconductor memory device disclosed in Patent Document 2, power is reduced by a synchronous / asynchronous setting unit that is a mode register that generates a signal for transitioning between a synchronous mode and an asynchronous mode, and a state transition signal input in advance. Select either the internal signal that transitions in the state or the internal signal that does not transition and pass it to the synchronous / asynchronous setting unit, so that either the synchronous mode or the asynchronous mode can be used when recovering from the power-down state to the standby state. Select whether to transition to the standby state.
Japanese translation of PCT publication No. 2005-503631 JP 2005-141828 A

  In the memory devices disclosed in Patent Documents 1 and 2 described above, although it is possible to perform an asynchronous operation after startup, address information for specifying a memory cell to be accessed in the asynchronous operation is provided by a method for supplying the address information. It is not disclosed or suggested including issues.

  In a normal memory system, address information is supplied from a memory controller to a memory device regardless of synchronous / asynchronous operation. However, immediately after startup of the entire memory system (after cold start or after power down), the operation of the memory controller itself is also unstable. In addition, the memory controller is a predetermined communication method (mode register such as latency and burst length) between the memory controller and the plurality of synchronous memory devices constituting the period in the synchronous memory system after the period or after the period has passed. And they are communicated via the address bus) to initiate preprocessing for the initialization sequence. In addition to outputting an asynchronous control signal to the memory performing the asynchronous access operation during the unstable state period or the preprocessing period, the address information for the asynchronous access operation is also processed and output. This is a serious problem for the memory controller immediately after startup. In other words, they mean that the address processing for the synchronous operation and the address processing for the asynchronous access operation, which are the preprocessing, are processed in the same time period, which is a burden. Furthermore, the memory controller must ensure sufficient accuracy (setup time / hold time, etc.) for the output timing between a plurality of control signals and addresses for the asynchronous access operation, and the unstable state. During the period or during the preprocessing period, the address information transfer rate must be reduced.

  One way to solve the output timing accuracy problem is to reduce the transfer speed. However, when loading the boot sector by asynchronous operation after startup, for example, when accessing a 128 Kbyte (1 Mbit) address space with an 8-byte I / O memory device, the transfer speed of the address information Slow (for example, 10 MHz) is a problem because it takes a long time (≈1.6 ms) for the total read time of the boot sector after startup. The period of the unstable state and the initial setting sequence period are 200 to 300 μs. In this case, the result of reading by synchronous communication is faster, and the effect of asynchronous communication cannot be exhibited.

  The present invention has been proposed in view of the above-described problems, and is a synchronous memory that performs an asynchronous operation after startup from a power-down state and a synchronous operation that does not require address information to be supplied from the outside during the asynchronous operation of the memory system. An object is to provide a type memory and a memory system.

A synchronous nonvolatile memory according to the present invention is a synchronous nonvolatile memory that performs an asynchronous data read operation for a predetermined period after startup from a power-down state, and stores a predetermined address information in advance. An address register configured with a storage element, and an address counter that generates address information, triggered by a control signal supplied from the outside with reference to predetermined address information during an asynchronous data read operation, and an asynchronous data read operation, A switch unit that selects an address counter instead of an external address terminal and a command monitoring unit that monitors an initialization command for a synchronous operation are provided. In response to the initialization command, the asynchronous data reading operation is terminated.

A memory system according to the present invention is a memory system including a synchronous nonvolatile memory that performs an asynchronous data read operation for a predetermined period after startup from a power-down state, and a memory controller. The memory is preliminarily configured with an address register composed of a non-volatile memory element in which predetermined address information is stored, and a control signal supplied from the memory controller based on the predetermined address information during an asynchronous data read operation as a trigger. An address counter that generates address information, a switch unit that selects an address counter instead of an external address terminal during an asynchronous data read operation, and a command monitoring unit that monitors an initialization command for synchronous operation Yes. In response to the initialization command, the asynchronous data reading operation is terminated.

  Thus, when an asynchronous data read operation is performed in a predetermined period after activation from the power-down state, only a control signal is supplied to the synchronous nonvolatile memory from the outside such as a memory controller. Using this control signal as a trigger, the address counter in the synchronous nonvolatile memory can be counted. At this time, since predetermined address information is stored in the address register in advance, information such as initial address information, end address information, address count-up number (the number of bits is smaller than the end address information), and the like are obtained. A counter can be counted.

  For this reason, the memory controller sets and registers an address space for asynchronous data reading in the nonvolatile address register before shifting to the power-down state, and addresses necessary for asynchronous data reading in a predetermined period after startup. Only a control signal for generating a space is supplied to the memory device. That is, the memory controller does not need to issue address information to the synchronous nonvolatile memory in an asynchronous data read operation after activation. Even when the memory controller is in an unstable operating state after startup or in the initial setting sequence processing period for synchronous communication, only the control signal needs to be output to the synchronous nonvolatile memory that performs asynchronous operation. Thus, the burden on the memory controller during the unstable operation period after startup or the processing period of the initial setting sequence can be reduced.

  Also, problems related to the output timing of the control signal and the address information can be avoided. That is, it is freed from the problem that sufficient accuracy (setup time / hold time, etc.) cannot be secured for the output timing of both signals. Furthermore, it is not necessary to reduce the transfer speed of the signal output from the memory controller in order to ensure the accuracy of the output timing, and the data read time after startup can be shortened.

  In addition, the memory system according to the present invention is configured such that the memory controller issues an initialization command for synchronous communication to another device, and asynchronous data to the own device by a control signal not used for the initialization command of the other device. A function of simultaneously processing read communication is provided.

  As a result, the initialization sequence for synchronous communication and the asynchronous read sequence can be processed simultaneously.

  According to the synchronous nonvolatile memory and memory system of the present invention, in a synchronous nonvolatile memory and memory system that performs an asynchronous read operation after startup from the power-down state, the predetermined address information is synchronized before entering the power-down state. By writing to the type non-volatile memory, it is unnecessary to supply address information from the outside such as a memory controller at the time of asynchronous read operation after startup, and in the asynchronous read operation after startup, the signal supplied from the outside It is possible to provide a synchronous nonvolatile memory and a memory system capable of ensuring accuracy and improving signal transfer speed.

  FIG. 1 is a system configuration diagram including a memory system 1 according to the present invention. A memory system 1 is connected to a bus 5 together with a CPU 2 and a memory controller 3. The memory system 1 includes a memory controller 6, a synchronous DRAM 7, and a synchronous flash memory 8. The synchronous DRAM 7 and the synchronous flash memory 8 are connected to the memory controller 6 via the local bus 9. The memory controllers 3 and 6 are connected to the bus 5. The memory controller 3 is connected to the NAND flash memory 4.

  Here, the local bus 9 is a bus in which the synchronous DRAM 7 and the synchronous flash memory 8 share (share) address information lines, data lines, control signal lines, and the like.

  In the system of FIG. 1, code information for starting the system is stored not in the NAND flash memory 4 but in the synchronous flash memory 8. In the initialization sequence after system startup, when loading various programs and various data represented by Boot loader (IPL) with a relatively small capacity (128 Kbytes) indispensable for system startup to CPU 2 and synchronous DRAM 7, We are trying to speed up. This is because in the NAND flash memory 4 having a slow first access, the load time of the IPL is slow.

  In this case, the memory controller 6 performs synchronization control using a system clock (synchronization signal CLK) for controlling the synchronous DRAM 7 and the synchronous flash memory 8 in a steady state. For synchronous communication between the controller 6 and the synchronous DRAM 7 and the synchronous flash memory 8 in the synchronous control, it is necessary to set access conditions such as latency control and burst length control in advance. This is an operation called an initialization sequence for synchronous communication by setting a mode register (MRS). Further, when the entire system is cold-started, it is necessary to perform a synchronization operation after the synchronization signal CLK reaches a stable frequency, and a predetermined waiting time (200 μs) is required from the time when the power source reaches a predetermined voltage and stabilizes. Become.

  Here, according to the synchronous flash memory 8 of the present application, data read operation in asynchronous communication during a predetermined period after the system is started (from the time when the power source reaches a predetermined voltage and is stabilized until the initialization sequence of the synchronous flash memory 8). By doing this, it is possible to perform an IPL data read operation indispensable for system activation even during a period when the synchronization signal CLK after activation is not stable or during an initialization sequence period of the synchronous DRAM 7. At this time, the signal for asynchronous communication output from the memory controller 6 may be only at least one control signal (/ RAS or / CAS, DM not used for the initialization sequence) as a trigger signal. It is not necessary to output the address information. A non-volatile address register and an address counter (see FIG. 2) built in the synchronous flash memory 8 perform a counting operation in response to a control signal such as / RAS, / CAS, etc. This is because address information is sequentially generated.

  Even if the operation of the memory controller 6 is busy with the process for the instability / initialization sequence during the predetermined period in which the asynchronous flash memory 8 performs the asynchronous read operation after the startup, the memory controller 6 receives the / RAS , / CAS and the like need only be output. There is no need to perform control operations such as updated output of address information and highly accurate output synchronization timing between the address information and the control signal.

  As a necessary minimum control of outputting at least one control signal such as / RAS or / CAS for a predetermined period after the system is started, the address information of the IPL space is set inside the synchronous flash memory 8. As a result, the asynchronous read operation of the synchronous flash memory 8 can be performed. Thereby, it is possible to further speed up loading of various programs such as IPL and various data, which are indispensable for system activation after system activation, from the synchronous flash memory 8 to the CPU 2 and the synchronous DRAM 7.

  FIG. 2 is a circuit block diagram of the synchronous flash memory 8 of the embodiment.

First, a description will be given of a circuit related to control for shifting to an asynchronous read operation after starting an external power supply that requires an initial setting sequence or after returning from a power-down state involving restart of an internal power supply of a memory device.
The power-on reset signal POR output from the power-on reset circuit 10 is input to the asynchronous control circuit 11 and the I / O control circuit 18. The asynchronous control circuit 11 receives the synchronization signal CLK, the / RAS signal, the / CAS signal, and other signals. Asynchronous control signal ASYC is output from asynchronous control circuit 11. Asynchronous control signal ASYC is input to command decoder 12, changeover switch 21, latency control circuit 17, I / O control circuit 18, and address transition detection circuit 22.

Next, a description will be given of circuit portions related to control for command input and setting of address information.
The command decoder 12 receives the synchronization signal CLK, the / RAS signal, the / CAS signal, and other signals, and commands for controlling the row-related control circuit 13, the column-related control circuit 14, and the latency control circuit 17 during the synchronous operation. A signal COM is output. In addition, an address latch signal AL is output to the address buffer circuit 20. Further, the asynchronous control signal ASYC is input to the command decoder 12, and an asynchronous control signal CNT for control required during the asynchronous operation is output to the nonvolatile address register & address counter 19 during the asynchronous operation. The asynchronous control signal CNT is used for pre-registration in the non-volatile register or by counting up an address counter using at least one control signal supplied from the outside as a trigger based on predetermined address information of the non-volatile register at the time of non-synchronization. It is a signal for generating information. The address counter has a known configuration (volatile) in which the lower side is a column address and the upper side is a row address. The address counter is counted up from the lower side corresponding to the rising edge of the control signal. In the asynchronous operation, the asynchronous control signal CNT controls an address counter or the like in response to an asynchronous control signal (/ RAS signal, / CAS signal or data mask signal DM) from the outside of the device. In addition, the nonvolatile address register & address counter 19 has nonvolatile external address information Add indicating the memory space to be accessed from the outside during asynchronous operation in advance (before shifting to the power-down state) by a mode register set command or the like. The predetermined address information is set in the address register. Here, the address register is composed of a non-volatile storage element and does not disappear even when the power is turned off. The address counter operates during an asynchronous read operation after activation based on the contents of the address register. The nonvolatile address register & address counter 19 outputs register address information RAdd that is an output value of the address counter and an address end signal ATE. The register address information RAdd is output to the changeover switch 21 and the address transition detection circuit 22. The address end signal ATE is output to the asynchronous control circuit 11. Further, the external address information Add input from the external terminal 23 is input to the changeover switch 21, and either the register address information RAdd or the external address information Add is selected and output to the address buffer circuit 20. Register address information RAdd is selected by the asynchronous control signal ASYC. The address buffer circuit 20 outputs the input address information as internal address information IAdd to the row decoder 31R and the column decoder 31C.
The address buffer circuit 20 is reset to a high level when the power is turned on, and the internal address information IAdd indicates the final address (#F; hexadecimal number). Thus, even when the register address information RAdd indicates the initial address (# 0; hexadecimal), the address transition detection circuit 22 described later detects the transition of the address information, and the row-related control circuit 13 and the column-related control circuit 14 Accesses data in the memory cell array.

Next, a circuit portion related to control for address information will be described.
The address transition detection circuit 22 is a circuit that functions at the time of asynchronous operation, and is used for address information transition and bit line (not shown) switching related to switching of word lines (not shown) in the input internal address information IAdd. The address information transition is detected, and the transition detection pulse signal ATR is output to the row-related control circuit 13 and the column-related control circuit 14. On the other hand, during the synchronous operation, the row control circuit 13 and the column control circuit 14 are controlled by the command signal COM output from the command decoder 12 and access the memory cell array 31. Regarding word line switching during asynchronous operation, if the memory space accessed during asynchronous operation is 128 Kbytes, each of the 512 word lines is provided with 2048-bit memory cells. The transition detection pulse signal ATR detects the transition of the word line from the address information related to the word line, and the row system control circuit 13 resets the word line and initializes the bit line, and the activation of the word line after the switching, the column system The control circuit 14 resets and switches the data bus between the data read circuit 15 and the column decoder 31C to the data read circuit 15, and activates the bit line activation / data read circuit 15. Regarding bit line switching, the transition detection pulse signal ATR detects transition of the bit line from the address information related to the bit line for the 2048 bit lines accessed during asynchronous operation, and the column control circuit 14 reads the data. The data bus between the circuit 15 and the column decoder 31C and the data read circuit 15 is reset and switched to activate the bit line activation / data read circuit 15. Row-related control circuit 13 and column-related control circuit 14 output control signals to row decoder 31R and column decoder 31C, respectively. The column-related control circuit 14 also outputs a control signal to the data read circuit 15. Row decoder 31R and column decoder 31C decode the row address and column address of memory cell array 31, respectively.

Next, a circuit portion relating to data output control will be described.
The latency control circuit 17 is a function for managing the delay in data input / output via the I / O buffer circuit 16 corresponding to the synchronization signal CLK, which acts during the synchronization operation, and controls the set latency information by I / O control. Output to the circuit 18. Latency control circuit 1 7 via the I / O control circuit 18, and outputs a control signal to the I / O buffer circuit 16. The data read circuit 15 is a circuit including a sense amplifier circuit (not shown), amplifies the data read from the memory cell array 31, and outputs it to the I / O buffer circuit 16. The I / O buffer circuit 16 outputs data based on control by the I / O control circuit 18. Although not shown, data is written through the I / O buffer circuit 16. Further, the asynchronous control signal ASYC is input to the latency control circuit 17, and the management function is inactivated during the asynchronous operation. Specifically, in response to an asynchronous control signal (/ RAS signal, / CAS signal or data mask signal DM) from the outside of the device for control required during asynchronous operation, the I / O control circuit 18 performs I / O control. By controlling High-Z / Low-Z of the buffer circuit 16, data in the asynchronous operation is output to the I / O. Further, a power-on reset signal POR is input to the I / O control circuit 18. The I / O control circuit 18 controls the I / O buffer circuit 16 to High-Z when the power supply VDD / VDDQ (I / O power supply) is turned on. The I / O buffer circuit 16 is released to Low-Z during the synchronization operation when the latency control circuit 17 outputs the synchronization data. On the other hand, the I / O buffer circuit 16 is released to Low-Z during asynchronous operation when asynchronous data is output by an asynchronous control signal (/ RAS signal, / CAS signal or data mask signal DM) from the outside of the device. is there. That is, for the control from High-Z to Low-Z, the asynchronous control signal ASYC is switched from the latency control to the asynchronous control signal from the outside of the device which is an external control signal at the asynchronous time.

  Next, an outline of the asynchronous read operation after activation will be described. A detailed timing chart will be described later with reference to FIGS.

  First, when the memory 1 is activated, a power-on reset signal POR output from the power-on reset circuit 10 is received, or a return command from the power-down mode (with any combination of the synchronization signal CLK and other signals). Input), the asynchronous control circuit 11 outputs an asynchronous control signal ASYC. As a result, the command decoder 12 that is synchronously controlled in the normal synchronous operation state and the synchronous control portion of the latency control circuit 17 are set to full pass-through as described above. Further, the I / O control circuit 18 entrusts the Low-Z control of the I / O buffer circuit 16 to the external control signal at the asynchronous time.

  Also, if the power-on reset signal POR is normal (synchronous operation), the active command after the initialization sequence is completed and a high latency (hereinafter referred to as HiZ) state is maintained until a predetermined latency. The O output terminal is released by the asynchronous control signal ASYC. As a result, in the asynchronous read operation, data corresponding to the asynchronous control signal from the outside of the device, which is an external control signal at the time of asynchronous, can be output.

  The changeover switch 21 selects the external address information Add during a normal synchronous operation in which the asynchronous control signal ASYC is not issued. The register address information RAdd is selected in place of the external address information Add by the asynchronous control signal ASYC.

  The row-related control circuit 13 and the column-related control circuit 14 operate in response to the falling edges of the / RAS signal, / CAS signal, or DM0 and DM1 signals that have passed through the command decoder 12. In this case, the / RAS signal or DM0 signal is used for intermittent control of the signal path of the / CAS signal or DM1 signal. That is, when the / RAS signal or DM0 signal is at a low level, a signal path is established and the / CAS signal DM1 signal is propagated. The memory cell array 31 is accessed by the operations of the row-related control circuit 13 and the column-related control circuit 14. The external control signal during asynchronous operation may be at least one external control signal. For example, only the / CAS signal may be used, or only the DM1 signal may be used. This is because switching to the word line and switching of the bit line can be performed by one external control signal by the transition detection pulse signal ATR output from the address transition detection circuit 22 described above.

  At this time, the address buffer circuit 20 latches the register address information RAdd that is input via the changeover switch 21. The nonvolatile address register & address counter 19 performs a count operation at the rising edge of / CAS, and outputs register address information RAdd that is sequentially updated based on predetermined address information. The output register address information RAdd is latched in the address buffer circuit 20 at the falling edge of / CAS, and is output to the row / column decoders 31R / 31C as internal address information IAdd. A memory cell in a predetermined address space designated by the internal address information IAdd is selected, and initialization data such as a boot program is output from the I / O buffer circuit 16.

  At this time, there is a case where reading is continued across the word lines in the memory cell array 31 by the internal address information IAdd that is sequentially updated. Since the memory controller 6 recognizes the address mapping of the memory cell array 31 in advance, the / RAS signal (DM0) at the rising edge before the number of transitions of the falling edge of the / CAS signal (DM1 signal) reaches a predetermined count. Signal) is also shifted to a high level. When the address transition detection circuit 22 detects the rising edge of the / RAS signal (DM0 signal), it outputs a transition detection pulse signal, and resets the row control circuit 13 and the column control circuit 14. As a result, the word lines can be switched. In the case of a memory system in which asynchronous operation is performed by one external control signal (any one of / RAS signal, / CAS signal, DM0 signal, and DM1 signal), the memory controller is configured according to the address mapping. The high level and low level of the control signal are repeated. The high level corresponding to the word line switching and the high level time corresponding to the bit line switching are controlled according to the address mapping. The transition detection pulse signal ATR in this case detects the transition of the word line from the address information related to the switching of the word line, and the row control circuit 13 resets the word line and initializes the bit line, and the word line after the switching. The column control circuit 14 activates the bit line activation / data read circuit 15 after resetting and switching the data bus between the data read circuit 15 and the column decoder 31C to the data read circuit 15. Further, the transition detection pulse signal ATR detects the transition of the bit line from the address information related to the switching of the bit line, and the column control circuit 14 detects the data bus between the data read circuit 15 and the column decoder 31C to the data read circuit 15. The bit line activation / data read circuit 15 is activated after switching to resetting.

  When the final address is recognized, an address end signal ATE issued from the nonvolatile address register & address counter 19 is input, or a command (synchronization) constituting an initialization sequence of the synchronous DRAM 7 sharing the local bus 9 The asynchronous control circuit 11 resets the asynchronous control signal ASYC when a command signal EMRS corresponding to any one of the signals CLK, / RAS signal, / CAS signal, and other signals) is input. As a result, the asynchronous operation ends, and the normal synchronous operation state is entered.

  FIG. 3 is a circuit diagram illustrating an example of the asynchronous control circuit 11. The return determination circuit 25 to which a signal group constituting a power-down command composed of any combination of the synchronization signal CLK, the / RAS signal, the / CAS signal, and other signals is inputted, returns from the power-down state. Detect and output a return signal PDEXIT. Further, the return determination circuit 25 to which a signal group constituting an initialization sequence of the synchronous DRAM 7 configured by any combination of the synchronization signal CLK, the / RAS signal, the / CAS signal, and other signals is input is synchronized. An initialization sequence for operation is detected and a command signal EMRS is output. Further, the return determination circuit 25 to which a signal group constituting an initialization sequence of the synchronous flash memory 8 configured by any combination of the synchronization signal CLK, the / RAS signal, the / CAS signal, and other signals is input. The initialization sequence for the synchronous operation is detected and the command signal PRE is output. The first OR gate 26 receives the power-on reset signal POR and the return signal PDEXIT. The second OR gate 27 recognizes the address end signal ATE, the command signal EMRS recognizing the command group constituting the initialization sequence of the synchronous DRAM 7, or the command group constituting the initialization sequence of the synchronous flash memory 8. The command signal PRE is input. The first OR gate 26 and the second OR gate 27 are input to the set terminal and the reset terminal of the flip-flop circuit 28, respectively. Asynchronous control signal ASYC is output from flip-flop circuit 28. The asynchronous control signal ASYC is activated by the power-on reset signal POR or the return signal PDEXIT, and deactivated by the command signal EMRS of the synchronous DRAM 7, the command signal PRE of the synchronous flash memory 8, or the address end signal ATE. The command signal EMRS can recognize the initialization sequence of the synchronous DRAM 7 by invalidating the chip select signal CS for selecting the synchronous flash memory 8.

  4 and 5 are timing charts showing an asynchronous read operation after the system is started in the synchronous flash memory 8. FIG. This is shown together with the positioning in the timing chart on the local bus 9 in the memory system 1. FIG. 4 shows an asynchronous read operation from the synchronous flash memory 8 before the synchronous signal CLK generated from the memory controller 6 after the system is started is shifted to a stable state. FIG. 5 shows the operation when the asynchronous read operation from the synchronous flash memory 8 is extended to the initialization sequence period of the synchronous DRAM 7. The upper timing chart shows the timing chart after the system activation of various signal lines on the local bus 9. A timing chart at the time of asynchronous operation of the synchronous flash memory 8 is shown in the lower part.

  In FIG. 4, in the upper timing chart, the period (A) is a period immediately after the system is started and the operation of the memory controller 6 is not stable. This is a period during which the synchronization signal CLK is not stably supplied. The period (B) is a period during which the synchronization signal CLK is stably supplied. The period (B) is a period of the initialization sequence of the synchronous flash memory 8 or the synchronous DRAM 7. The period (C) is a period in which the initialization sequence of the synchronous flash memory 8 and the synchronous DRAM 7 ends and a normal synchronous operation is performed. FIG. 4 shows a read operation for the synchronous flash memory 8. The period (A) includes a pre-process for an initial setting sequence (period (B)) for the synchronous DRAM 7 and the synchronous flash memory 8.

  The asynchronous read operation period (X1) of the synchronous flash memory 8 is executed in the period (A). It is executed after the power supply voltage rises in the period (A). The external address information Add is in a don't care state from the memory controller 6 and no valid address information is issued. During this period, an asynchronous operation to the synchronous flash memory 8 is started. The / CAS signal transitions in a state where the / RAS signal transitions from the high level to the low level and the low level is maintained. The word line / bit line or the like is activated in response to the fall of the / RAS signal, the data read circuit 15 or the like is activated in response to the fall of the / CAS signal, and the memory cell data is output to the I / O. . The address counter 19 performs a counting operation in response to the rise of the / CAS signal, and the register address information RAdd is updated sequentially. This accesses the memory cell array 31 as internal address information IAdd, and data is sequentially output to the I / O terminals. The external control signal during asynchronous operation may be at least one external control signal (/ RAS signal or / CAS signal).

  The end of the asynchronous read operation is ended according to the end address or the address count number stored in advance in the address register 19. Since reading of all data is completed in the period (A), the control signal for command command or the external address Add issued to the synchronous flash memory 8 or the synchronous DRAM 7 in the period (B) is an asynchronous read operation. Will not collide with.

  In the asynchronous read operation of the synchronous flash memory 8, it is not necessary to issue the external address information Add from the memory controller 6. Further, since the initialization sequence of the synchronous flash memory 8 or the synchronous DRAM 7 is not started, there is no need to issue a command command control signal to the synchronous flash memory 8 or the synchronous DRAM 7. Therefore, control signals such as a / RAS signal and a / CAS signal can be used for asynchronous read control of the synchronous flash memory 8.

  In the asynchronous read operation of the synchronous flash memory 8, it is not necessary to issue the external address information Add from the memory controller 6, and the problem of output timing accuracy does not occur, so asynchronous read can be performed at a higher speed than before. Specifically, when loading a boot sector, for example, when accessing a 128 Kbyte (1 Mbit) address space with an 8-byte I / O memory device, the transfer speed of address information is fast (for example, 100 MHz), the boot sector total read time after startup (≈160 μs) can be shortened. In the period (A), reading of all data is completed.

  In FIG. 5, in the upper timing chart, the period (O) is a period during which the synchronization signal CLK is stably supplied. Prior to the initialization sequence period (B) of the synchronous flash memory 8, the initialization sequence period (O) of the synchronous DRAM 7 is performed. Since the periods (A), (B), and (C) are the same as those in FIG. 4, the description thereof is omitted here.

  The asynchronous read operation period (X2) of the synchronous flash memory 8 is executed from the period (A) to the period (O). Execution is started after the power supply voltage rises in the period (A). The asynchronous read operation is completed within the period (O). Since the command (PRE, ARF, MRS, EMRS) is issued from the memory controller 6 in the period (O), the control signal or / and the address information may be used for the command command. Therefore, the control signal issued from the memory controller 6 to the synchronous flash memory 8 in the asynchronous read operation needs to be a signal that is not used in the initialization sequence of the synchronous DRAM 7. FIG. 5 illustrates the case where the data mask signals DM0 and DM1 are used. The DM1 signal changes in a state where the DM0 signal changes from the high level to the low level and the low level is maintained. The word line / bit line or the like is activated in response to the falling of the DM0 signal, the data read circuit 15 is activated in response to the falling of the DM1 signal, and the memory cell data is output to the I / O. The address counter 19 performs a counting operation in response to the rise of the DM1 signal, and the register address information RAdd is sequentially updated. This accesses the memory cell array 31 as internal address information IAdd, and data is sequentially output to the I / O terminals. The external control signal during asynchronous operation may be at least one external control signal (DM0 signal or DM1 signal).

  The asynchronous read operation is terminated by detecting the EMRS command that is the last command in a series of command groups in the initialization sequence of the synchronous DRAM 7. The asynchronous read operation can be surely terminated even when the reading of all data is not completed within the period (A) in the asynchronous read operation, or when the memory controller 6 interrupts the asynchronous read operation in the middle. .

  In the asynchronous read operation of the synchronous flash memory 8, the DM0 signal and DM1 signal can be used, and the external address information Add on the local bus 9 can be invalidated.

  Here, the synchronous flash memory 8 is an example of a synchronous nonvolatile memory. The nonvolatile address register & address counter 19 is an example of a nonvolatile address register and address counter. The external terminal 23 is an example of an external address terminal. The changeover switch 21 is an example of a switch unit. The address transition detection circuit 22 is an example of an address transition detection unit, and the transition detection pulse signal is an example of a control pulse.

  The memory system 1 is an example of a memory system, the synchronous DRAM 7 is an example of another device, and the local bus 9 is an example of a signal line through which a command propagates. The commands (PRE, ARF, MRS, EMRS) given during the initialization sequence of the synchronous flash memory 8 or the synchronous DRAM 7 are examples of initialization commands. The return determination circuit 25 and the command decoder 12 are examples of a command monitoring unit, and the command signals PRE and EMRS are examples of predetermined commands.

  As described above in detail, according to the embodiment of the present invention, when an asynchronous data read operation is performed in a predetermined period after power-on or startup from a power-down state by a power-down command, the synchronous flash memory 8 Is supplied with at least one external control signal (any one of / RAS signal, / CAS signal, DM0 signal, DM1 signal) from the memory controller 6. Using this control signal as a trigger, the address counter constituting the nonvolatile address register & address counter 19 in the synchronous flash memory 8 can be counted. At this time, since the predetermined address information is stored in advance in the address register that constitutes the nonvolatile address register & address counter 19 (before the transition to the power-down state), the initial address Information, final address information, and information such as the number of addresses can be obtained to count the address counter.

  Therefore, it is not necessary to input the external address information Add via the external terminal 23 when performing an asynchronous data read operation. Even when the memory controller 6 is in an unstable operation state after starting, it is only necessary to output a control signal (/ RAS, / CAS, DM0, DM1) to the synchronous flash memory 8 that performs asynchronous operation. The burden on the memory controller 6 during the subsequent unstable operation period can be reduced.

  Further, the complexity of adjusting the output timing of the control signals (/ RAS, / CAS, DM0, DM1) and the external address information Add is also eliminated. That is, it is freed from the problem that sufficient accuracy cannot be secured for the output timing of both signals. Furthermore, it is not necessary to slow down the transfer speed of the signal output from the memory controller 6 in order to ensure the accuracy of the output timing, and the asynchronous data read time after activation can be shortened.

Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the configuration in which the synchronous flash memory 8 and the synchronous DRAM 7 are connected to the local bus 9 as the memory controller 1 is illustrated, but the present invention is not limited to this. Needless to say, other devices than the synchronous DRAM 7 may be used. There is no limit to the number of memory devices connected to the local bus 9. The synchronous flash memory 8 may be a non-volatile memory, and the principle operation of the non-volatile memory is not limited. The storage structure, storage method, and circuit configuration of the nonvolatile address register are not limited.
Further, the configuration in which the asynchronous read operation is terminated by detecting the mode register set command EMRS / precharge command PRE among the initialization sequence commands of the synchronous DRAM 7 / synchronous flash memory 8 has been described as an example. It is not limited. Any command that constitutes an initialization sequence can be applied. Further, the configuration for detecting the return from the power-down state may be a combination of the clock enable signal CKE and the synchronization signal CLK. Further, the function of the asynchronous control circuit 11 can be included in the command decoder 12. In addition, regarding the output control of data at the time of asynchronous, the I / O control circuit 18 replaces the Low-Z control of the I / O buffer circuit 16 with the external control signal (/ RAS signal, / CAS signal) at the time of asynchronous. Thus, Low-Z control may be performed only by the asynchronous control signal ASYC. In this case, the I / O buffer circuit 16 in the asynchronous operation period is Low-Z control, and the data is not interrupted even when the / RAS signal and the / CAS signal rise (without moving to High-Z). Continue to output previous data until data changes. The data before and after the switching of the word line is not interrupted. The transfer speed of address information during asynchronous operation can be further increased (for example, 200 MHz). It can support 256 Kbyte (2 Mbit) IPL. This is because the effective period of the data latch of the memory controller is doubled.

It is a system configuration figure of an embodiment of the present invention. It is a circuit block diagram of the synchronous memory of the embodiment. 2 is a circuit diagram of an asynchronous control circuit 11. FIG. It is one timing chart which shows operation | movement of embodiment. It is another timing chart which shows operation | movement of embodiment.

1 Memory system 2 CPU
3, 6 Memory controller 4 NAND flash memory 5 Bus 7 Synchronous DRAM
8 Synchronous flash memory 9 Local bus 10 Power-on reset circuit 11 Asynchronous control circuit 12 Command decoder 13 Row system control signal 14 Column system control signal 15 Data read circuit 16 I / O buffer circuit 17 Latency control circuit 18 I / O control circuit 19 address register & address counter 20 address buffer circuit 21 changeover switch 22 address transition detection circuit 23 external terminal 25 return determination circuit 26 first OR gate 27 second OR gate 28 flip-flop circuit 31 memory cell array 31C column decoder 31R Row decoder Add External address information AL Address latch signal ASYC Asynchronous control signal ATE Address end signal ATR Transition detection pulse signal CLK Synchronous signal CNT Asynchronous control signal COM Command signal EMR S Command signal PRE Command signal IAdd Internal address information PDEXIT Return signal POR Power-on reset signal RAdd Register address information

Claims (14)

A synchronous nonvolatile memory that performs an asynchronous data read operation for a predetermined period after startup from a power-down state,
An address register composed of a nonvolatile memory element in which predetermined address information is stored in advance;
An address counter that generates address information, triggered by a control signal supplied from the outside with the predetermined address information as a reference during the asynchronous data read operation;
A switch unit that selects the address counter instead of an external address terminal during the asynchronous data read operation ;
A command monitoring unit that monitors an initialization command for synchronous operation;
The synchronous nonvolatile memory , wherein the asynchronous data read operation is terminated in response to the initialization command .   2. The synchronous type according to claim 1, further comprising an address transition detection unit that outputs a control pulse in response to a transition of address information related to switching of a word line among the address information generated by the address counter. Non-volatile memory.   3. The synchronous nonvolatile memory according to claim 1, wherein the predetermined address information is start address information of the asynchronous data reading operation.   4. The synchronous nonvolatile memory according to claim 1, wherein the predetermined address information is end address information of the asynchronous data reading operation. 5.   4. The synchronous nonvolatile memory according to claim 1, wherein the predetermined address information is a count-up number of an address counter that determines end address information of the asynchronous data read operation. memory. The command monitoring unit is an initialization command for another device that shares a signal line through which a command propagates, and monitors a predetermined command of another device issued before issuing a command related to its own synchronization operation. The synchronous nonvolatile memory according to claim 1, wherein: 6. The at least one of claims 1 to 5, wherein the command monitoring unit monitors a command related to its own synchronization operation, which is an initialization command of its own device sharing a signal line through which the command is propagated. The synchronous nonvolatile memory according to item . 5. The switch unit selects the external address terminal in response to the address counter generating the end address information or the command monitoring unit detecting the predetermined command. to synchronous non-volatile memory according to at least any one of 7. A memory system comprising a synchronous nonvolatile memory that performs an asynchronous data read operation for a predetermined period after startup from a power-down state, and a memory controller,
The synchronous nonvolatile memory is
An address register composed of a nonvolatile memory element in which predetermined address information is stored in advance;
An address counter that generates address information using the control signal supplied from the memory controller as a trigger based on the predetermined address information during the asynchronous data read operation;
A switch unit that selects the address counter instead of an external address terminal during the asynchronous data read operation ;
A command monitoring unit that monitors an initialization command for synchronous operation;
The memory system , wherein the asynchronous data read operation is terminated in response to the initialization command . The memory system according to claim 9 , wherein the memory controller includes a control unit that writes the predetermined address information to the synchronous nonvolatile memory before shifting to the power-down state. The memory controller has a function of simultaneously processing the asynchronous data reading by the control signal not used for the initialization command of the other device while issuing an initialization command of the other device. The memory system according to 9 or 10 . It has other devices that share the signal line on which the command propagates,
The memory system according to claim 9 or 10 , wherein data read from the synchronous nonvolatile memory during the asynchronous data read operation is stored in the other device. The at least one of claims 9 to 12, wherein the command monitoring unit monitors a predetermined command of another device that is an initialization command of another device and is issued before issuing a command related to its own synchronous operation. The memory system according to claim 1 . The at least one of claims 9 to 12, wherein the command monitoring unit monitors a command related to its own synchronization operation, which is an initialization command of its own device sharing a signal line through which the command is propagated. The memory system according to item .

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