JP4756221B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device made of SRAM (Static Random Access Memory).

  In order to realize high integration and high performance of a semiconductor device, a columnar semiconductor is formed on the surface of a semiconductor substrate, and an SGT (vertical gate transistor having a gate formed so as to surround the columnar semiconductor layer on a sidewall thereof. (Surrounding Gate Transistor) has been proposed (for example, Patent Document 1: JP-A-2-188966). In the SGT, the drain, gate and source are arranged in the vertical direction, so that the occupied area can be greatly reduced as compared with the conventional planar type transistor.

  When an LSI (Large Scale Integrated Circuit) is configured using SGT, it is essential to use an SRAM configured by a combination of SGTs as the cache memory. In recent years, there is a strong demand for a large capacity for SRAM mounted on an LSI, and it is essential to realize an SRAM having a small cell area even when SGT is used.

  FIG. 25 (a) is a cross-sectional view of a plan view of a CMOS type 6T-SRAM composed of six transistors designed using SGT, shown in the embodiment of Patent Document 2 (Japanese Patent Laid-Open No. 7-99311). Is shown in FIG. The SRAM will be described with reference to these drawings. The bit lines (801a, 801b) are formed of N + diffusion layers, the ground wiring GND is formed of N + diffusion layers 802, and the power supply wiring Vcc is formed of P + diffusion layers 803. Access transistors (810a, 810b) for accessing the memory cells on these diffusion layers, driver transistors (811a, 811b) for driving the memory cells, and load transistors (812a, 812b) for supplying charges to the memory cells A columnar silicon layer is formed. Gates (804a, 804b, 804c, 804d) are formed so as to surround these columnar silicon layers. The storage node is composed of wiring layers (807a and 807b). In the SRAM cell, since each transistor constituting the SRAM has a source, a gate, and a drain formed in the vertical direction on the columnar silicon layer, a small SRAM cell can be designed.

JP 2-188966 JP-A-7-99311 (paragraph 51, FIG. 75)

However, the above SRAM cell actually has the following problems.
In the SRAM of Patent Document 2, it is possible to realize a small cell area when the power supply wiring 803 and the ground wiring 802 formed in the SRAM cell array are formed to have a minimum dimension. Since the ground wiring 802 and the ground wiring 802 are formed by the P + diffusion layer and the N + diffusion layer, respectively, when they are formed to a minimum dimension, the resistance becomes very high, and the SRAM cannot be stably operated. . Conversely, when the dimensions of the power supply wiring 803 and the ground wiring 802 are increased in order to stably operate the SRAM, the SRAM cell area increases.

  The present invention has been made in view of the above circumstances, and an object thereof is to realize an SRAM cell having a small area and an SRAM cell having a sufficient operation margin in a CMOS type 6T-SRAM using SGT. .

According to the present invention, for example, as shown in FIG. 3d, a semiconductor memory device comprising static memory cells in which six MOS transistors are arranged on a substrate,
Each of the six MOS transistors is
A source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, the columnar semiconductor layer is arranged between the source diffusion layer and the drain diffusion layer, and the columnar semiconductor layer A gate is formed on the side wall,
First and second NMOS access transistors for accessing the memory (Qn11及 beauty Qn21), first and second NMOS driver transistors for driving a memory node in order to retain data in the memory cell (Qn31 And Qn41), and function as first and second PMOS load transistors (Qp11 and Qp21) for supplying charges to hold data in the memory cells,
The first NMOS access transistor (Qn11) , the first NMOS driver transistor (Qn31), and the first PMOS load transistor (Qp11) are arranged adjacent to each other,
The second NMOS access transistor (Qn21) , the second NMOS driver transistor (Qn41), and the second PMOS load transistor (Qp21) are arranged adjacent to each other,
A first well (1a, p-well) common to a plurality of memory cells for applying a potential to the substrate is formed,
Formed on the bottom of the first diffusion layer single lifting the first NMOS access transistor N-type conductivity type formed on the bottom of (Qn11) (3a, N-type), the first NMOS driver transistor (Qn31) The second diffusion layer (5a, N type) having the N type conductivity and the third diffusion layer (P type conductivity type) formed at the bottom of the first PMOS load transistor (Qp11) 4a, P-type) are formed on the surfaces of the first diffusion layer (3a, N-type), second diffusion layer (5a, N-type) and third diffusion layer (4a, P-type ) . Connected to each other through one silicide layer (13a),
The first diffusion layer (3a, N type), the second diffusion layer (5a, N type) and the third diffusion layer (4a, P type) connected to each other are data stored in the memory cell. Function as the first storage node (Qa) to hold
Said third diffusion layer (4a, P-type) in order to prevent leakage between said first well (1a, p-well), the third diffusion layer (4a, P-type) and the first A first leakage preventing diffusion layer (1b, N-type) having a conductivity type opposite to that of the first well is formed between the wells (1a, p-well) ,
The first leakage preventing diffusion layer (1b, N type) is directly connected to the first diffusion layer (3a, N type) and the second diffusion layer (5a, N type),
Fourth diffusion layer having a second N-type conductivity type formed on the bottom of the NMOS access transistor (Qn21) (N-type), N being formed in the bottom portion of the second NMOS driver transistor (Qn41) A fifth diffusion layer (N-type) having a conductivity type of P and a sixth diffusion layer (P-type) having a P-type conductivity formed at the bottom of the second PMOS load transistor (Qp21) , the fourth expansion goldenrod (N-type), are connected to each other via the fifth second silicide layer formed on the surface of the diffusion layer (N-type) and a sixth diffusion layer (P type) of
The fourth diffusion layer (N type), the fifth diffusion layer (N type), and the sixth diffusion layer (P type) connected to each other are configured to hold data stored in memory cells. Functions as the second storage node (Qb)
Wherein the sixth diffusion layer of the (P-type) first well (1a, p-well) in order to prevent leakage between the sixth diffusion layer (P-type) and the first well ( 1a, p-well), a second leak-proof diffusion layer (N-type) having a conductivity type opposite to that of the first well is formed,
The second leak preventing diffusion layer (N type) is directly connected to the fourth diffusion layer (N type) and the fifth diffusion layer ( N type). Is done.
Further, according to the present invention, for example, as described in FIG. 4d, 6 pieces of MOS transistor motor is a semiconductor memory device including a static type memory cells arranged on a substrate,
Each of the six MOS transistors is
A source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate , the columnar semiconductor layer is arranged between the source diffusion layer and the drain diffusion layer, and the columnar semiconductor layer A gate is formed on the side wall,
First and second NMOS access transistors for accessing the memory (Qn11及 beauty Qn21), first and second NMOS driver transistors for driving a memory node in order to retain data in the memory cell (Qn31 and a Qn41), acts as a first and second PMOS load transistors for supplying electric charge in order to hold the data of memory cells (Qp11 and Qp21),
The first NMOS access transistor (Qn11), a first NMOS driver transistors (Qn31) and first PMOS load transistor (Qp11) is arranged adjacent to each other,
The second NMOS access transistor (Qn21), a second NMOS driver transistors (Qn41) and second PMOS load transistor (Qp21) is arranged adjacent to each other,
Common first well (1a, N-well) in a plurality of memory cells for applying a potential to the substrate is made form,
Formed on the bottom of the first diffusion layer single lifting the first NMOS access transistor N-type conductivity type formed on the bottom of (Qn11) (3a, N-type), the first NMOS driver transistor (Qn31) second diffusion layers (5a, N-type) and the third diffusion layer having a P-type conductivity type formed on the bottom of the first PMOS of Rodoto transistor (Qp11) having N-type conductivity type ( 4a, P-type) are formed on the surfaces of the first diffusion layer (3a, N-type), second diffusion layer (5a, N-type) and third diffusion layer (4a, P-type ). Connected to each other through one silicide layer (13a),
The first diffusion layer (3a, N type), the second diffusion layer (5a, N type) and the third diffusion layer (4a, P type) connected to each other are data stored in the memory cell. functions as a first storage node (Qa) for holding,
In order to prevent leakage between the first diffusion layer (3a, N-type) and the second diffusion layer (5a, N-type) and the first well ( 1a, N-well), the first diffusion layer (3a, N-type) diffusion layers (3a, N-type) between the first wells (1a, N-well), and the second diffusion layer (5a, N-type) and the first well (1a, N-well) A first leak preventing diffusion layer (1b, P type) having a conductivity type opposite to that of the first well is formed between
The first leak preventing diffusion layer (1b, P type) is directly connected to the third diffusion layer (4a, P type) ,
Fourth diffusion layer having a second N-type conductivity type formed on the bottom of the NMOS access transistor (Qn21) (N-type), N being formed in the bottom portion of the second NMOS driver transistor (Qn41) A sixth diffusion layer (P type) having a P type conductivity type formed at the bottom of the fifth diffusion layer (N type) having the conductivity type and a second PMOS load transistor (Qp21), the fourth expansion goldenrod (N-type), are connected to each other via the fifth second silicide layer formed on surface of the diffusion layer (N-type) and a sixth diffusion layer (P type) of
The fourth diffusion layer (N-type), the fifth diffusion layer (N-type), and the sixth diffusion layer (P-type) connected to each other are configured to hold data stored in memory cells. and a second storage node (Qb) function,
In order to prevent leakage between the fourth diffusion layer (N-type) and the fifth diffusion layer (N-type) and the first well (1a, N-well ), the fourth diffusion layer during the (N-type) and the first well (1a, N -well), and between said fifth diffusion layer (N-type) and the first well (1a, N-well), the A second leak prevention diffusion layer (P type) having a conductivity type opposite to that of the first well is formed, and the second leak prevention diffusion layer (P type) is the sixth diffusion layer (P type). directly connected have a semiconductor memory device according to claim Rukoto is provided when.

In a preferred aspect of the present invention, in the semiconductor device, the first NMOS driver transistor (Qn31) formed on the diffusion layer functioning as the first storage node (Qa ) and the load of the first PMOS A gate wiring (18c) extending from the gate of the transistor (Qp11) is connected by a common contact (11a) , and the second NMOS formed on the diffusion layer functioning as the second storage node (Qb) . the driver transistor (Qn41) and the second a gate wire extending from the gate of the PMOS load transistor (Qp21) (18 d) are connected by a common contact (11b).

In another preferred aspect of the present invention, in the semiconductor device, the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors (Qn33 and Qn43) is the first and second Having a value equal to or greater than the peripheral length of the side wall of the columnar semiconductor layer forming the NMOS access transistors (Qn13 and Qn23) ;
Alternatively, the peripheral length of the side wall of the columnar semiconductor layer forming the first and second PMOS load transistors (Qp13 and Qp23) forms the first and second NMOS access transistors ( Qn13 and Qn23) . It has a value less than or equal to the peripheral length of the sidewall of the columnar semiconductor layer.

According to another preferred aspect of the present invention, in the semiconductor device, the contact (107a) formed on the gate wiring extending from the gate electrodes of the first and second NMOS access transistors (Qn12 and Qn22 ) . At least one is shared with a contact ( 107a) formed on the gate wiring extending from the gate electrode of the NMOS access transistor of the adjacent memory cell.

In still another preferred aspect of the present invention, in the plurality of semiconductor devices, the plurality of columnar semiconductor layers are arranged in a hexagonal lattice pattern.
Further, in the semiconductor device, the six MOS transistors are arranged in a matrix in the row and column directions which are perpendicular to each other Te said substrate smell,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor (Qn11) is arranged in the first row and the first column,
The first PMOS load transistor (Qp11) is arranged in the second row and the first column,
The first NMOS driver transistor (Qn31) is arranged in the third row and the first column,
The second NMOS access transistor (Qn21) is arranged in the third row and the second column,
The second PMOS load transistor (Qp21) is arranged in the second row and the second column,
The second NMOS driver transistor (Qn41) is arranged in the first row and the second column.

Further, in the semiconductor device, the six MOS transistors are arranged in a matrix in the row and column directions which are perpendicular to each other Te said substrate smell,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor (Qn15) is arranged in the first row and the first column,
The first PMOS load transistor (Qp15) is arranged in the third row and the first column,
The first NMOS driver transistor (Qn35) is arranged in the second row and the first column,
The second NMOS access transistor (Qn25) is arranged in the third row and the second column,
The second PMOS load transistor (Qp25) is arranged in the first row and the second column,
The second NMOS driver transistor (Qn45) is arranged in the second row and the second column.

Further, in the semiconductor device, the six MOS transistors are arranged in a matrix in the row and column directions which are perpendicular to each other Te said substrate smell,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor (Qn16) is arranged in the first row and the first column,
The first PMOS load transistor (Qp16) is arranged in the third row and the first column,
The first NMOS driver transistor (Qn36) is arranged in the second row and the first column,
The second NMOS access transistor (Qn26) is arranged in the first row and the second column,
The second PMOS load transistor (Qp26) is arranged in the third row and the second column,
The second NMOS driver transistor (Qn46) is arranged in the second row and the second column.

Further, in the semiconductor device, the six MOS transistors are arranged in a matrix in the row and column directions which are perpendicular to each other Te said substrate smell,
The six MOS transistors are arranged in two rows and three columns on the substrate,
The first NMOS access transistor (Qn18) is arranged in the first row and the first column,
The first PMOS load transistor (Qp18) is arranged in the second row and the second column,
The first NMOS driver transistor (Qn38) is arranged in the second row and the first column,
The second NMOS access transistor (Qn28) is arranged in the second row and the third column,
The second PMOS load transistor (Qp28) is arranged in the first row and the second column,
The second NMOS driver transistor (Qn48) is arranged in the first row and the third column.

In another preferred embodiment of the present invention, in the semiconductor device, contacts (6a, 6b, 8a, 8b, 9a, 9b) formed on the columnar semiconductor and other contacts (7a, 7b, 10a) , 10b, 11a, 11b) are formed in different etching steps.

3 is an equivalent circuit showing the SRAM of the first embodiment of the present invention. 1 is an SRAM plan view of a first embodiment of the present invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is sectional drawing of SRAM of 1st Example of this invention. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. FIG. 6 is an SRAM plan view of a second embodiment of the present invention. FIG. 6 is an SRAM plan view of a third embodiment of the present invention. It is SRAM top view of 4th Example of this invention. It is SRAM top view of the 5th Example of this invention. It is SRAM top view of the 6th Example of this invention. It is SRAM top view of the 7th Example of this invention. It is a SRAM top view of the 8th example of the present invention. It is sectional drawing of SRAM of the 8th Example of this invention. It is sectional drawing of SRAM of the 8th Example of this invention. It is sectional drawing of SRAM of the 8th Example of this invention. It is sectional drawing of SRAM of the 8th Example of this invention. It is the top view and sectional drawing which show the conventional SRAM.

[Example 1]
FIG. 1 shows an equivalent circuit diagram of a memory cell of a CMOS type 6T-SRAM used in the present invention. In FIG. 1, BL1 and BLB1 are bit lines, WL1 is a word line, Vcc1 is a power supply potential, Vss1 is a ground potential, Qn11 and Qn21 are access transistors for accessing the memory cells, and Qn31 and Qn41 are drivers for driving the memory cells. Transistors, Qp11 and Qp21 are load transistors for supplying charges to the memory cells, and Qa and Qb are storage nodes for storing data.

  As an example of the operation of the memory cell of FIG. 1, a read operation in the case where “L” data is stored in the storage node Qa and “H” data is stored in the storage node Qb will be described below. When reading is performed, the bit lines BL1 and BLB1 are precharged to the “H” potential. Data read starts when the word line WL1 becomes “H” after the precharge is completed. At this time, the access transistors Qn11 and Qn21 are turned on, and the potential of the bit line BL1 being "H" is close to the "H" potential because the storage node Qb is close to the "H" potential, so that the driver transistor Qn31 is turned on. The transistor Qn11 is discharged through the storage node Qa and the driver transistor Qn31, and approaches the “L” potential. On the other hand, the potential of the bit line BLB1 is “H” because the storage node Qa is close to the “L” potential, so that the driver transistor Qn41 is off and is not discharged, but conversely, the charge is supplied from the load transistor Qp21. “It remains close to the potential. When the potential difference between BL1 and BLB1 reaches a level that can be amplified by the sense amplifier, the sense amplifier connected to the bit line is activated, but the data in the memory cell is amplified and output. The

  FIG. 2 shows a layout diagram of the SRAM memory cell in the first embodiment of the present invention. The unit cells UC shown in FIG. 2 are repeatedly arranged in the SRAM cell array. FIGS. 3a, 3b, 3c and 3d show cross-sectional structures along cut lines A-A ', B-B', C-C 'and D-D' in the layout diagram of FIG.

First, the layout of the present invention will be described with reference to FIGS.
A P-well, which is the first well 1a, is formed in the SRAM cell array of the substrate, and the diffusion layer on the substrate is separated by element isolation 2. The first storage node Qa formed by the diffusion layer on the substrate is composed of the N + diffusion layers (3a, 5a) and the P + diffusion layer 4a, and the N + diffusion layer and the P + diffusion layer adjacent to each other are formed on the substrate surface. The second storage node Qb connected by the silicide layer 13a and formed by the diffusion layer on the substrate is composed of an N + diffusion layer, an N + diffusion layer 5b and a P + diffusion layer 4b formed below the access transistor Qn21. Adjacent N + diffusion layers and P + diffusion layers are connected by a silicide layer 13b formed on the surface of each diffusion layer. The bottom of the P + diffusion layer having the same conductivity type as the P-well which is the first well 1a has a conductivity type different from that of the first well in order to suppress leakage to the substrate. first leakage prevention diffusion layer (1b, 1c) which is disposed above are made form. The first leak preventing diffusion layer is separated into each SRAM cell by element isolation. Qn11 and Qn21 are access transistors for accessing a memory cell that is an NMOS, Qn31 and Qn41 are driver transistors that drive the memory cell that is an NMOS, and Qp11 and Qp21 are load transistors that supply charges to the memory cell that is a PMOS. .
In this embodiment, one unit cell UC includes transistors arranged in 3 rows and 2 columns on a substrate. In the first column, an access transistor Qn11, a load transistor Qp11, and a driver transistor Qn31 are arranged from the upper side of the drawing, respectively. Note that the diffusion layers 3a, 4a, and 5a arranged in the lower layers of Qn11, Qp11, and Qn31 function as the first storage node Qa. In the second column, a driver transistor Qn41, a load transistor Qp21, and an access transistor Qn21 are arranged from the upper side of the drawing. Note that the diffusion layers 3b, 4b, and 5b arranged in the lower layers of Qn41, Qp21, and Qn21 function as the second storage node Qb. The SRAM cell array of this embodiment is configured by continuously arranging unit cells UC having such six transistors in the vertical direction in the figure.
Contact 10a formed on the diffusion layer on the substrate, which is the first storage node Qa, is contact 11b formed on the gate wiring extending from the gate electrodes of driver transistor Qn41 and load transistor Qp21 by node connection wiring Na1. A contact 10b formed on the diffusion layer on the substrate which is connected and is the second storage node Qb is formed on the gate wiring extending from the gate electrodes of the driver transistor Qn31 and the load transistor Qp11 by the node connection wiring Nb1. Connected to the contact 11a. Contact 6a formed on access transistor Qn11 is connected to bit line BL1, and contact 6b formed on access transistor Qn21 is connected to bit line BLB1. Contact 7a formed on the gate wiring extending from the gate electrode of access transistor Qn11 and contact 7b formed on the gate wiring extending from the gate electrode of access transistor Qn21 are connected to word line WL1. The contacts (8a, 8b) formed on the driver transistors (Qn31, Qn41) are respectively connected to the wiring layers (Vss1a, Vss1b) having the ground potential, and the contacts (9a) formed on the load transistors (Qp11, Qp21). 9b) is connected to the wiring layer Vcc1 which is the power supply potential.
The word line wiring, bit line wiring, power supply potential wiring, and ground potential wiring are preferably higher than the node connection wiring that is the wiring in each memory cell in order to share with the wiring of other memory cells. Connected in layers.
As an example of the above-described hierarchical wiring configuration, the node connection wiring (Na1), the node connection wiring (Nb1), and the ground potential wiring (Vss1a, Vss1b) is wired in a lower layer than the bit lines (BL1, BLB1) and the power supply potential wiring (Vcc1), and the word line (WL1) is wired from the bit lines (BL1, BLB1) and the power supply potential wiring (Vcc1). A configuration in which wiring is performed in an upper layer can be realized.

FIG. 2 shows the N + implantation region (24a, 24b) and the P + implantation region 25. In the SRAM cell array region of this embodiment, the pattern for forming the N + implantation region (24a, 24b) and the P + implantation region 25 is formed by simple lines and spaces. Therefore, the influence of the dimensional deviation and alignment deviation is small, and the margin of the dimension in the vicinity of the boundary between the N + implantation region and the P + implantation region can be suppressed to the minimum. In the drawing, the length of the SRAM cell in the vertical direction This is effective in reducing (the length in the connecting direction of each SRAM cell).
Further, in this embodiment, since the shape of the storage node and the gate wiring shown in the layout of FIG. 2 is composed only of a rectangular shape, it is easy to correct the pattern shape by OPC (Optical Proximity Correction). The layout is suitable for realizing a small SRAM cell area.

  In the present invention, the source and drain of each transistor constituting the SRAM are defined as follows. For the driver transistors (Qn31, Qn41), a diffusion layer formed above the columnar semiconductor layer connected to the ground voltage is defined as a source diffusion layer, and a diffusion layer formed below the columnar semiconductor layer is defined as a drain diffusion layer. . For the load transistors (Qp11, Qp21), the diffusion layer formed above the columnar semiconductor layer connected to the power supply voltage is defined as the source diffusion layer, and the diffusion layer formed below the columnar semiconductor layer is defined as the drain diffusion layer. . For the access transistor, depending on the operating state, both the diffusion layer formed above the columnar semiconductor layer and the diffusion layer formed below are the source or drain, but for convenience, the diffusion formed above the columnar semiconductor layer. The layer is defined as a source diffusion layer, and the diffusion layer formed below the columnar semiconductor layer is defined as a drain diffusion layer.

  Next, the structure of the SRAM of the present invention will be described with reference to the cross-sectional structure of FIG. As shown in FIG. 3 a, a P-well which is the first well 1 a is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation 2. An N + drain diffusion layer 3a is formed by impurity implantation or the like in the first storage node Qa formed by the diffusion layer on the substrate, and impurity implantation or the like is performed by the second storage node Qb formed by the diffusion layer on the substrate. Thus, the N + drain diffusion layer 5b is formed. Silicide layers (13a, 13b) are formed on the N + drain diffusion layers (3a, 5b). Columnar silicon layer 21a constituting access transistor Qn11 is formed on N + drain diffusion layer 3a, and columnar silicon layer 22b constituting driver transistor Qn41 is formed on N + drain diffusion layer 3b. A gate insulating film 17 and a gate electrode 18 are formed around each columnar silicon layer. An N + source diffusion layer 14 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 15 is formed on the surface of the source diffusion layer. Contact 6a formed on access transistor Qn11 is connected to bit line BL1, and contact 7a formed on gate line 18a extending from the gate of access transistor Qn11 is connected to word line WL1, and on driver transistor Qn41. The formed contact 8b is connected to the ground potential wiring Vss1.

  As shown in FIG. 3 b, a P-well which is the first well 1 a is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation 2. An N + drain diffusion layer 3a is formed by impurity implantation or the like in the first storage node Qa formed by the diffusion layer on the substrate, and impurity implantation or the like is performed by the second storage node Qb formed by the diffusion layer on the substrate. Thus, the N + drain diffusion layer 5b is formed. Silicide layers (13a, 13b) are formed on the N + drain diffusion layer. Contact 10a formed on drain diffusion layer 3a is formed on the boundary between N + drain diffusion layer 3a and P + drain diffusion layer 4a, and extends from the gate electrodes of driver transistor Qn41 and load transistor Qp21 through storage node connection wiring Na1. It is connected to a contact 11b formed on the gate wiring 18d.

As shown in FIG. 3 c, a P-well which is a first well is formed on the substrate, and the diffusion layer on the substrate is separated by element isolation 2. A P + drain diffusion layer 4a is formed by impurity implantation or the like in the first storage node Qa formed by the diffusion layer on the substrate, and impurity implantation or the like is performed by the second storage node Qb formed by the diffusion layer on the substrate. Thus, the N + drain diffusion layer 4b is formed. Silicide layers (13a, 13b) are formed on the surface of the P + drain diffusion layers (4a, 4b). To the bottom of the P + diffusion layer 4a having a first same conductivity type as the well to suppress the leakage to the substrate, the first rie click preventing diffusion layer 1b having a different conductivity type as the first well It is formed, for the bottom of the P + diffusion layer 4b having a first well same conductivity type as to inhibit leakage to the substrate, a different conductivity type as the first well, over the first well A second leak preventing diffusion layer 1c is formed .
A columnar silicon layer 23a constituting the load transistor Qp11 is formed on the P + drain diffusion layer 4a, and a columnar silicon layer 23b constituting the load transistor Qp21 is formed on the P + drain diffusion layer 4b. A gate insulating film 17 and a gate electrode 18 are formed around each columnar silicon layer. A P + source diffusion layer 16 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 15 is formed on the surface of the source diffusion layer. The contacts (9a, 9b) formed on the load transistors (Qp11, Qp21) are both connected to the power supply potential wiring Vcc1 through the wiring layer.

As shown in FIG. 3 d, a P-well which is a first well is formed on the substrate, and the diffusion layer on the substrate is separated by element isolation 2. In the first storage node Qa formed by the diffusion layer on the substrate, the N + drain diffusion layers (3a, 5a) and the P + drain diffusion layer 4a are formed by impurity implantation or the like. A silicide layer 13a is formed on the drain diffusion layer, and the N + drain diffusion layers (3a, 5a) and the P + drain diffusion layer 4a are directly connected by the silicide layer 13a. For this reason, it is not necessary to form element isolation for separating the N + drain diffusion layer and the P + drain diffusion layer and to form a contact for connecting the N + drain diffusion layer and the P + drain diffusion layer, so that the memory cell area can be reduced. . At the bottom of the P + diffusion layer 4a having the same conductivity type as that of the first well, a first leak prevention diffusion layer 1b having a conductivity type different from that of the first well 1a is formed in order to suppress leakage to the substrate. Is done .
Columnar silicon layer 21a constituting access transistor Qn11 is formed on N + drain diffusion layer 3a, columnar silicon layer 22a constituting driver transistor Qn31 is formed on N + drain diffusion layer 5a, and loaded on P + drain diffusion layer 4a. A columnar silicon layer 23a constituting the transistor Qp11 is formed. The N + drain diffusion layer 3a, the P + drain diffusion layer 4a, and the N + drain diffusion layer 5a are directly connected by a silicide layer 13a formed on the surface of each diffusion layer. A gate insulating film 17 and a gate electrode 18 are formed around each columnar silicon layer. A source diffusion layer is formed on each columnar silicon layer by impurity implantation or the like, and a silicide layer 15 is formed on the surface of the source diffusion layer. Contact 6a formed on access transistor Qn11 is connected to bit line BL1, contact 8a formed on driver transistor Qn31 is connected to power supply potential wiring Vss1a, and contact 9a formed on load transistor Qp11 is power supply potential. Connected to the wiring Vcc1.
The gate electrodes of the driver transistor Qn31 and the load transistor Qp11 are connected to a common contact 11a on the gate wiring 18c extending from them. Contact 11a is connected to contact 10b formed on the drain diffusion layer of storage node 2b through storage node connection line Nb1. Contact 10a formed on the boundary between drain diffusion layers 3a and 4a is connected to contact 11b formed on gate wiring 18d extending from the gate electrodes of driver transistor Qn41 and load transistor Qp21 through storage node connection wiring Na1. .

In the present invention, the N + drain diffusion layer and the P + drain diffusion layer formed on the substrate are directly connected by the silicide layer formed on the surface of the diffusion layer, so that the drain diffusion of the access transistor, driver transistor, and load transistor is performed. The layers are shared and function as a storage node of the SRAM. This eliminates the need for element isolation for separating the N + source / drain diffusion layer and the P + source / drain diffusion layer, which are normally required for planar transistors, and element isolation is sufficient to separate the two storage nodes of the SRAM. Therefore, a very small SRAM cell area can be realized. The drain diffusion layer having the same conductivity type as the first well has a conductivity type opposite to that of the first well at the bottom of each drain diffusion layer and is shallower than the first well and the second leak prevention diffusion layer and the second well. by leakage preventing diffusion layer is made form, thereby suppressing the leakage to the substrate.

As shown in FIG. 4, even in a structure in which the first well 1a is an N-well and the first leakage preventing diffusion layer 1b and the second leakage preventing diffusion layer 1c are formed at the bottom of the N + diffusion layer. Similarly, an SRAM cell can be formed.

  An example of a manufacturing method for forming the semiconductor device of the present invention will be described below with reference to FIGS. In each figure, (a) is a plan view and (b) is a cross-sectional view taken along D-D '.

  As shown in FIG. 5, a mask 19 such as a silicon nitride film is formed on the substrate. Then, the columnar silicon layers (21a-23a, 21b-23b) are formed by forming patterns of the columnar silicon layers (21a-23a, 21b-23b) by lithography and etching. Subsequently, a P-well which is the first well 1a is formed in the SRAM cell array by impurity implantation or the like.

  As shown in FIG. 6, element isolation 2 is formed. The element isolation is formed by first etching the groove pattern, embedding an oxide film in the groove pattern by applying silica or CVD, and removing the excess oxide film on the substrate by dry etching or wet etching. Thereby, the pattern of the diffusion layer that becomes the first storage node Qa and the second storage node Qb is formed on the substrate.

As shown in FIG. 7, impurities are introduced into the N + implantation regions 24a and 24b and the P + implantation region 25 by ion implantation or the like to form drain diffusion layers (3a, 4a, 5a) below the columnar silicon layer on the substrate. To do. At the bottom of the P + diffusion layer 4a having the same conductivity type as the P-well which is the first well 1a, a first leak prevention diffusion layer 1b is formed in order to suppress leakage to the substrate. The first leak preventing diffusion layer 1b can be formed by performing impurity implantation using a mask of the P + implantation region 25. The first leak preventing diffusion layer is separated into each SRAM cell by element isolation.

  As shown in FIG. 8, a gate insulating film 17 and a gate conductive film 18 are formed. The gate insulating film 17 is formed of an oxide film or a high-k film. The gate conductive film is formed of a metal film of polysilicon.

  As shown in FIG. 9, a gate wiring pattern is formed by lithography using a resist 33 or the like.

  As shown in FIG. 10, the gate conductive film 17 and the gate insulating film 18 are etched and removed using the resist 33 as a mask. Thereby, gate wirings (18a to 8d) are formed. Thereafter, the mask 19 on the pillar is removed.

  As shown in FIG. 11, after an insulating film such as a silicon nitride film is formed, it is etched back so that the sidewall of the columnar silicon layer and the sidewall of the gate electrode are covered with an insulating film 34 such as a silicon nitride film.

  As shown in FIG. 12, impurities are introduced into the N + implantation region and the P + implantation region by ion implantation or the like to form source diffusion layers (14, 16) above the columnar silicon layer.

As shown in FIG. 13, by sputtering a metal such as Co or Ni and performing heat treatment, the source / drain diffusion layer is selectively silicided to form silicide layers (13a, 13b) on the drain diffusion layer and A silicide layer 15 on the source diffusion layer above the columnar silicon layer is formed.
Here, the insulating layer 34 such as a silicon nitride film covering the side walls of the columnar silicon layer and the gate electrode can suppress a drain-gate and source-gate short circuit due to the silicide layer.

  As shown in FIG. 14, contacts (6a to 10a, 6b to 10b) are formed after forming a silicon oxide film as an interlayer film.

  At the time of contact formation, contacts on the pillars are formed by the first lithography and etching as shown in FIG. 15, and other contacts are formed by the second lithography and etching as shown in FIG. As a result, the minimum distance between the contact on the pillar and the other contact can be reduced, and the SRAM cell area can be further reduced.

[Example 2]
FIG. 17 shows the SRAM cell layout of this embodiment. In the present embodiment, the transistor arranged in the first column of the unit cell UC in FIG. 17 in the SRAM cell array is the transistor arranged in the second column of the memory cell adjacent to the upper side or the lower side of the unit cell UC. The transistors arranged in the second column of the unit cell UC have the same arrangement configuration, and the transistors arranged in the first column of the memory cells adjacent to the upper side or the lower side of the unit cell UC have the same arrangement configuration. That is, the same transistors as the transistors Qn42, Qp22, and Qn22 arranged in the second column are arranged in order from the top above the transistors Qn12, Qp12, and Qn32 arranged in the first column of the unit cell UC of FIG. Therefore, an access transistor is arranged adjacent to the upper side of the access transistor Qn12 in the drawing, and an access transistor is arranged adjacent to the lower side of the access transistor Q22 in the drawing. By arranging the SRAM cell in this way, the gate wiring extending from the gate electrode of the access transistor Qn12 is connected to the gate electrode of the access transistor of the adjacent memory cell on the upper side of the drawing, and connected to the word line (WL2). Contacts (107a, 107b) can be shared on the gate wiring. In the first embodiment, the contacts (107a, 107b) to the word line (WL2) are formed between the first storage node and the second storage node, but in this embodiment, the upper and lower SRAM cells. , The space between the storage nodes can be reduced. In the drawing, the lateral length of the SRAM cell can be reduced.
Note that the sharing of the contact between the gate electrodes of the access transistors described above can also be applied to the case where the transistors are arranged as in the first embodiment. For example, the gate wiring extends from the gate electrode of the access transistor Qn11 in FIG. 2 in the diagonally upper right direction in the drawing, and the gate wiring extends in the diagonally downward left direction from the gate electrode of the access transistor disposed in the diagonally upper right direction of Qn11. It is also possible to connect to the gate wiring extended to the gate wiring and share the contact on the connected gate wiring. As described above, as long as the access transistors of adjacent memory cells are configured so that the gate electrodes are arranged adjacent to each other, the contact to the word line can be shared.
Further, as described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with other memory cell wirings. Arranged in a layer above the node connection wiring which is the wiring in the memory cell. In this regard, as an example of the hierarchical wiring configuration, the node connection wiring (Na2, Nb2) is the lower layer and the word line (WL2) is the middle so that each wiring does not contact the contact that should not contact It is possible to realize a configuration in which the bit line wiring (BL2, BLB2), the power supply potential wiring (Vcc2), and the ground potential wiring (Vss2a, Vss2b) are wired in the upper layer.
Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

[Example 3]
FIG. 18 shows the SRAM layout of this embodiment. This embodiment is different from the second embodiment in that the shape of the columnar silicon layer forming the driver transistor is different. In 6T-SRAM, the drain current of the driver transistor is often set larger than that of the normal access transistor in order to ensure an operation margin during normal reading. In the case of a planar transistor, the drain current can be increased by making the diffusion layer width of the driver transistor larger than the diffusion layer width of the access transistor. However, when SGT is used, the diameter of the columnar silicon layer is increased. Thus, the drain current can be increased by making the peripheral length of the sidewall of the columnar silicon layer forming the driver transistor equal to or greater than the peripheral length of the sidewall of the columnar silicon layer forming the access transistor. As shown in FIG. 18, the read margin can be improved by making the diameter of the columnar silicon layer forming the driver transistor larger than that of the other columnar silicon layers. However, care should be taken because the short channel effect is likely to occur when the size of the columnar silicon layer is increased. The shape of the columnar silicon layer is not limited to a circle, but the perimeter of the columnar silicon layer may be increased by forming an elliptical or rectangular shape.
In order to increase the operating speed, the access transistor diameter is increased to increase the drain current value of the access transistor. To improve the write margin, the load transistor diameter is decreased to reduce the load transistor drain current. The peripheral length of the side wall of the columnar silicon layer forming the load transistor may be set to be equal to or less than the peripheral length of the side wall of the columnar silicon layer forming the access transistor. Thus, various SRAM characteristics can be adjusted by changing the shapes of the access transistor, driver transistor, and load transistor.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. Arranged in a layer above the node connection wiring which is the wiring in the memory cell. In this regard, as a hierarchical wiring configuration, for example, the same configuration as that of the second embodiment can be realized.
Since the other points are the same as the configuration shown in the second embodiment, description thereof is omitted.

[Example 4]
FIG. 19 shows the SRAM cell layout of this embodiment. In this embodiment, the difference from the second embodiment is that in this embodiment, the diffusion layer on the substrate, which is a storage node, and the gate wiring are connected by a common contact formed across both. Referring to FIG. 19, the diffusion layer on the substrate which is storage node Qa4 and the gate wiring extending from the gate electrodes of driver transistor Qn44 and load transistor Qp24 are connected by a common contact 310a formed over both of them, The diffusion layer on the substrate, which is storage node Qb4, and the gate wiring extending from the gate electrodes of driver transistor Qn34 and load transistor Qp14 are connected by a common contact 310b formed across both. As described above, the number of contacts in the SRAM cell can be reduced by connecting the gate and the storage node with the contact instead of the wiring layer. Therefore, the cell area can be reduced by adjusting the arrangement of the columnar silicon layer and the contact. can do. In particular, the cell area can be reduced by forming the contact formed on the pillar and the common contact (310a, 310b) by different lithography and etching processes. In this case, the common contact 310a is disposed near the center of the four pillar contacts (306a, 308b, 309a, 309b), and the common contact 310b is disposed on the four pillar contacts (306b, 308a, 309a, 309b). As a result, the space between the contact on the pillar and the common contact can be made smaller than the minimum space that can be formed by the same process, and the cell area can be reduced.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. It is arranged in a layer above the node connection wiring which is a wiring in the memory cell, that is, in a layer above the contact 310a and the contact 310b.
Since the other points are the same as the configuration shown in the second embodiment, description thereof is omitted.

[Example 5]
FIG. 20 shows the SRAM cell layout of this embodiment. This embodiment is different from the second embodiment in that the arrangement of the driver transistor and the load transistor is switched. In this embodiment, since the driver transistor and the load transistor are interchanged, there is only one boundary between the N + implantation region and the P + implantation regions (425a, 425b) crossing the diffusion layer on the substrate which is the storage node. For this reason, the length of the SRAM cell in the vertical direction can be reduced because there is only one place where an overlap margin needs to be secured in the vicinity of the boundary between the N + implantation region and the P + implantation region. However, as in the layout of the first embodiment, the N + implantation region and the P + implantation region are not simple lines and spaces, the P + implantation region (425a, 425b) is a rectangular groove pattern, and the N + implantation region is a P + implantation region ( 425a and 425b) are inverted patterns. For this reason, when patterning the implantation region, precise control of the resist pattern is required.
In the present embodiment, the arrangement of the power supply wiring (Vcc5a, Vcc5b) and the ground wiring Vss5 is exchanged with that in the second embodiment in accordance with the arrangement of the driver transistor and the load transistor.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. Arranged in a layer above the node connection wiring which is the wiring in the memory cell. In this regard, as a hierarchical wiring configuration, for example, the same configuration as that of the second embodiment can be realized.
Since the other points are the same as the configuration shown in the second embodiment, description thereof is omitted.

[Example 6]
FIG. 21 shows the SRAM cell layout of this embodiment. This embodiment is different from the second embodiment in that the arrangement of the transistors constituting the SRAM is different. In this embodiment, since the arrangement of the transistors is changed, there is only one boundary line between the N + implantation region 524 and the P + implantation region 525 that crosses the diffusion layer on the substrate that is the storage node. For this reason, since there is only one place where the overlap margin must be secured near the boundary between the N + implantation region and the P + implantation region, the length of the SRAM cell in the vertical direction can be reduced. Further, as in the first embodiment, the N + implantation region 524 and the P + implantation region 525 are formed by simple lines and spaces. For this reason, since the margin of the size near the boundary between the N + implantation region and the P + implantation region can be minimized, the length of the SRAM cell in the vertical direction can be further reduced as compared with the fifth embodiment. Since the access transistors (Qn16, Qn26) are adjacent to each other, the contacts formed on these gate electrodes can be shared.
As shown in FIG. 21, the first storage node 502a formed by the diffusion layer on the substrate and the gate wiring extending from the gate electrodes of the driver transistor Qn46 and the load transistor Qp26 are connected by a common contact 510a. The contact 510b formed on the second storage node 502b formed by the diffusion layer on the substrate is connected to the contact 511a by the node connection wiring Nb6 which is the first layer wiring. As described above, in this embodiment, the SRAM cell wiring method is asymmetrical in the left and right, and therefore, the SRAM characteristic may be asymmetrical in the lateral direction. If the SRAM characteristics become asymmetrical, the SRAM operating margin is degraded. In this embodiment, attention must be paid to the asymmetry of the SRAM characteristics.
In this embodiment, unlike the previous embodiments, the word line WL6 is wired in the horizontal direction, and the bit lines (BL8, BLB8) are wired in the vertical direction. Further, since two driver transistors (Qn36, Qn46) and two load transistors (Qp16, Qp26) are formed on the same column, they are connected to the power supply wiring Vcc6 and the ground wiring Vss6 with a simple layout. Can do.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. Arranged in a layer above the node connection wiring which is the wiring in the memory cell. In this regard, as an example of the hierarchical wiring configuration, the node connection wiring (Na6, Nb6) is the lower layer, and the word line (WL6), the power supply potential wiring (Vcc6), and the ground potential wiring (Vss6) are medium. It is possible to realize a configuration in which the bit line wirings (BL6, BLB6) are wired in the upper layer in the upper layer.

[Example 7]
FIG. 22 shows the SRAM cell layout of this embodiment. This embodiment is different from the other embodiments in that the columnar semiconductors are arranged in a hexagonal lattice so as to be arranged in the closest packing. By arranging the columnar semiconductors in this way, the columnar semiconductors can be arranged in a balanced manner in the smallest area, and a small SRAM cell area can be designed. The arrangement of the transistors is not limited to that shown in FIG.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. Arranged in a layer above the node connection wiring which is the wiring in the memory cell. In this regard, as a hierarchical wiring configuration, for example, the same configuration as that of the second embodiment can be realized.

[Example 8]
FIG. 23 shows a cell layout of this embodiment. The unit cells shown in FIG. 23 are repeatedly arranged in the SRAM cell array. 24A, 24B, 24C, and 24D show cross-sectional structures taken along cut lines AA ′, BB ′, CC ′, and DD ′ in the layout diagram of FIG. 23, respectively.

First, the layout of the present invention will be described with reference to FIGS.
This embodiment is different from the other embodiments in that the layout of the diffusion layer on the substrate which is a storage node is L-shaped. Regarding the patterning of the diffusion layer on the substrate as the storage node, it is easier to form a rectangular shape as in the other embodiments. However, in this embodiment, like the fifth and sixth embodiments, there is only one boundary line between the N + implantation region (724a, 724b) and the P + implantation region 725 crossing the storage node, and the N + implantation region (724a, 724a, 724b) and the pattern forming the P + implantation region 725 is formed by simple lines and spaces. For this reason, since the margin of the dimension near the boundary between the N + implantation regions (724a, 724b) and the P + implantation region 725 can be minimized, a small area SRAM cell can be designed.
In this embodiment, the word line WL8 is wired in the horizontal direction, and the bit lines (BL8, BLB8) are wired in the vertical direction. Although contacts (707a, 707b) to the gates of the access transistors connected from the bit lines are not shown in the figure, they can be shared with memory cells adjacent in the horizontal direction. The diffusion layer on the substrate of storage node Qa7 and the gate wiring extending from the gate electrodes of driver transistor Qn48 and load transistor Qp28 are connected by a common contact 710a formed over both of them, and on the substrate of storage node Qb7. The diffusion layer and the gate wiring extending from the gate electrodes of driver transistor Qn38 and load transistor Qp18 are connected by a contact 710b formed across both.
As described in the first embodiment, the word line wiring, the bit line wiring, the power supply potential wiring, and the ground potential wiring are preferably used in common with the wiring of other memory cells. It is arranged in a layer above the node connection wiring which is a wiring in the memory cell, that is, in a layer above the contact 707a and the contact 707b. In this regard, as an example of a hierarchical wiring configuration, the node connection wiring is a lower layer, the word line (WL8) and the ground potential wiring (Vss8a, Vss8b) are the middle layer, and the bit line wiring (BL8 , BLB8) and the wiring of the power supply potential (Vcc8) can be realized in an upper layer.

Next, the structure of the SRAM of the present invention will be described with reference to the cross-sectional structure of FIG.
As shown in FIG. 24A, a P-well which is a first well 701a is formed on a substrate, and a diffusion layer on the substrate is separated by element isolation 702. An N + drain diffusion layer 703a is formed by impurity implantation or the like in the first storage node Qa7 formed by the diffusion layer on the substrate, and an impurity is added in the second storage node Qb7 formed by the diffusion layer on the substrate. An N + drain diffusion layer 703b and a P + drain diffusion layer 704b are formed by implantation or the like. Further, a second leak prevention diffusion layer having a conductivity type different from that of the first well 701a is provided at the bottom of the P + diffusion layer 704b having the same conductivity type as that of the first well 701a in order to suppress leakage to the substrate. 701c is formed .
Silicide layers (713a, 713b) are formed on the surface of the drain diffusion layers (703a, 703b, 704b), and the N + diffusion layer 703b and the P + diffusion layer 704b are not shown in the figure, but are formed by the silicide layer 713b. It is connected. A columnar silicon layer 721a constituting the access transistor Qn18 is formed on the N + drain diffusion layer 703a, a columnar silicon layer 723b constituting the load transistor Qp28 is formed on the P + drain diffusion layer 704b, and a driver is formed on the N + drain diffusion layer 703b. A columnar silicon layer 722b constituting the transistor Qn48 is formed. A gate insulating film 717 and a gate electrode 718 are formed around each columnar silicon layer. A source diffusion layer (714, 716) is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 715 is formed on the surface of the source diffusion layer. Contact 706a formed on access transistor Qn18 is connected to bit line BL8, and contact 707a formed on gate wiring 718a extending from the gate electrode of access transistor Qn18 is connected to word line WL8, and on load transistor Qp28. The contact 708b formed on the gate electrode is connected to the power supply potential wiring Vcc8, the contact 709b formed on the driver transistor Qn48 is connected to the ground potential wiring Vss8, and the gate electrodes of the load transistor Qp28 and the driver transistor Qn48 are connected to the respective gate electrodes. They are connected to each other by an extended gate wiring 718d.

  As shown in FIG. 24B, a P-well which is the first well 701a is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation 702. An N + drain diffusion layer 703a is formed by impurity implantation or the like in the first storage node Qa7 formed by the diffusion layer on the substrate, and impurity implantation or the like is performed by the second storage node Qb7 formed by the diffusion layer on the substrate. As a result, an N + drain diffusion layer 703b is formed, and silicide layers (713a, 713b) are formed on the N + drain diffusion layer. The drain diffusion layer 703a and the gate wiring 718f are connected by a common contact 710a formed across both, and the drain diffusion layer 703b and the gate wiring 718e are connected by a common contact 710b formed across both.

  As shown in FIG. 24C, a P-well which is the first well 701a is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation 702. An N + drain diffusion layer 703a is formed by impurity implantation or the like on the first storage node Qa7 formed by the diffusion layer on the substrate, and a silicide layer 713a is formed on the surface of the N + drain diffusion layer 703a. A columnar silicon layer 721a constituting the access transistor Qn18 and a columnar silicon layer 722a constituting the driver transistor Qn38 are formed on the N + drain diffusion layer 703a. A gate insulating film 717 and a gate electrode 718 are formed around each columnar silicon layer. An N + source diffusion layer 714 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 715 is formed on the surface of the source diffusion layer. Contact 706a formed on access transistor Qn18 is connected to bit line BL8, and contact 709a formed on driver transistor Qn38 is connected to ground potential wiring Vss8 through a wiring layer.

As shown in FIG. 24D, a P-well which is the first well 701a is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation 702. An N + drain diffusion layer 703a is formed by impurity implantation or the like in the first storage node Qa7 formed by the diffusion layer on the substrate, and impurity implantation or the like is performed by the second storage node Qb7 formed by the diffusion layer on the substrate. As a result, an N + drain diffusion layer 703b is formed. In addition, a first leak prevention diffusion layer having a conductivity type different from that of the first well 701a is provided at the bottom of the P + diffusion layer 704a having the same conductivity type as that of the first well 701a in order to suppress leakage to the substrate. 701b is formed , and a second leak having a conductivity type different from that of the first well 701a is formed at the bottom of the P + diffusion layer 704b having the same conductivity type as the first well 701a in order to suppress leakage to the substrate. A prevention diffusion layer 701c is formed . A columnar silicon layer 723b constituting the load transistor Qp28 is formed on the drain diffusion layer 704b, and a columnar silicon layer 723a constituting the load transistor Qp18 is formed on the drain diffusion layer 704a. A gate insulating film 717 and a gate electrode 718 are formed around each columnar silicon layer, a P + source diffusion layer 716 is formed on each columnar silicon layer by impurity implantation, and a silicide layer 715 is formed on the surface of the source diffusion layer. Is formed. Contacts (708b, 708a) formed on load transistor Qp28 and load transistor Qp18 are connected to power supply potential wiring Vcc8.

  In this embodiment, as in the previous embodiments, the N + drain diffusion layer and the P + drain diffusion layer formed at the storage node on the substrate are directly connected by the silicide layer formed on the surface of each diffusion layer. Thus, the drain diffusion layers of the access transistor, driver transistor, and load transistor are shared, and function as a storage node of the SRAM. This eliminates the need for element isolation for separating the N + source / drain diffusion layer and the P + source / drain diffusion layer, which are normally required for planar transistors, and element isolation is sufficient to separate the two storage nodes of the SRAM. Therefore, a very small SRAM cell area can be realized.

As described above, according to the present invention, in a static memory cell configured using six MOS transistors, the MOS transistor is formed of an SGT in which a drain, a gate, and a source are arranged in a vertical direction. A first well is formed, and the N + source diffusion layer and the P + source diffusion layer formed on the substrate are directly connected by a silicide layer formed on the surface thereof, and have the same conductivity type as the first well. The drain diffusion layer has a conductivity type opposite to that of the first well at the bottom of each drain diffusion layer, and functions as an SRAM storage node by forming first and second leak prevention diffusion layers shallower than the first well. . This eliminates the need for element isolation for separating the N + source / drain diffusion layer and the P + source / drain diffusion layer, which are normally required in a planar transistor, and the element isolation can be achieved by simply separating the two storage nodes of the SRAM. Since it is sufficient, a CMOS 6T-SRAM having a very small memory cell area can be realized.

Qa, Qa2, Qa3, Qa4, Qa5, Qa6, Qa7: first storage nodes Qb, Qb2, Qb3, Qb4, Qb5, Qb6, Qb7: second storage nodes 1a, 101a, 201a, 301a, 401a, 501a, 601a, 701a: first well 1b, 701b: first leak prevention diffusion layer 1c, 701c: second leak prevention diffusion layer 2, 102, 202, 302, 402, 502, 602, 702: element isolation 3a, 103a, 203a, 303a, 403a, 503a, 603a, 703a, 3b, 103b, 203b, 303b, 403b, 503b, 603b, 703b: N + drain diffusion layers 4a, 104a, 204a, 304a, 404a, 504a, 604a, 704a, 4b, 104b, 204b, 304b, 404b, 5 4b, 604b, 704b: P + drain diffusion layers 5a, 105a, 205a, 305a, 405a, 505a, 605a, 5b, 105b, 205b, 305b, 405b, 505b, 605b: N + drain diffusion layers 6a, 106a, 206a, 306a, 406a, 506a, 606a, 706a, 6b, 106b, 206b, 306b, 406b, 506b, 606b, 706b: Access transistor source diffusion layer contact 7a, 107a, 207a, 307a, 407a, 507a, 607a, 707a, 7b, 107b , 207b, 307b, 407b, 507b, 607b, 707b: Access transistor word line contacts 8a, 108a, 208a, 308a, 408a, 508a, 608a, 708a, 8b 108b, 208b, 308b, 408b, 508b, 608b, 708b: Load transistor source diffusion layer contact 9a, 109a, 209a, 309a, 409a, 509a, 609a, 709a, 9b, 109b, 209b, 309b, 409b, 509b, 609b 709b: Driver transistor source diffusion layer contacts 10a, 110a, 210a, 310a, 410a, 510a, 610a, 710a, 10b, 110b, 210b, 310b, 410b, 510b, 610b, 710b: Contacts on drain diffusion layers 11a, 111a 211a, 311a, 411a, 511a, 611a, 711a, 11b, 111b, 211b, 311b, 411b, 511b, 611b, 711b: contact on the gate wiring 13a, 13b, 15, 713a, 713b, 715: silicide layer 14, 714: N + source diffusion layer 16, 716: P + source diffusion layer 17, 717: gate insulating film 18, 718: gate electrodes 18a, 18b, 18c, 18d, 718a, 718d, 718e, 18f: Gate wiring 19: Silicon nitride film masks 21a, 21b, 721a, 721b: Access transistor columnar silicon layers 22a, 22b, 722a, 722b: Driver transistor columnar silicon layers 23a, 23b, 723a 723b: Load transistor columnar silicon layers 24a, 124a, 224a, 324a, 524, 724a, 24b, 124b, 224b, 324b, 724b: N + implantation regions 25, 125, 225, 325, 425a, 425b, 525, 6 5a, 625b, 725: P + implantation region 33: resist 34: insulating film Qa such as silicon nitride film, Qb: storage nodes Qn11, Qn21, Qn12, Qn22, Qn13, Qn23, Qn14, Qn24, Qn15, Qn25, Qn16, Qn26 Qn17, Qn27, Qn18, Qn28: Access transistors Qn31, Qn41, Qn32, Qn42, Qn33, Qn43, Qn34, Qn44, Qn35, Qn45, Qn36, Qn46, Qn37, Qn47, Qn38, Qn48: Driver transistors Qp11, Qp21, Qp12 Qp22, Qp13, Qp23, Qp14, Qp24, Qp15, Qp25, Qp16, Qp26, Qp17, Qp27, Qp18, Qp28: Load transistors BL1, BL2, BL3, L4, BL5, BL6, BL7, BL8, BLB1, BLB2, BLB3, BLB4, BLB5, BLB6, BLB7, BLB8: bit lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8: word lines Vcc1, Vcc2, Vcc3, Vcc4, Vcc5a, Vcc5b, Vcc6, Vcc7, Vcc8: power supply lines Vss1a, Vss1b, Vss2a, Vss2b, Vss3a, Vss3b, Vss4a, Vss4b, Vss5, Vss6, Vss7a, Vss7b, Vss8a, Vss8a, Vss8a

Claims (16)

A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
Each of the six MOS transistors is
First and second NMOS access transistors for accessing the memory, first and second NMOS driver transistors for driving the storage node to hold the memory cell data, and holding the memory cell data Functioning as first and second PMOS load transistors for supplying charge to
In the first and second NMOS access transistors for accessing the memory ,
A first diffusion layer having an N-type conductivity , a first columnar semiconductor layer, and a second diffusion layer having an N-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on the substrate. The first columnar semiconductor layer is disposed, and the first diffusion layer formed on the bottom of the first columnar semiconductor layer and the second diffusion layer formed on the top of the first columnar semiconductor layer And a gate is formed on a side wall of the first columnar semiconductor layer,
In the first and second NMOS driver transistors that drive the storage node to hold the memory cell data ,
A third diffusion layer having an N-type conductivity type, a second columnar semiconductor layer, and a fourth diffusion layer having an N-type conductivity type are hierarchically arranged in a vertical direction on an insulating film formed on the substrate. The second columnar semiconductor layer is disposed, and the third diffusion layer is formed at the bottom of the second columnar semiconductor layer, and the fourth diffusion layer is formed on the second columnar semiconductor layer. And a gate is formed on a side wall of the second columnar semiconductor layer,
In the first and second PMOS load transistors that supply charge to hold the memory cell data ,
A fifth diffusion layer having a P-type conductivity type, a third columnar semiconductor layer, and a sixth diffusion layer having a P-type conductivity type are arranged hierarchically in a vertical direction on an insulating film formed on the substrate. The third columnar semiconductor layer is formed of the fifth diffusion layer formed on the bottom of the third columnar semiconductor layer and the sixth diffusion layer formed on the third columnar semiconductor layer. And a gate is formed on a side wall of the third columnar semiconductor layer,
It said first NMOS access transistor, load transistor of said first NMOS driver transistor and the first PMOS are arranged adjacent to each other,
It said second NMOS access transistor, the second NMOS driver transistor and the load transistor of the second PMOS are arranged adjacent to each other,
A first well common to a plurality of memory cells for applying a potential to the substrate is formed;
Wherein with the first diffusion layer, N-type conductivity type formed on the bottom of the driver transistor of said first NMOS with N-type conductivity type formed on the bottom of the access transistor of the first NMOS It said fifth diffusion layer having a third diffusion layer and P-type conductivity type formed on the bottom of the first PMOS load transistor, said first diffusion layer, the third diffusion layer and the fifth Connected to each other through a first silicide layer formed on the surface of the diffusion layer of
The first diffusion layer, the third diffusion layer, and the fifth diffusion layer connected to each other function as a first storage node for holding data stored in a memory cell;
In order to prevent leakage between the fifth diffusion layer and the first well, a first conductivity type opposite to the first well is provided between the fifth diffusion layer and the first well. The bottom of the leak prevention diffusion layer is formed to be shallower than the element isolation ,
The first leakage preventing diffusion layer is directly connected to the first diffusion layer and the third diffusion layer;
Wherein with the first diffusion layer, N-type conductivity type formed in the bottom of the second NMOS driver transistor having N-type conductivity type formed in the bottom of the second NMOS access transistor It said fifth diffusion layer having a third diffusion layer and P-type conductivity type formed in the bottom of the second PMOS load transistor, said first diffusion layer, the third diffusion layer and the fifth Interconnected via a second silicide layer formed on the surface of the diffusion layer of
The first diffusion layer, the third diffusion layer, and the fifth diffusion layer connected to each other function as a second storage node for holding data stored in a memory cell;
In order to prevent leakage between the fifth diffusion layer and the first well, a conductivity type opposite to the first well is provided between the fifth diffusion layer and the first well. The bottom of the second leak prevention diffusion layer is formed to be shallower than the element isolation ,
The semiconductor memory device, wherein the second leak preventing diffusion layer is directly connected to the first diffusion layer and the third diffusion layer. A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
Each of the six MOS transistors is
First and second NMOS access transistors for accessing the memory, first and second NMOS driver transistors for driving the storage node to hold the memory cell data, and holding the memory cell data Functioning as first and second PMOS load transistors for supplying charge to
In the first and second NMOS access transistors for accessing the memory ,
A first diffusion layer having an N-type conductivity , a first columnar semiconductor layer, and a second diffusion layer having an N-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on the substrate. The first columnar semiconductor layer is disposed, and the first diffusion layer formed on the bottom of the first columnar semiconductor layer and the second diffusion layer formed on the top of the first columnar semiconductor layer And a gate is formed on a side wall of the first columnar semiconductor layer,
In the first and second NMOS driver transistors that drive the storage node to hold the memory cell data ,
A third diffusion layer having an N-type conductivity type, a second columnar semiconductor layer, and a fourth diffusion layer having an N-type conductivity type are hierarchically arranged in a vertical direction on an insulating film formed on the substrate. The second columnar semiconductor layer is disposed, and the third diffusion layer is formed at the bottom of the second columnar semiconductor layer, and the fourth diffusion layer is formed on the second columnar semiconductor layer. And a gate is formed on a side wall of the second columnar semiconductor layer,
In the first and second PMOS load transistors that supply charge to hold the memory cell data ,
A fifth diffusion layer having a P-type conductivity type, a third columnar semiconductor layer, and a sixth diffusion layer having a P-type conductivity type are arranged hierarchically in a vertical direction on an insulating film formed on the substrate. The third columnar semiconductor layer is formed of the fifth diffusion layer formed on the bottom of the third columnar semiconductor layer and the sixth diffusion layer formed on the third columnar semiconductor layer. And a gate is formed on a side wall of the third columnar semiconductor layer,
It said first NMOS access transistor, load transistor of said first NMOS driver transistor and the first PMOS are arranged adjacent to each other,
It said second NMOS access transistor, the second NMOS driver transistor and the load transistor of the second PMOS are arranged adjacent to each other,
A first well common to a plurality of memory cells for applying a potential to the substrate is formed;
Wherein with the first diffusion layer, N-type conductivity type formed on the bottom of the driver transistor of said first NMOS with N-type conductivity type formed on the bottom of the access transistor of the first NMOS It said fifth diffusion layer having a third diffusion layer and P-type conductivity type formed on the bottom of the first PMOS load transistor, said first diffusion layer, the third diffusion layer and the fifth Connected to each other through a first silicide layer formed on the surface of the diffusion layer of
The first diffusion layer, the third diffusion layer, and the fifth diffusion layer connected to each other function as a first storage node for holding data stored in a memory cell;
In order to prevent leakage between the first diffusion layer and the third diffusion layer and the first well, and between the first diffusion layer and the first well, and the third diffusion layer, Between the first wells, a bottom portion of the first leak prevention diffusion layer having a conductivity type opposite to that of the first well is formed so as to be shallower than the element isolation ,
The first leakage preventing diffusion layer is directly connected to the fifth diffusion layer;
Wherein with the first diffusion layer, N-type conductivity type formed in the bottom of the second NMOS driver transistor having N-type conductivity type formed in the bottom of the second NMOS access transistor It said fifth diffusion layer having a third diffusion layer and P-type conductivity type formed in the bottom of the second PMOS load transistor, said first diffusion layer, the third diffusion layer and the fifth Interconnected via a second silicide layer formed on the surface of the diffusion layer of
The first diffusion layer, the third diffusion layer, and the fifth diffusion layer connected to each other function as a second storage node for holding data stored in a memory cell;
In order to prevent leakage between the first diffusion layer and the third diffusion layer and the first well, and between the first diffusion layer and the first well, and the third diffusion layer. Between the first well and the first well, the bottom of the second leak-proof diffusion layer having a conductivity type opposite to that of the first well is formed shallower than the element isolation ,
The semiconductor memory device, wherein the second leak preventing diffusion layer is directly connected to the fifth diffusion layer.   The first gate wiring extending from the gates of the first NMOS driver transistor and the first PMOS load transistor formed on the diffusion layer functioning as the first storage node has a common first gate wiring. The second gate wiring extending from the gates of the second NMOS driver transistor and the second PMOS load transistor formed on the diffusion layer connected by the contact and functioning as the second storage node is common. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected by the first contact.   The peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors is longer than the peripheral length of the side wall of the columnar semiconductor layer forming the first and second PMOS load transistors. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. By forming the columnar semiconductor layer forming the first and second NMOS driver transistors in an elliptical columnar shape, the peripheral length of the sidewall of the columnar semiconductor layer forming the first and second NMOS driver transistors is reduced. 3. The semiconductor memory device according to claim 1, wherein the length is longer than a peripheral length of a side wall of the columnar semiconductor layer forming the first and second PMOS load transistors.   The peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors is longer than the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS access transistors. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. By forming the columnar semiconductor layer forming the first and second NMOS driver transistors in an elliptical columnar shape, the peripheral length of the sidewall of the columnar semiconductor layer forming the first and second NMOS driver transistors is reduced. 3. The semiconductor memory device according to claim 1, wherein the length is longer than the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS access transistors.   The peripheral length of the side wall of the columnar semiconductor layer forming the first and second PMOS load transistors is shorter than the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS access transistors. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device.   At least one of the third and fourth contacts formed on the third and fourth gate lines respectively extending from the gate electrodes of the first and second NMOS access transistors is connected to the adjacent memory cell. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is shared with a contact formed on a gate wiring extending from a gate electrode of an NMOS access transistor.   The semiconductor memory device according to claim 1, wherein the plurality of columnar semiconductor layers are arranged in a hexagonal lattice pattern. Each fifth gate wiring extending from the gates of the first NMOS driver transistor and the first PMOS load transistor formed on the diffusion layer functioning as the first storage node, Connected by a first common contact with a diffusion layer functioning as a storage node,
Each sixth gate wiring extending from the gate of the second NMOS driver transistor and the second PMOS load transistor formed on the diffusion layer functioning as the second storage node, 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a diffusion layer functioning as one storage node by a second common contact. The six MOS transistors are arranged in a matrix in the row direction and the column direction orthogonal to each other on the substrate,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor is arranged in the first row and the first column,
The first PMOS load transistor is arranged in the second row and the first column,
The first NMOS driver transistor is arranged in the third row and the first column,
The second NMOS access transistor is arranged in the third row and the second column,
The second PMOS load transistor is arranged in the second row and the second column,
3. The semiconductor memory device according to claim 1, wherein the second NMOS driver transistors are arranged in the first row and the second column. The six MOS transistors are arranged in a matrix in the row direction and the column direction orthogonal to each other on the substrate,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor is arranged in the first row and the first column,
The first PMOS load transistor is arranged in the third row and the first column,
The first NMOS driver transistor is arranged in the second row and the first column,
The second NMOS access transistor is arranged in the third row and the second column,
The second PMOS load transistor is arranged in the first row and the second column,
3. The semiconductor memory device according to claim 1, wherein the second NMOS driver transistor is arranged in the second row and the second column. The six MOS transistors are arranged in a matrix in the row direction and the column direction orthogonal to each other on the substrate,
The six MOS transistors are arranged in 3 rows and 2 columns on the substrate,
The first NMOS access transistor is arranged in the first row and the first column,
The first PMOS load transistor is arranged in the third row and the first column,
The first NMOS driver transistor is arranged in the second row and the first column,
The second NMOS access transistor is arranged in the first row and the second column,
The second PMOS load transistor is arranged in the third row and the second column,
3. The semiconductor memory device according to claim 1, wherein the second NMOS driver transistor is arranged in the second row and the second column.   11. The semiconductor memory device according to claim 10, wherein a fifth contact formed on a seventh gate wiring extending from the gates of the first and second NMOS access transistors is shared. The six MOS transistors are arranged in a matrix in the row direction and the column direction orthogonal to each other on the substrate,
The six MOS transistors are arranged in two rows and three columns on the substrate,
The first NMOS access transistor is arranged in the first row and the first column,
The first PMOS load transistor is arranged in the second row and the second column,
The first NMOS driver transistor is arranged in the second row and the first column,
The second NMOS access transistor is arranged in the second row and the third column,
The second PMOS load transistor is arranged in the first row and the second column,
3. The semiconductor memory device according to claim 1, wherein the second NMOS driver transistor is arranged in the first row and the third column.

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