JP4745410B2 - Wireless communication demodulator - Google Patents

Description

  The present invention belongs to an adaptive reception technique for extracting a transmission signal with high quality from signals received by a plurality of antennas in wireless communication, and adaptively combines symbol clock and frequency error information detected based on a signal before adaptive synthesis. This is a technique related to synchronization that improves the quality of a demodulated signal by appropriately switching and using information on a symbol clock and frequency error detected based on a later signal.

  FIG. 3 shows a conventional adaptive receiving device described in Patent Document 1. In FIG. This receiving apparatus includes an antenna, an adaptive filter circuit, and a demodulation circuit. The applied filter circuit includes a high-speed clock 31, a weighting coefficient calculation circuit 333, a coefficient holding circuit 332, and a weighting synthesis circuit 331. The demodulation circuit includes a waveform shaping filter 37, an automatic frequency error compensation circuit (AFC) 35, a carrier recovery circuit 36, and a clock recovery circuit 34. The signal flow will be described below.

  The user signal is received by the antenna 30a and the antenna 30b. The signal received by each antenna is synchronized with the sampling rate output from the high-speed clock 31 and is input to the weighting factor calculation circuit 333, and the weighting factor of the adaptive filter is calculated.

  Next, the weight coefficient output from the weight coefficient arithmetic circuit 333 is latched by the coefficient holding circuit 332 with this symbol clock so as to be synchronized with the symbol clock detected by the demodulator circuit at the subsequent stage.

  The adaptive filter processing is performed by weighting and combining the coefficient output from the coefficient holding circuit 332 in synchronization with the symbol clock and the received signal by the weighting combining circuit 331.

  The signal subjected to the adaptive filter processing is subjected to waveform shaping processing, frequency error compensation, and carrier wave phase compensation in a subsequent demodulation circuit, and the demodulation processing is completed.

Japanese Patent Laid-Open No. 11-251996

  Since the demodulation circuit of FIG. 3 extracts the symbol clock from the demodulated signal after adaptive weighting, the reproduction timing accuracy of the demodulated signal is degraded when the adaptive weighting is not converged, such as at the start of reception. If weighted synthesis of the adaptive filter in the previous stage is executed in synchronization with the timing when the accuracy is deteriorated, the adaptive weighting accuracy is deteriorated, so that the quality of the demodulated signal is deteriorated.

  Further, the weighting factor calculation circuit of FIG. 3 does not consider the frequency error, and there is a problem that the weighting factor does not converge to a desired weighting factor when the weighting factor is affected by the frequency error.

  The weighting factor estimation circuit in FIG. 3 derives the weighting factor at the sample timing and is latched by the symbol clock in the coefficient holding circuit, but the training signal is transmitted in symbol units, and when the sampling timing and the symbol clock are asynchronous, There is a problem that the training signal synchronization circuit becomes complicated.

In order to solve the above problems, a radio communication demodulator according to the present invention receives a transmission signal having a training signal by a plurality of antennas, and detects a arrival timing of the training signal,
An adaptive filter circuit that weights and synthesizes signals received by each antenna according to the propagation path;
A demodulation circuit for demodulating a transmission signal from the output of the adaptive filter circuit ;
A coarse clock recovery circuit and a selection circuit for recovering the first symbol clock by the training signal ;
The adaptive filter circuit includes a weighting factor calculation circuit that calculates a weighting factor based on a signal received by each antenna;
A weighting synthesis circuit for weighting and synthesizing signals received by a plurality of antennas using the weighting coefficient output from the weighting coefficient arithmetic circuit;
The demodulation circuit includes a clock recovery circuit that recovers a second symbol clock using an output signal from the adaptive filter circuit;
In synchronization with the symbol clock output from the selection circuit , the synchronization circuit, the adaptive filter circuit, and the demodulation circuit are operated.
The adaptive filter circuit calculates a weighting factor using the training signal in synchronization with the arrival timing and symbol clock of the training signal detected by the synchronization circuit ;
The coarse clock recovery circuit includes a matched filter circuit that detects a correlation with a training signal;
A sampling circuit that samples the matched pulse output from the matched filter circuit with a free-running symbol clock that is asynchronous with the received signal;
Based on the shape of the matched pulse sampled by the sampling circuit, it has a phase detection circuit that detects the clock phase difference between the free-running symbol clock and the received signal,
Based on the detection result of the phase detection circuit, the phase of the free-running symbol clock is corrected and the first symbol clock is output,
The selection circuit outputs a symbol clock to be output based on the arrival timing of the training signal.
From the first symbol clock recovered by the coarse clock recovery circuit
Switching to the second symbol clock recovered by the clock recovery circuit .

Further, the demodulation circuit includes a frequency error detection circuit,
The synchronization circuit includes a frequency error compensation circuit and a matched filter circuit for each antenna,
Supplying the frequency error detected by the frequency error detection circuit to the frequency error compensation circuit;
Compensate for frequency error from the received signal,
It is also preferable to input the output signal of the frequency error compensation circuit to the matched filter circuit and detect the arrival timing of the training signal from the output of the matched filter circuit for each antenna.

The synchronization circuit includes a frequency error compensation circuit, a matched filter circuit, and a frequency error detection circuit for each antenna,
Supplying the frequency error detected by the frequency error detection circuit to the frequency error compensation circuit for each antenna;
Compensate for frequency error from the received signal,
It is also preferable to input the output signal of the frequency error compensation circuit to the matched filter circuit and detect the arrival timing of the training signal from the output of the matched filter circuit for each antenna.

  It is also preferable that the weighting factor calculation circuit calculates a weighting factor based on the output signal of the frequency error compensation circuit.

  As described above, when the technique of the present invention is used, it is possible to weight and synthesize received signals from a plurality of antennas with high accuracy of timing and frequency error compensation, thereby improving the quality of demodulated signals and establishing high-speed synchronization. .

1 illustrates an example of a wireless communication demodulation device according to a first embodiment of the present invention. 6 shows an example of a wireless communication demodulation device according to a second embodiment of the present invention. 1 shows a conventional adaptive receiver. An example of symbol clock regeneration processing from a matched pulse signal is shown.

  The block diagram showing the 1st Embodiment of this invention is shown in FIG. FIG. 1 includes an antenna, a synchronization circuit, an adaptive filter circuit, and a demodulation circuit.

  The antenna is composed of two antennas 10a and 10b, and performs adaptive reception on the reception signals of these two antennas. In this example, two antennas will be described, but the present invention is not limited to two.

  The synchronization circuit includes frequency error compensation circuits (hereinafter referred to as AFC) 111 and 112, matched filters 121 and 122, a coarse clock recovery circuit 19, an arrival timing detection circuit 110, and a selection circuit 111.

  The adaptive filter circuit includes a weighting synthesis circuit 131 and a weighting coefficient calculation circuit 132.

  The demodulation circuit includes a waveform shaping filter 17, a frequency error compensation circuit (hereinafter AFC) 15, a frequency error detection circuit 18, a carrier recovery circuit 16, and a clock recovery circuit 14.

Next, the signal flow will be described.
On the transmission side, a signal is transmitted by inserting a training signal having a sharp peak in the autocorrelation waveform and a small cross-correlation. On the other hand, on the receiving side, signals received by the receiving antennas 10a and 10b are input to the synchronization circuit, and frequency errors are compensated for each antenna by the AFC 111 and the AFC 112. Here, the frequency error used for compensation is the one detected by the frequency error detection circuit 18 of the demodulator circuit in the subsequent stage.

  The signals whose reception frequency error is compensated for each antenna by the AFC 111 and AFC 112 are input to the matched filters 121 and 122, and the arrival timing of the training signal is detected by the arrival timing detection circuit 110 from the matched pulse signals of the matched filters. The In parallel, the coarse clock recovery circuit 19 recovers the symbol clock from the matched pulse signal.

FIG. 4 shows an example of clock recovery processing from a matched pulse signal.
In FIG. 4, the selection circuit selects the symbol clock from the coarse clock recovery circuit at the beginning of reception, and the phase correction circuit of the coarse clock recovery circuit is a free-running symbol clock set to the same frequency as the symbol rate supplied from the outside. Is output without phase correction.

  For this reason, the free-running symbol clock and the signal Nyquist timing do not match, and the output of the matched pulse, which is the sum of squares of the matched filter output, is distributed to a, b, and c as shown in FIG.

  Using the dispersed a, b, and c, the phase difference detection circuit detects the phase difference between the free-running symbol clock and the signal Nyquist timing, and the phase correction circuit corrects it. The phase correction method is shown in FIG.

If the timing at which the peak value obtained by interpolating the levels a, b, and c is defined as Nyquist timing, the phase difference Δ between the free-running symbol clock and the Nyquist timing is expressed by the following equation.

  Therefore, the phase detection circuit inputs a, b and c and outputs a phase difference Δ. On the other hand, the phase correction circuit corrects Δ to make the free-running symbol clock coincide with the Nyquist timing of the signal. As a result, as shown in FIG. 4b, a matched pulse having a large peak value can be obtained only at the timing that coincides with the Nyquist timing.

  Next, the operation of the adaptive filter circuit will be described. The adaptive filter circuit 13 calculates a weighting factor so that the signals received by the antennas 10a and 10b are weighted and combined with the maximum C / N (signal to noise power ratio). In deriving the weighting factor, the signal whose frequency error is compensated by the AFC 111 and the AFC 112 is used to derive the weighting factor using a signal that is not affected by the frequency error.

  An adaptive filter process is performed by weighting and synthesizing the received signal using the weighting coefficient derived here.

  In the demodulation circuit, the output from the adaptive filter is subjected to route roll-off processing by the waveform shaping filter 17, error detection by the frequency error detection circuit 18, compensation of the error detected by the AFC 15, and carrier phase recovery by the carrier recovery circuit 16. The clock recovery circuit 14 performs symbol clock recovery.

  The switching of the symbol clock in the selection circuit of the synchronous circuit will be described.

  In the present invention, the symbol clock is detected from the matched pulse by the coarse clock recovery circuit, while the symbol clock is recovered from the signal after interference compensation by the demodulation circuit.

  Since the accuracy of the symbol clocks reproduced by both varies depending on the length and period of the training signal and other parameters, the demodulation characteristics are improved by selecting a symbol clock with higher accuracy. Therefore, the selection circuit 111 receives the first symbol clock from the coarse clock recovery circuit 19 and the second symbol clock from the clock recovery circuit 14, and the first symbol clock and the second symbol clock according to some criteria. Switch between and use.

  As an example of switching, until the synchronization of the training signal is established, the timing at which the training signal is detected using the first symbol clock (the timing at which the power of the matched pulse shown in FIG. 4b exceeds the set threshold) is used. A method for switching to the second symbol clock is used as a trigger.

  However, the switching timing of the symbol clock is an example of various switching methods, and the switching timing is not limited to the timing at which the training signal is synchronized.

  Since the timing recovery is possible before the weighted synthesis, the first symbol clock is desirably used for synchronization at the initial stage where demodulation circuit synchronization is not established at the beginning of reception. On the other hand, since the second symbol clock is obtained from the signal after weighted synthesis, the timing accuracy is high after the initial synchronization of the demodulation circuit is established, and it is desirable to use it in the steady state after the establishment of the initial synchronization.

  As described above, by appropriately switching between the first symbol clock and the second symbol clock, the symbol can be obtained with higher accuracy from the beginning of reception compared to the conventional adaptive receiving apparatus of FIG. 3 that uses only the second symbol clock. Clock synchronization can be established.

  Furthermore, by compensating in advance the frequency error estimated by the demodulation circuit from the received signal input to the matched filter and weighting factor calculation circuit, the timing detection accuracy and weighting factor accuracy in the matched filter is improved, and the signal quality is improved. Improved.

  The block diagram showing the 2nd Embodiment of this invention is shown in FIG. FIG. 2 includes an antenna, a synchronization circuit, an adaptive filter circuit, and a demodulation circuit.

  The antenna is composed of two antennas 20a and 20b, and performs adaptive reception on the reception signals of these two antennas. In this example, two antennas will be described, but the antenna of the present invention is not limited to two.

  The synchronization circuit includes frequency error compensation circuits (hereinafter referred to as AFC) 211 and 212, matched filters 221 and 222, frequency error detection circuits 281 and 282, coarse clock recovery circuit 29, arrival timing detection circuit 210, and selection circuit 211. .

  The adaptive filter circuit includes a weighting synthesis circuit 231 and a weighting coefficient calculation circuit 232.

  The demodulation circuit includes a waveform shaping filter 27, a carrier recovery circuit 26, and a clock recovery circuit 24.

Next, the signal flow will be described.
A signal is transmitted by inserting a training signal having a sharp peak in the autocorrelation waveform and a small cross-correlation from the transmission side.

  On the other hand, on the receiving side, signals received by the receiving antennas 20a and 20b are input to the synchronization circuit. The frequency error is compensated by the AFC 211 and the AFC 212. The frequency error used in the compensation is detected by the frequency error detection circuits 281 and 282 using the phase rotation of the outputs from the matched filters 221 and 222 in the subsequent stage, respectively. Shall.

  Since the operations of the adaptive filter circuit and the demodulation circuit are the same as those in the first embodiment, a description thereof will be omitted.

  Unlike FIG. 1, FIG. 2 includes a frequency error detection circuit for each antenna and performs error detection correction, and thus has a feature that can cope with the case where the RF conversion frequencies of the receiving antennas 20 a and 20 b are asynchronous.

  Moreover, all the embodiments described above are illustrative of the present invention and are not intended to limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

10a, 10b, 20a, 20b Antenna 111, 112, 15, 211, 212 Frequency error compensation circuit (AFC)
121, 122, 221, 222 Matched filter 19, 29 Coarse clock recovery circuit 110, 210 Arrival timing detection circuit 111, 211 Selection circuit 131, 231 Weighting synthesis circuit 132, 232 Weight coefficient calculation circuit 14, 24 Clock recovery circuit 16, 26 Carrier recovery circuit 17, 27 Waveform shaping filter 18, 281, 282 Frequency error detection circuit 30a, 30b Antenna 31 High-speed clock 331 Weighting synthesis circuit 332 Coefficient holding circuit 333 Weight coefficient calculation circuit 34 Clock recovery circuit 35 Automatic frequency error compensation circuit ( AFC)
36 Carrier regeneration circuit 37 Waveform shaping filter

Claims (4)

A synchronization circuit that receives a transmission signal having a training signal with a plurality of antennas and detects the arrival timing of the training signal;
An adaptive filter circuit that weights and synthesizes signals received by each antenna according to the propagation path;
A demodulation circuit for demodulating a transmission signal from the output of the adaptive filter circuit ;
A coarse clock recovery circuit and a selection circuit for recovering the first symbol clock by the training signal ;
The adaptive filter circuit includes a weighting factor calculation circuit that calculates a weighting factor based on a signal received by each antenna;
A weighting synthesis circuit for weighting and synthesizing signals received by a plurality of antennas using the weighting coefficient output from the weighting coefficient arithmetic circuit;
The demodulation circuit includes a clock recovery circuit that recovers a second symbol clock using an output signal from the adaptive filter circuit;
In synchronization with the symbol clock output from the selection circuit , the synchronization circuit, the adaptive filter circuit, and the demodulation circuit are operated.
The adaptive filter circuit calculates a weighting factor using the training signal in synchronization with the arrival timing and symbol clock of the training signal detected by the synchronization circuit ;
The coarse clock recovery circuit includes a matched filter circuit that detects a correlation with a training signal;
A sampling circuit that samples the matched pulse output from the matched filter circuit with a free-running symbol clock that is asynchronous with the received signal;
Based on the shape of the matched pulse sampled by the sampling circuit, it has a phase detection circuit that detects the clock phase difference between the free-running symbol clock and the received signal,
Based on the detection result of the phase detection circuit, the phase of the free-running symbol clock is corrected and the first symbol clock is output,
The selection circuit outputs a symbol clock to be output based on the arrival timing of the training signal.
From the first symbol clock recovered by the coarse clock recovery circuit
A radio communication demodulating apparatus, wherein the radio communication demodulating apparatus switches to a second symbol clock regenerated by the clock regenerating circuit . The demodulation circuit includes a frequency error detection circuit;
The synchronization circuit includes a frequency error compensation circuit and a matched filter circuit for each antenna,
Supplying the frequency error detected by the frequency error detection circuit to the frequency error compensation circuit;
Compensate for frequency error from the received signal,
2. The radio communication demodulation according to claim 1, wherein the output signal of the frequency error compensation circuit is input to the matched filter circuit, and the arrival timing of the training signal is detected from the output of the matched filter circuit for each antenna. apparatus. The synchronization circuit includes a frequency error compensation circuit, a matched filter circuit, and a frequency error detection circuit for each antenna,
Supplying the frequency error detected by the frequency error detection circuit to the frequency error compensation circuit for each antenna;
Compensate for frequency error from the received signal,
2. The radio communication demodulation according to claim 1, wherein the output signal of the frequency error compensation circuit is input to the matched filter circuit, and the arrival timing of the training signal is detected from the output of the matched filter circuit for each antenna. apparatus.   4. The radio communication demodulator according to claim 2, wherein the weighting factor calculation circuit calculates a weighting factor based on an output signal of the frequency error compensation circuit.

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