JP4718773B2 - converter - Google Patents

Description

  The present invention relates to a converter.

  The switching converter periodically switches DC power applied to the primary winding of the transformer, rectifies AC power appearing in the secondary winding of the transformer, and then outputs the smoothed output. A diode rectifier is generally used for a circuit that rectifies AC power.

  However, since the forward voltage drop of the diode rectifier element is relatively large, power loss in the diode rectifier element cannot be ignored particularly in a switching converter with a low output voltage. Therefore, a Schottky barrier diode (SBD) with a small forward voltage drop is often used as the diode rectifier.

  Also, field effect transistors (FETs) with very low on-resistance have been developed by recent high integration technologies. Therefore, a synchronous rectifier circuit has been proposed that realizes a low-loss rectifier function by using a field-effect transistor having a low on-resistance as a rectifier and switching the field-effect transistor in synchronization with the excitation timing of the transformer. (See Patent Document 1).

  FIG. 5 is a configuration example of a forward type switching converter provided with a synchronous rectifier circuit. This switching converter includes a DC power supply 10, a field effect transistor 11, a transformer 12, field effect transistors 13 and 14, a reactor 15, and a capacitor 16.

  The field effect transistor 11 is periodically turned on and off by a signal supplied from the outside. As a result, an exciting current intermittently flows in the primary winding Np of the transformer 12, and AC power appears in the secondary winding Ns of the transformer 12.

  The field effect transistors 13 and 14 are used as rectifying elements. In this example, a self-driven method is used to control the field effect transistors 13 and 14. That is, the on / off states of the field effect transistors 13 and 14 are controlled using the voltage appearing in the secondary winding Ns of the transformer 12. The AC power appearing in the secondary winding Ns of the transformer 12 is rectified by a rectifier circuit including field effect transistors 13 and 14, smoothed by a smoothing circuit including a reactor 15 and a capacitor 16, and then DC The voltage Vo is output from the output terminals 17 and 18.

  Next, the operation of the switching converter shown in FIG. 5 will be described below. When the field effect transistor 11 connected to the primary winding Np of the transformer 12 is turned on and an exciting current flows through the primary winding Np, the field effect transistor is generated by the positive voltage appearing in the secondary winding Ns. Since 13 is turned on, the power appearing in the secondary winding Ns is supplied to the output side via the field effect transistor 13. At this time, the field effect transistor 14 is turned off.

  On the other hand, when the field effect transistor 11 connected to the primary winding Np of the transformer 12 is turned off, the exciting current of the primary winding Np is cut off, and the polarity of the voltage appearing in the secondary winding Ns is reversed. Accordingly, the field effect transistor 13 is switched from the on state to the off state, and the field effect transistor 14 is switched from the off state to the on state.

At this time, the commutation current flows through the field effect transistor 14 due to the storage of the current flowing through the reactor 15, and power is supplied to the load. Thus, the timing at which the field effect transistors 13 and 14 constituting the synchronous rectifier circuit are turned on and off depends on the voltage appearing in the secondary winding Ns.
JP 2003-116273 A (claims, abstract)

  Incidentally, in the converter using the synchronous rectifier circuit as shown in FIG. 5, the output voltage Vo cannot be controlled. Therefore, when the load fluctuates, the output voltage Vo fluctuates.

  Therefore, it is conceivable to connect a saturable reactor (mag amplifier) to the output side of the converter and adjust the reset current of this saturable reactor to realize PWM (Pulse Width Modulation) control and control the output voltage. . However, since the reset current is supplied to the saturable reactor when the field effect transistor 13 shown in FIG. 5 is turned off (when the circuit is opened), the mag amplifier and the synchronous rectifier circuit are connected. When simply combined, there is a problem that it is difficult to flow a reset current in such a state.

  The present invention has been made based on the above circumstances, and an object thereof is to provide an efficient converter while performing output voltage control combining a mag-amp and a synchronous rectifier circuit.

To achieve the above object, the present invention includes a transformer, a first winding connected in series to a secondary winding of the transformer, and a second winding different from the first winding. A saturable reactor for a mag amplifier, a synchronous rectifier circuit connected to the first winding of the saturable reactor, a control circuit for causing a reset current to reduce the residual magnetic flux of the saturable reactor to flow through the second winding, And a synchronous rectifier circuit is connected to the saturable reactor, and a first transistor for passing an AC power current appearing in the secondary winding when an exciting current flows in the primary winding of the transformer, and the transformer A second transistor for passing a commutation current when the exciting current of the primary winding of the transformer is cut off, and further, the second transistor immediately before the exciting current of the primary winding of the transformer is cut off.蓄to the input capacitance of the transistor of Has a discharge circuit for discharging the charges, one end of the first winding of the saturable reactor is connected to the gate of the second transistor via a diode, a first winding of the saturable reactor Is connected to the drain of the first transistor, one end of the second winding of the saturable reactor is connected to the control circuit, and the other end of the second winding of the variable reactor is the first It is connected to the source of the transistor.

Therefore, it is possible to provide an efficient converter while performing output voltage control combining a mag amplifier and a synchronous rectifier circuit. In addition, loss of power can be suppressed by synchronous rectification. Further, by including the discharge circuit, the second switching element can be turned off at an appropriate timing.

  According to the present invention, it is possible to realize an efficient converter while performing output voltage control using a mag amplifier and a synchronous rectifier circuit.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration example of the first embodiment of the present invention. As shown in this figure, the first embodiment of the present invention includes a DC power supply 50, a field effect transistor 51, a transformer 52, a control circuit 53, a diode 54, a saturable reactor 55, field effect transistors 56 and 57. , Current control circuit 58, diode 59, discharge circuit 60, reactor 61, capacitor 62, and output terminals 63 and 64.

  Here, the DC power supply 50 is, for example, a switching power supply or the like, and is a power supply circuit that converts commercial power into DC power and outputs it, or a battery. The field effect transistor 51 is connected to the primary winding Np of the transformer 52, and is periodically turned on or off in accordance with the control of the control circuit 53, so that the exciting current is supplied to the primary winding Np of the transformer 52. Shed.

  The transformer 52 includes a primary winding Np and a secondary winding Ns, and an AC voltage corresponding to an excitation current flowing into the primary winding Np according to a change in the on or off state of the field effect transistor 51 is applied to the secondary winding. Output from Ns.

  The control circuit 53 controls the field effect transistor 51 to be periodically turned on or off, and controls the discharge circuit 60 immediately before the field effect transistor 51 is turned on so that the field effect transistor is turned on. The charge accumulated in the input capacitance present at the gate of the transistor 57 is discharged.

  When the output voltage Vs of the secondary winding Ns is negative (when the upper terminal of the secondary winding Ns shown in FIG. 1 has a negative polarity), the diode 54 A positive voltage is applied to the gate to turn it on, and the field effect transistor 57 is kept on until the charge is discharged by the discharge circuit 60.

  The saturable reactor 55 is a so-called mag amplifier, and is reset by a current conducted from the current control circuit 58 to the second winding Nb during a period in which the field effect transistor 51 is in an off state. The first winding Na of the saturable reactor 55 has a large inductance until a magnetic flux change equal to the amount of residual magnetic flux that decreases due to this resetting is generated, so even if the field effect transistor 51 is turned on, the output side There is no current flowing through.

  The saturable reactor 55 is configured by winding a first winding Na and a second winding Nb around a toroidal core. The number of turns na of the first winding Na and the number of turns nb of the second winding Nb have a relationship of nb> na. Further, for the first winding Na, for example, a current of about several A to several tens of A is conducted, and for the second winding Nb, for example, a current of about several mA to several tens of mA is conducted, Magnetic saturation of the toroidal core.

  The field effect transistor 56 which is the first switching element is used when the field effect transistor 51 is in an on state, that is, when the output voltage Vs of the secondary winding Ns is positive (the secondary winding shown in FIG. 1). When the terminal on the upper side of Ns has a positive polarity), the terminal is turned on and outputs a voltage to the output terminals 63 and 64. When the output voltage Vs is negative, it is turned off.

  When the output voltage Vs of the secondary winding Ns is negative, the field effect transistor 57 that is the second switching element is turned on by the voltage input through the diode 54, and is connected to the reactor 61. A commutation current generated by the energy of the flowing current is output from the output terminals 63 and 64. When the output voltage Vs is positive, it is turned off.

  These field effect transistors 56 and 57 constitute a synchronous rectifier circuit.

  The current control circuit 58, which is a control circuit, supplies a reset current to the second winding Nb of the saturable reactor 55 according to the output voltage Vo appearing at the output terminals 63 and 64, and the output voltage Vo is a desired value. Control to become.

  FIG. 2 is a diagram illustrating a detailed configuration example of the current control circuit 58. As shown in this figure, the current control circuit 58 includes a diode 58a, a PNP transistor 58b, an NPN transistor 58c, a comparator 58d, a reference power supply 58e, and resistors 58f and 58g.

  Here, the diode 58 a is a diode for preventing a backflow, and allows a current flowing out from the collector terminal of the PNP transistor 58 b to flow into the second winding Nb of the saturable reactor 55.

  When the NPN transistor 58c connected to the base of the PNP transistor 58b is turned on, the PNP transistor 58b is turned on and the second winding Nb of the saturable reactor 55 through the diode 58a. Into the current.

  The NPN transistor 58c is turned on when the output voltage of the comparator 58d is positive, and controls the PNP transistor 58b to be turned on.

  The comparator 58d compares the voltage applied to the reference power source 58e and the resistor 58g (the voltage obtained by dividing the output voltage Vo by the resistors 58f and 58g), and when the voltage applied to the resistor 58g is higher. The output voltage is a positive predetermined value, otherwise the output voltage is a negative predetermined value or zero.

  The reference power source 58e is configured by, for example, a Zener diode. The resistors 58f and 58g are voltage dividing resistors, and divide and output the output voltage Vo. The element values of the voltage dividing resistors 58f and 58g are set so that the voltage appearing at the resistor 58g is equal to the voltage of the reference power source 58e when the output voltage Vo is a desired value.

  Returning to FIG. 1, the diode 59 is connected between the source and drain of the field effect transistor 57.

  The discharge circuit 60 discharges the electric charge accumulated in the input capacitance (floating capacitance) existing between the gate and the drain of the field effect transistor 57 immediately before the field effect transistor 51 is turned on, so that the field effect is obtained. The type transistor 57 is controlled to be turned off at an appropriate timing. The discharge circuit 60 includes a semiconductor switch (for example, a field effect transistor), and is controlled so that the control circuit 53 is turned on immediately before the field effect transistor 51 is turned on. .

  The reactor 61 forms a smoothing circuit together with the capacitor 62, smoothes and outputs the pulsating current, and generates a commutation current when the field effect transistor 51 is turned off. The capacitor 62 forms a smoothing circuit together with the reactor 61. The output terminals 63 and 64 are terminals for taking out a DC voltage.

  Next, the operation of the first embodiment of the present invention will be described with reference to FIG.

  FIG. 3 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention. Here, Vs in FIG. 3 indicates an output voltage of the secondary winding Ns of the transformer 52, Vg1 in FIG. 3 indicates a voltage between the gate and the source of the field effect transistor 56, and Vg2 in FIG. The voltage between the gate and the source of the field effect transistor 57 is shown.

  At time t1, according to the control of the control circuit 53, when the field effect transistor 51 is turned on, a current flows from the DC power supply 50 to the primary winding Np of the transformer 52, and the secondary winding Ns Electric power is generated, and an output voltage Vs is generated as shown in FIG. As a result, as shown in FIG. 3, since the voltage Vg1 between the gate and the source of the field effect transistor 56 is in a high state, the field effect transistor 56 is in an on state. As shown in FIG. 3, since the voltage Vg2 between the gate and the source of the field effect transistor 57 is in a low state, the field effect transistor 57 is in an off state.

  When the field effect transistor 56 is turned on, a closed circuit including a reactor 61, a load (not shown), and a saturable reactor 55 is formed. However, as will be described later, saturable reactor 55 maintains a high impedance state until a current corresponding to the amount of magnetic flux generated by the reset current flows, and thus is substantially in an off state until a predetermined time has elapsed. Then, when a certain time elapses, the output is turned on and the output voltage Vo is output to the output terminals 63 and 64.

  Next, when the field effect transistor 51 is turned off at time t2, the exciting current of the primary winding Np is cut off, and the polarity of the voltage Vs appearing in the secondary winding Ns is reversed as shown in FIG. . As a result, the voltage Vg1 between the gate and source of the field effect transistor 56 is in a low state as shown in FIG. 3, so that the field effect transistor 56 is turned off. On the other hand, since the voltage Vg2 between the gate and the source of the field effect transistor 57 is in a high state as shown in FIG. 3, the field effect transistor 57 is turned on.

  When the field effect transistor 56 is turned off, the exciting current flowing through the reactor 61 is interrupted, so that a commutation current is generated in the reactor 61. This commutation current is output from the output terminals 63 and 64 to a load (not shown) via the field effect transistor 57 that is in the ON state.

  Subsequently, at time t3, when the voltage appearing in the secondary winding Ns of the transformer 52 becomes “0”, the voltage at the anode terminal of the diode 54 also becomes “0”. However, since the diode 54 is in a reverse bias state due to the influence of the electric charge accumulated in the input capacitance existing at the gate of the field effect transistor 57, the gate of the field effect transistor 57 and the gate of the field effect transistor 57 are shown in FIG. The voltage Vg2 between the sources is kept high. 3 indicates a change in Vg2 when the diode 54 is not provided. By providing the diode 54 as described above, the time during which the field-effect transistor 57 is in the on state can be increased, so that power loss can be suppressed as will be described later.

  That is, since a parasitic diode (body diode) exists inside the field effect transistor 57, even when the field effect transistor 57 is turned off, a commutation current flows through the parasitic diode of the field effect transistor 57. Continue to flow. It is desirable that the field-effect transistor 57 is in an on state while the commutation current is flowing (while the exciting current of the primary winding Np is interrupted). However, if the field effect transistor 57 is switched to the off state while the commutation current is flowing as described above, the subsequent commutation current flows through the parasitic diode inside the field effect transistor 57. For this reason, the power loss increases due to the influence of the voltage drop in the parasitic diode.

  However, in the case of the present embodiment, the field effect transistor 57 is kept on by the presence of the diode 54, so that it is possible to prevent voltage loss due to the parasitic diode.

  Subsequently, at time t4, the discharge circuit 60 operates under the control of the control circuit 53, and the charge accumulated in the input capacitance existing at the gate of the field effect transistor 57 is discharged. As a result, as shown in FIG. 3, the voltage between the gate and the source of the field effect transistor 57 decreases and goes to a low state, so that the field effect transistor 57 is turned off.

  Incidentally, during the period from time t2 to time t4, the current control circuit 58 applies a reset current to the second winding Nb of the saturable reactor 55 in accordance with the output voltage Vo appearing at the output terminals 63 and 64. And reset it (ie, return the magnetic state of the saturable reactor 55 to the initial state of one cycle).

  That is, when the terminal voltage of the resistor 58g is higher than the voltage of the reference power supply 58e (when the output voltage Vo is higher than a desired voltage), the comparator 58d constituting the current control circuit 58 sets its output to high. Put it in a state. As a result, since the NPN transistor 58c is turned on, the PNP transistor 58b is also turned on, and a reset current flows into the second winding Nb of the saturable reactor 55 via the diode 58a.

  As a result, the magnetic core of the saturable reactor 55 is magnetized in the direction opposite to that in the case where the field effect transistor 56 is in the on state.

  Next, at time t5, the field effect transistor 51 is turned on according to the control of the control circuit 53, so that the output voltage Vs of the secondary winding Ns becomes positive. As a result, as shown in FIG. 3, since the voltage Vg1 between the gate and the source of the field effect transistor 56 becomes high, the field effect transistor 56 is turned on.

  When the field effect transistor 56 is turned on, a closed circuit including a reactor 61, a load (not shown), and a saturable reactor 55 is formed. However, as described above, the saturable reactor 55 is magnetized in the reverse direction, so that it maintains a high impedance state until a current that saturates in the positive direction flows by canceling the amount of magnetic flux reduced at that time, In the meantime, it is turned off. Thereafter, the saturable reactor 55 is turned on, and the output voltage Vo is applied to the output terminals 63 and 64.

  Therefore, the current control circuit 58 and the saturable reactor 55 perform PWM control for controlling the output voltage Vo to a desired value by controlling the width of the output pulse in accordance with the output voltage Vo. As a result, the output voltage Vo always holds a constant value regardless of the fluctuation of the load.

  As described above, according to the first embodiment of the present invention, the saturable reactor 55 having the first winding Na and the second winding Nb is used. It becomes possible to control the output voltage of the circuit.

  In addition, since the number of turns of the second winding Nb of the saturable reactor 55 is larger than that of the first winding Na, resetting can be performed with a small current, so that wasted power can be reduced. Thus, the efficiency of the switching converter can be improved.

  In addition, since the diode 54 is inserted between the gate terminal of the field effect transistor 57 and the secondary winding Ns of the transformer 52, the on-time of the field effect transistor 57 is extended so that the parasitic diode The power loss due to the voltage drop can be reduced.

  Next, a second embodiment of the present invention will be described.

  FIG. 4 is a circuit diagram illustrating a configuration example of the second embodiment of the present invention. In this figure, parts common to the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  In the second embodiment shown in FIG. 4, the circuit shown in FIG. 1 is a slave circuit 101, and a master circuit 100 is newly added thereto. That is, the transformer 52 is replaced with a transformer 80 having a primary winding Np, a secondary winding Ns, and a tertiary winding Nt. A master circuit 100 having diodes 81 and 82, a reactor 83, a capacitor 84, and output terminals 85 and 86 is newly added, and the control circuit 53 is replaced with a control circuit 87. Other configurations are the same as those in FIG.

  Here, the diodes 81 and 82 which are a part of the rectifying / smoothing circuit constitute a rectifying circuit, and rectify the alternating current output from the tertiary winding Nt of the transformer 80. A reactor 83 which is a part of the rectifying / smoothing circuit and a capacitor 84 which is a part of the rectifying / smoothing circuit constitute a smoothing circuit, and smoothes and outputs the DC voltage (pulsating current) output from the diodes 81 and 82.

  The control circuit 87 which is a switching control circuit changes the switching duty ratio of the field effect transistor 51 in accordance with the output voltage Vo2 appearing at the output terminals 85 and 86 so that the output voltage Vo2 becomes a desired value. Control.

  Next, the operation of the above second embodiment will be described.

  The control circuit 87 switches the field effect transistor 51 at a predetermined cycle. As a result, an AC voltage is generated in the tertiary winding Nt. This AC voltage is half-wave rectified by the diodes 81 and 82 and smoothed by the reactor 83 and the capacitor 84. As a result, the DC output voltage Vo2 is applied to the output terminals 85 and 86.

  The control circuit 87 detects the value of the output voltage Vo2 appearing at the output terminals 85 and 86. If this value is different from the desired voltage, the control circuit 87 changes the duty ratio of switching of the field effect transistor 51 to thereby change the desired voltage. Adjust so that As a result, the output voltage Vo2 of the master circuit 100 is controlled to be always constant.

  On the other hand, the slave circuit 101 generates an output voltage Vo1 at the output terminals 63 and 64 by the same operation as in the first embodiment, and this output voltage Vo1 is always constant by the current control circuit 58 and the saturable reactor 55. It is controlled to become.

  According to the above embodiment, the master circuit 100 can always obtain a constant voltage by the PWM control by the control circuit 87. Further, since the slave circuit 101 can always obtain a constant voltage by the current control circuit 58 and the saturable reactor 55, two different types of voltages can be obtained.

  In the above embodiment, the case where there is only one slave circuit 101 is shown, but a plurality of slave circuits may be provided. According to such an embodiment, three or more different voltages can be obtained.

  As described above, according to the second embodiment of the present invention, the master circuit 100 and the slave circuit 101 are provided, and the master circuit 100 is configured such that the output voltage Vo2 is constant by PWM control, and the slave circuit 101 can be controlled by the current control circuit 58 and the saturable reactor 55 so that the output voltage Vo1 becomes constant.

  In each of the above embodiments, a field effect transistor is used as the switching element, but another switching element (for example, an IGBT (Insulated Gate Bipolar Transistor)) may be used.

In each of the above embodiments, the diode 54 is connected between the gate terminal of the field effect transistor 57 and the secondary winding Ns. However, the diode 54 can be omitted. There is .

  Further, the circuit configuration of the current control circuit 58 shown in FIG. 2 is an example, and other configurations may be used.

  The converter according to the present invention is used in, for example, a power supply device built in an electronic device such as a personal computer.

1 is a circuit diagram showing a configuration example of a switching converter according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a detailed configuration example of a current control circuit of the switching converter shown in FIG. 1. 2 is a timing chart for explaining the operation of the switching converter shown in FIG. 1. It is a circuit diagram which shows the structural example of the switching inverter which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the conventional switching converter.

Explanation of symbols

54 Diode 55 Saturable Reactor 56 Field Effect Transistor (Part of Synchronous Rectification Circuit, First Switching Element)
57 Field effect transistor (part of synchronous rectification circuit, second switching element)
58 Current control circuit (detection circuit, control circuit)
60 Discharge circuit 81, 82 Diode (part of rectifying and smoothing circuit)
83 reactor (part of rectifying and smoothing circuit)
84 Capacitor (part of rectifying and smoothing circuit)
87 Control circuit (switching control circuit)

Claims (1)

A transformer,
A saturable reactor for a mag-amp having a first winding connected in series to the secondary winding of the transformer, and a second winding different from the first winding;
A synchronous rectifier circuit connected to the first winding of the saturable reactor;
A control circuit for causing a reset current to reduce the residual magnetic flux of the saturable reactor to flow through the second winding;
Have
The synchronous rectifier circuit is
Is connected to the saturable reactor, a first transistor for passing the AC power of the current appearing in the secondary winding when the excitation current flows through the primary winding of the transformer,
A second transistor for passing a commutation current when the excitation current of the primary winding of the transformer is interrupted;
Have
And a discharge circuit for discharging the charge accumulated in the input capacitance of the second transistor immediately before the exciting current of the primary winding of the transformer is cut off,
One end of the first winding of the saturable reactor is connected to the gate of the second transistor via a diode, and the other end of the first winding of the saturable reactor is connected to the first winding. Connected to the drain of the transistor,
One end of the second winding of the saturable reactor is connected to the control circuit, and the other end of the second winding of the variable reactor is connected to a source of the first transistor.
A converter characterized by that.

Images