JP4704328B2 - ΔΣ modulator and ΔΣ modulation type digital analog converter - Google Patents

Description

  The present invention relates to a delta-sigma modulator and a delta-sigma modulation type digital-analog converter that encode an input signal by delta-sigma modulation.

  In recent years, 1-bit encoding technology using ΔΣ modulation has been widely applied in fields such as digital audio and AD / DA conversion devices. For example, ΔΣ modulation is used in a class D amplifier that amplifies an input signal using switching by a transistor. Unlike Class A amplifiers, Class D amplifiers are used in the nonlinear region (saturated region) rather than in the linear region (unsaturated region) of the transistor, so power amplification is extremely efficient. Has the advantage of being able to

  The class D amplifier switches a constant voltage according to an input signal, and basically outputs a binary value of a voltage corresponding to an input signal indicating ON and a voltage corresponding to an input signal indicating OFF. That is, the class D amplifier amplifies binary input representing ON / OFF. Therefore, for example, when an audio signal is amplified by a class D amplifier, first, it is necessary to generate a binary signal corresponding to the waveform of the audio signal, that is, to encode the audio signal into a 1-bit signal. Then, a method using ΔΣ modulation has been put into practical use in encoding an audio signal into a 1-bit signal.

  FIG. 12 is a diagram showing a configuration of a conventional ΔΣ modulation type 1-bit amplifier 128. The ΔΣ modulation type 1-bit amplifier 128 includes a DA converter (DAC) 121, a subtractor 122, an analog integrator group 123, a quantizer 124, a class D amplifier 125, a low-pass filter (LPF) 126, and a feedback adjuster 127. Consists of. The ΔΣ modulation type 1-bit amplifier 128 amplifies an input signal digitally encoded by PCM (Pulse Code Modulation) and outputs it as an analog signal. The operation of the ΔΣ modulation type 1-bit amplifier 128 will be described below.

  The DA converter 121 receives a digital signal obtained by encoding an audio signal by PCM. The DA converter 121 converts the input digital signal into an analog signal and outputs the analog signal to the subtractor 122. Further, the switching pulse output from the class D amplifier 125 is fed back to the subtractor 122 via the feedback adjuster 127. The switching pulse and feedback output from the class D amplifier 125 will be described later.

  The subtractor 122 subtracts the switching pulse fed back via the feedback adjuster 127 from the analog signal input from the DA converter 121, generates a difference signal, and outputs the difference signal to the analog integrator 123. The analog integrator 123 integrates the difference signal input from the subtractor 122 and outputs it to the quantizer 124. The quantizer 124 quantizes the input from the analog integrator 123 to generate a quantized signal, and outputs the quantized signal to the class D amplifier 125. This quantized signal represents the waveform of the original input signal with a very fast frequency pulse distribution (the temporal density of the pulses).

  The class D amplifier 125 performs switching according to the quantized signal to switch the constant voltage. As a result, a high-voltage switching pulse corresponding to the quantized signal is generated, and the quantized signal is amplified. The class D amplifier 125 outputs the switching pulse to the low pass filter 126.

  The low-pass filter 126 demodulates the switching pulse and outputs the original audio signal as an amplified analog signal.

  As described above, the ΔΣ modulation type 1-bit amplifier 128 is provided with a feedback loop that negatively feeds back the switching pulse output from the class D amplifier 125 to the subtractor 122 via the feedback adjuster 127.

  At this time, the feedback adjuster 127 adjusts the magnitude of the switching pulse to be fed back. The feedback adjuster 127 is set with an optimum feedback gain so that the ΔΣ modulation operates stably, and the magnitude of the switching pulse to be fed back is appropriately adjusted. The feedback adjuster 127 feeds back a switching pulse delayed by one sample time.

  Thereby, the analog information contained in the output of the class D amplifier 125 including the power fluctuation noise and the switching error component in the class D amplifier 125 can be fed back. Therefore, since the power fluctuation noise and the switching error component can be corrected, SNR (Signal to Noise Ratio) is improved and THD (Total Harmonic Distortion) + N (Noise) is reduced.

  However, in the configuration of the ΔΣ modulation type 1-bit amplifier 128, it is necessary to include the DA converter 121 and the like in order to provide the above-described feedback loop for feeding back analog information, and the cost increases.

  Therefore, a configuration of a ΔΣ modulation type 1-bit amplifier that does not include the above-described feedback loop that feeds back analog information is conceivable.

  FIG. 13 is a diagram showing a configuration of a conventional ΔΣ modulation type 1-bit amplifier 138 that does not include a feedback loop for analog information.

  The ΔΣ modulation type 1-bit amplifier 138 includes a subtractor 131, a digital integrator 132, a quantizer 133, a class D amplifier 134, a low-pass filter (LPF) 135, and a feedback adjuster 136. Note that the subtractor 131, the digital integrator 132, the quantizer 133, and the feedback adjuster 136 constitute a ΔΣ modulator 137. The ΔΣ modulation type 1-bit amplifier 138 amplifies the input signal digitally encoded by the PCM and outputs it as an analog signal. The operation of the ΔΣ modulation type 1-bit amplifier 138 will be described below.

  The subtracter 131 receives a digital signal obtained by encoding an audio signal by PCM. The subtracter 131 feeds back the quantized signal output from the quantizer 133 via the feedback adjuster 136. The quantized signal and feedback output from the quantizer 133 will be described later.

  The subtractor 131 subtracts the quantized signal fed back via the feedback adjuster 136 from the input signal (that is, the digital signal obtained by encoding the audio signal by PCM) to generate a difference signal, and the digital integrator 2 Output to. The digital integrator 132 integrates the difference signal input from the subtracter 131 and outputs it to the quantizer 133. The quantizer 133 quantizes the input from the digital integrator 132 to generate a quantized signal, and outputs the quantized signal to the class D amplifier 134.

  The class D amplifier 134 performs switching according to the quantized signal to switch the constant voltage. As a result, a high-voltage switching pulse corresponding to the quantized signal is generated, and the quantized signal is amplified. The class D amplifier 134 outputs the switching pulse to the low pass filter 135.

  The low-pass filter 135 demodulates the switching pulse and outputs the original audio signal as an analog signal.

  As described above, the ΔΣ modulation type 1-bit amplifier 138 is provided with a feedback loop that negatively feeds back the quantized signal output from the quantizer 133 to the subtractor 131 via the feedback adjuster 136. .

  At this time, the feedback adjuster 136 determines the magnitude of the signal value to be fed back according to the value of the quantized signal. For example, if the quantized signal is a binary value of “1” and “0”, a signal value of “+ τ” is fed back in the case of “1”, and a signal of “−τ” in the case of “0”. Feedback the value. The feedback adjuster 136 is set with an optimal quantized signal magnitude “τ” for stable ΔΣ modulation operation, and the magnitude of the fed back signal is appropriately adjusted. The feedback adjuster 136 feeds back the quantized signal delayed by one sample time.

Here, the principle of ΔΣ modulation will be described based on the configuration of the ΔΣ modulation unit 137. FIG. 14 is a diagram modeling the configuration of the ΔΣ modulation unit 137. The subtracter 131 corresponds to the subtracter 141. The digital integrator 132 corresponds to a block 142 represented by a transfer function represented by 1 / (1-z ⁻¹ ). The feedback adjuster 136 corresponds to a block 143 represented by z- ¹ . Note that the quantizer 133 is considered as a model in which the adder 144 adds quantization noise Nq.

Here, if the input signal is X and the output signal is Y, the input to the block 142 is represented by XY · z ⁻¹ , and the output from the block 142 is (XY−z ⁻¹ ) / (1-z ^-1 )
Represented by

Since the output signal Y is obtained by adding the quantization noise nq to the output from the block 142, it has a relationship of Y = (XY · z ⁻¹ ) / (1−z ⁻¹ ) + Nq. When this is arranged for the output signal Y, Y = X + (1-z ⁻¹ ) · Nq.

This expression represents that the input X is output as it is, and the quantization noise Nq is output through a filter represented by a transfer function indicated by 1-z- ¹ .

1-z- ¹ is a transfer function of the differentiating circuit. Then, the low frequency component of the quantization noise Nq is suppressed by the differentiating circuit, that is, the high pass filter.

  Thus, according to the ΔΣ modulation unit 137, the quantization noise of the signal generated by 1-bit encoding is distributed only in the high frequency range. This is called noise shaping and is used to reduce quantization noise in the audible band (20 kHz or less).

  Therefore, even when a feedback loop for feeding back analog information included in the output from the class D amplifier 134 is not provided, it is possible to configure a ΔΣ modulation type 1-bit amplifier. In addition, since a DA converter or the like is not necessary, the cost can be suppressed.

  Note that the noise characteristics can be improved by changing the configuration of the integrator. FIG. 15 is a diagram illustrating a configuration of a fifth-order ΔΣ modulator. As shown in FIG. 15, the fifth-order ΔΣ modulator is configured to include five integrators. The high-order ΔΣ modulator will be described in more detail as follows.

The above-described ΔΣ modulator 137 is a first-order ΔΣ modulator having a single integrator, and reduces quantization noise by a filter represented by 1-z ⁻¹ . On the other hand, with the configuration of the fifth-order ΔΣ modulator shown in FIG. 15, the order of the filter indicated by 1-z ⁻¹ is also increased, and the effect of reducing the quantization noise is increased. However, in a third-order or higher-order ΔΣ modulator, an oscillation phenomenon occurs when the amplitude of the input signal increases. Therefore, a design for avoiding an oscillation state is required, such as a configuration in which an amplitude limiter is applied so that the gain is appropriately set and the integrator output does not exceed a certain value.

  In the description of the ΔΣ modulation type 1-bit amplifier described above, the configuration in which the waveform of the original input signal is represented by a binary signal is shown, but the configuration in which the waveform of the original input signal is represented by a ternary signal. You can also In this case, a ternary quantized signal is output from the quantizer, and the class D amplifier amplifies the ternary quantized signal.

  Note that the above-described configuration of the ΔΣ modulation type 1-bit amplifier can be applied to a DA conversion technique to configure a ΔΣ modulation type DA converter.

  In recent years, a technique using ΔΣ modulation has been proposed for an audio amplifier using a class D amplifier (switching amplifier). For example, Patent Document 1 discloses a signal for driving a switching amplifier (class D amplifier). Techniques for suppressing harmonic distortion are disclosed.

In the configuration described in Patent Document 1, an input digital signal is quantized by a ΔΣ modulator, and a switching amplifier is driven by a PWM signal generated by applying PWM (Pulse Width Modulation). Then, the harmonic distortion generated by the PWM is predicted in advance and suppressed by canceling out the harmonic distortion component. As means for predicting harmonic distortion, linear combination of products using signals representing the first-order and second-order time differential signals of the original input signal and the continuous-time signal corresponding to the input signal is used. At this time, the fundamental wave component generated by the third order distortion is also taken into consideration.
JP 2006-115028 (April 27, 2006)

  However, in the configuration of the above-described conventional ΔΣ modulation type 1-bit amplifier 138, analog information included in the output of the class D amplifier 134, including power fluctuation noise and switching error components in the class D amplifier 134, cannot be fed back. . Therefore, since the power fluctuation noise and the switching error component cannot be corrected, there is a problem that SNR (Signal to Noise Ratio) deteriorates and THD (Total Harmonic Distortion) + N (Noise) increases. This problem will be described in more detail as follows.

  FIG. 16 is a diagram illustrating a distribution of noise included in an output signal when a sine wave is input to a conventional ΔΣ modulation type 1-bit amplifier 138. FIG. 16 shows a frequency spectrum obtained by frequency analysis of the output signal from the ΔΣ modulation type 1-bit amplifier 138. The spectrum near 1 kHz is the signal component of the amplified fundamental wave (sine wave). Spectrum.

  On the other hand, a plurality of peaks occurring in the vicinity of 1 kHz to 10 kHz are spectra of harmonics (sine waves whose frequency is an integral multiple of the fundamental wave). That is, the output signal from the ΔΣ modulation type 1-bit amplifier 138 includes the harmonic component of the fundamental wave as noise in addition to the signal component obtained by amplifying the sine wave of the fundamental wave. The generation of the harmonic component causes the SNR to deteriorate and the THD + N to increase in the ΔΣ modulation type 1-bit amplifier 138.

  In the configuration of Patent Document 1, logical harmonics when ΔΣ modulation is converted into PWM can be corrected, but due to analog elements of the switching amplifier, that is, due to dead time and power supply fluctuation in the switching amplifier. The generated harmonics are not considered. Further, the distortion component larger than the third order is not taken into consideration. For this reason, the configuration of Patent Document 1 cannot suppress harmonics generated in the above-described ΔΣ modulation type 1-bit amplifier 138.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to suppress the generation of harmonics in a ΔΣ modulation DA converter that does not have an analog information feedback loop, and to achieve SNR (Signal to It is an object of the present invention to provide a ΔΣ modulator and a ΔΣ modulation type digital-to-analog converter with good noise ratio (THD) and total harmonic distortion (THD) + N.

  The delta-sigma modulator according to the present invention includes an integrating unit that integrates a difference between an input signal and a feedback signal, a quantizing unit that modulates an output of the integrating unit into a quantized signal having three values, A ΔΣ modulator comprising feedback value output means for outputting a feedback value to be fed back as a feedback signal in accordance with the three values, wherein the first feedback value is in descending order as a candidate to be output as the feedback value. , A second feedback value, and a third feedback value are prepared, the absolute value of the difference between the first feedback value and the second feedback value, and the absolute value of the difference between the second feedback value and the third feedback value, Are different from each other, and the feedback value output means uses either the first feedback value, the second feedback value, or the third feedback value. Or a, according to the three values of the quantized signal, and wherein the output as the feedback value.

  According to the above configuration, in the ΔΣ modulator, the integration unit integrates the difference between the input signal and the feedback signal, and the quantization unit quantizes the output of the integration unit to generate a three-valued quantized signal. . The quantized signal is a pulse composed of three voltage values, and the waveform of the original input signal is represented by pulse distribution (temporal density of the pulse). The three voltage values of the quantized signal can be considered in association with values such as “1”, “0”, and “−1”, respectively.

  The integrating means is not limited to a single integrator, and may include a plurality of integrators, and is not particularly limited. For example, the integrating means may be configured as an integrator group in which a plurality of integrators are cascaded and / or feedback connected through coefficients. That is, the integrating means may be an integrating means composed of a plurality of integrators in which a digital signal is one integrator or cascaded and / or partially fed back, and is not particularly limited.

  Further, in the ΔΣ modulator, the feedback signal is fed back and reflected in the input signal. The feedback value represented by the feedback signal is output from the feedback value output means. The feedback value output means outputs a feedback value corresponding to the three values of the quantized signal. The feedback values include a first feedback value, a second feedback value, and a third feedback value. Of the three feedback values, the first feedback value is the largest value, and the second feedback value is the second. It is a large value, and the third feedback value is the smallest value. Furthermore, the absolute value of the difference between the first feedback value and the second feedback value is different from the absolute value of the difference between the second feedback value and the third feedback value. The feedback value output means outputs any one of the first feedback value, the second feedback value, and the third feedback value according to the three values of the quantized signal from the quantization means. For example, the feedback value output means outputs the first feedback value when the quantized signal is “1”, the second feedback value when the quantized signal is “0”, and the third feedback value when the quantized signal is “−1”. Outputs the feedback value.

  Here, the feedback value output means may be configured to read the first to third feedback values from a lookup table or the like, or may be configured to include a selector to which a signal corresponding to the feedback value is input. There is no particular limitation.

  By the way, when a ternary quantized signal generated by ΔΣ modulation is amplified by a switching amplifier (class D amplifier), the characteristics of the P-Side and N-Side of the bridge circuit constituting the switching amplifier are different, that is, Due to the unbalanced characteristics of the switching amplifier, the pulse height of the ternary quantized signal has a positive pulse height (for example, a voltage value corresponding to the quantized signal “1”) and a negative pulse height ( For example, there is a problem that the waveform when demodulated is distorted, and as a result, even-order harmonics (noise components) are generated.

  In a conventional ΔΣ modulator that generates a three-valued quantized signal, the feedback value fed back according to the three values of the quantized signal is, for example, the feedback value when the quantized signal is “0”. When “0” is set, the feedback value when the quantized signal is “1” (for example, “+ τ”) and the feedback value when the quantized signal is “−1” (for example, “−τ”) are signed. Although the value is different because it is different, the size is the same. That is, the value fed back from the conventional ΔΣ modulator does not take into account the difference between the positive and negative pulse heights (asymmetric and unbalanced characteristics) generated in the switching amplifier.

  Therefore, the delta-sigma modulator according to the present invention has a configuration in which the output feedback value is asymmetrical in consideration of the difference between the positive and negative pulse heights (asymmetry and unbalance characteristics) generated in the switching amplifier described above. ing. That is, the absolute value of the difference between the first feedback value and the second feedback value is different from the absolute value of the difference between the second feedback value and the third feedback value. For example, when the feedback value corresponding to the quantized signal “0” is set to “0” (second feedback value), the feedback value output means outputs the feedback value “+ τ + α” (first value) when the quantized signal is “1”. 1 feedback value), and in the case of the quantized signal “−1”, the feedback value “−τ” (third feedback value) is output.

  Thereby, according to the delta-sigma modulator according to the present invention, when the quantized signal output from the own device is amplified in the switching amplifier, the unbalanced characteristic of the switching amplifier is considered according to the three-valued quantized signal. A feedback value can be output. Therefore, even when the quantized signal generated by ΔΣ modulation in the own device is amplified by a switching amplifier having an unbalanced characteristic, generation of even-order harmonics due to the unbalanced characteristic of the switching amplifier is suppressed. Can do.

  In the ΔΣ modulator according to the present invention, the feedback value output means converts the output feedback value of the first feedback value, the second feedback value, or the third feedback value to the three values of the quantized signal. It is preferable to have a selector to select accordingly.

  In the ΔΣ modulator according to the present invention, three signal lines for inputting signals to the selector are connected to the selector, and “+ τ”, “0”, “−τ” (τ ≠ 0) is input, and a correction value α (α ≠ 0) is externally added to or subtracted from one of the three signal lines, whereby the first feedback value, Preferably, the second feedback value or the third feedback value is generated, and these values are input to the selector.

  According to the above configuration, three signal lines for inputting signals are connected to the selector. Signals “+ τ”, “0”, and “−τ” are input to the three signal lines, respectively. Further, the correction value α (from the outside is applied to any one of the three signal lines. α ≠ 0) is added or subtracted. That is, a signal representing the first feedback value, the second feedback value, and the third feedback value is input to the selector from the three signal lines.

  As a result, the feedback value output from the feedback value output means can be easily adjusted by changing the correction value α.

  In the delta-sigma modulator according to the present invention, the feedback value output means includes the first feedback value, the second feedback value, and the third feedback that are associated with one of the three values of the quantized signal in advance. It preferably has a lookup table in which values are stored.

  A ΔΣ modulation type digital-analog converter according to the present invention includes the ΔΣ modulator, a switching amplifier that generates a switching pulse corresponding to the quantized signal, and a low-pass filter that demodulates the switching pulse. It is characterized by.

  According to the above configuration, the delta-sigma modulation type digital-analog converter includes the delta-sigma modulator, a switching amplifier that generates a switching pulse corresponding to the quantized signal, and a low-pass filter that demodulates the switching pulse. ing.

  Thereby, according to the ΔΣ modulation type digital-analog converter according to the present invention, feedback according to the unbalance characteristic of the switching amplifier is performed in the ΔΣ modulator. Therefore, the generation of even harmonics due to the unbalanced characteristics of the switching amplifier can be suppressed, a good SNR can be obtained, and THD + N can be reduced.

  In the ΔΣ modulation type digital-analog converter according to the present invention, the feedback value output means outputs the feedback value to be output from the first feedback value, the second feedback value, or the third feedback value to the quantized signal. And three signal lines for inputting a signal to the selector are connected to each of the selectors, and “+ τ”, “0”, “−” are connected to the respective signal lines. A signal having a value of τ ”(τ ≠ 0) is input, and further, the correction value α (α ≠ 0) is added or subtracted from the outside to any of the three signal lines. One feedback value, the second feedback value, or the third feedback value is generated, and these values are input to the selector. A ΔΣ modulation type digital-analog converter comprising a switching amplifier that generates a switching pulse and a low-pass filter that demodulates the switching pulse, when the sine wave is input as the input signal, A correction that performs frequency analysis of the output of the switching amplifier or the output of the ΔΣ modulation type digital-analog converter itself, and adjusts the correction value α based on the frequency spectrum of the even-order harmonic obtained as a result of the frequency analysis A value adjusting means is further provided.

  According to the above configuration, in the ΔΣ modulation type digital-analog converter according to the present invention, when the correction value adjusting unit inputs a sine wave as the input signal to the ΔΣ modulation type digital-analog converter, the sine wave The frequency of the output of the switching amplifier or the output of the ΔΣ modulation type digital analog converter itself with respect to the frequency is analyzed, and the correction value α is adjusted based on the frequency spectrum of the even harmonics obtained as a result of the frequency analysis. To do.

  Thereby, the correction value α can be changed according to the actual output from the ΔΣ modulation type digital-analog converter, and the feedback can be adjusted according to the unbalance characteristic of the switching amplifier. Therefore, even-order harmonics resulting from the unbalanced characteristics of the switching amplifier can be reliably suppressed.

  The delta-sigma modulator according to the present invention includes an integrating unit that integrates a difference between an input signal and a feedback signal, a quantizing unit that modulates an output of the integrating unit into a quantized signal having three values, A ΔΣ modulator comprising feedback value output means for outputting a feedback value to be fed back as a feedback signal in accordance with the three values, wherein the first feedback value is in descending order as a candidate to be output as the feedback value. , A second feedback value, and a third feedback value are prepared, the absolute value of the difference between the first feedback value and the second feedback value, and the absolute value of the difference between the second feedback value and the third feedback value, Are different from each other, and the feedback value output means uses either the first feedback value, the second feedback value, or the third feedback value. Or a, according to the three values of the quantized signal, and outputs it as the feedback value.

  Further, a ΔΣ modulation type digital-analog converter according to the present invention includes the above-described ΔΣ modulator, a switching amplifier that generates a switching pulse corresponding to the quantized signal, and a low-pass filter that demodulates the switching pulse. Yes.

  Further, a ΔΣ modulation type digital-analog converter according to the present invention includes the above-described ΔΣ modulator, a switching amplifier that generates a switching pulse corresponding to the quantized signal, and a low-pass filter that demodulates the switching pulse. ΔΣ modulation type digital analog converter, when a sine wave is input as the input signal, frequency analysis of the output of the switching amplifier or the output of the ΔΣ modulation type digital analog converter itself for the sine wave, A correction value adjusting means for adjusting the correction value α is further provided based on the magnitude of the frequency spectrum of the even harmonics obtained as a result of the frequency analysis.

  Therefore, it is possible to provide a ΔΣ modulation type digital-analog converter that suppresses the generation of even-order harmonics and has good SNR and THD + N.

  An embodiment of a ΔΣ modulation type digital-analog converter according to the present invention will be described below with reference to FIGS.

(ΔΣ modulation type digital analog converter 1)
FIG. 1 is a block diagram showing a configuration of a ΔΣ modulation type digital-analog converter 1 according to the present invention.
A ΔΣ modulation type digital-analog converter 1 according to the present invention includes a ΔΣ modulation unit (ΔΣ modulator) 2, a class D amplifier (switching amplifier; SW amplifier) 3, a low-pass filter (low-pass filter; LPF; Low Pass Filter). 4. The ΔΣ modulation unit 2 includes a subtractor 5, an integrator group (integrating means) 6, a quantizer (quantizing means) 7, and a bridge imbalance corrector (feedback value output means) 8.

  The ΔΣ modulation type digital-analog converter 1 converts an input signal digitally encoded by the PCM into an analog signal and outputs the analog signal. Hereinafter, the operation of the ΔΣ modulation type digital-analog converter 1 will be described.

  The subtracter 5 receives a digital signal obtained by encoding an audio signal or the like by PCM. A feedback value is fed back to the subtracter 5 as a feedback signal according to the quantized signal output from the quantizer 7 via the bridge imbalance corrector 8. The quantized signal output from the quantizer 7 and feedback will be described later.

  The subtracter 5 generates a difference signal by subtracting the quantized signal fed back via the bridge imbalance corrector 8 from the input signal, that is, the digital signal obtained by encoding the original signal (original signal) by the PCM. , Output to integrator group 6. The integrator group 6 integrates the difference signal input from the subtracter 5 and outputs it to the quantizer 7. The quantizer 7 quantizes the input from the integrator group 6 to generate a quantized signal and outputs it to the class D amplifier 3. The integrator group 6 has a configuration as shown in FIG. 15, for example.

  The class D amplifier 3 performs switching according to the quantized signal to switch the constant voltage. As a result, a high-voltage switching pulse corresponding to the quantized signal is generated, and the quantized signal is amplified. The class D amplifier 3 outputs the switching pulse to the low-pass filter 4.

  The low-pass filter 4 demodulates the switching pulse and outputs the original audio signal or the like as an analog signal.

  Further, in the ΔΣ modulation type digital-analog converter 1 according to the present invention, the ΔΣ modulation unit 2 generates a ternary quantized signal based on the input signal, and the class D amplifier 3 generates a ternary quantized signal according to the quantized signal. A switching pulse is output. Hereinafter, this is referred to as ternary operation.

  The present invention improves SNR and THD + N by reducing even-order harmonics generated in ternary operation. The even-order harmonic is a harmonic whose frequency is an even multiple of the fundamental wave.

  As described above, the ΔΣ modulation type digital-analog converter 1 is provided with a feedback loop for negatively feeding back the quantized signal output from the quantizer 7 to the subtractor 5 via the bridge imbalance corrector 8. It has been.

  The ΔΣ modulation type digital-analog converter 1 according to the present invention is characterized in that the bridge imbalance corrector 8 outputs a feedback value that reduces even-order harmonics. Thereby, the distortion of the waveform of the output signal is corrected, and the SNR and THD + N are improved.

  Before describing in detail the characteristic configuration of the present invention, that is, the configuration of the bridge imbalance corrector 8, the principle that even-order harmonics are generated by ternary operation will be described.

(Class D amplifier 3)
First, the configuration and operation of the class D amplifier 3 will be described in detail. FIG. 2 is a diagram showing an image of the configuration and operation of the class D amplifier 3. As shown in FIG. 2, the class D amplifier 3 includes a full bridge circuit including four MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) 21 to 24. The MOSFETs 21 and 22 constitute a P-Side bridge, and the MOSFETs 23 and 24 constitute an N-Side bridge. A load 25 is provided between the P-side bridge and the N-Side bridge. The load 25 schematically shows a speaker or the like that outputs sound based on a signal supplied from the class D amplifier 3. The MOSET 21 and the MOSFET 23 are connected to a constant voltage “+ V”, and the MOSFET 22 and the MOSFET 24 are connected to a constant voltage “−V”.

  Note that the quantized signal output from the ΔΣ modulation unit 3 has three values (for example, “+1”, “0”, “0”, “H (High)” and “L (Low)” in combination with two voltage values. “−1”). In other words, the ΔΣ modulation unit 3 outputs two voltage values to the class D amplifier 3, and the class D amplifier 3 outputs a ternary value to the load 25 according to the combination of the input voltage values “H” and “L”. Supply the signal.

  Further, “H” and “L” are invertedly input to the MOSFET 22 and the MOSFET 24 by an inverter (not shown).

  FIG. 2A is a diagram illustrating a state where an “H” voltage is input to the P-Side bridge and an “L” voltage is input to the N-Side bridge. In this case, in FIG. 2A, the MOSFET 21 and the MOSFET 24 are turned on. At this time, an electrical signal corresponding to “+1” is input to the load 25.

  FIG. 2B is a diagram illustrating a state in which the “L” voltage is input to the P-Side bridge and the “L” voltage is input to the N-Side bridge. In this case, in FIG. 2B, the MOSFET 22 and the MOSFET 24 are turned on. At this time, an electrical signal corresponding to “0” is input to the load 25.

  FIG. 2C is a diagram illustrating a state where an “L” voltage is input to the P-Side bridge and an “H” voltage is input to the N-Side bridge. In this case, in FIG. 2C, the MOSFET 22 and the MOSFET 23 are turned on. At this time, an electrical signal corresponding to “−1” is input to the load 25.

  FIG. 2D is a diagram showing an image when a low-pass filter (LPF) and a speaker are connected as the load 25 to the bridge circuit included in the class D amplifier 3. Then, a voltage of “H” or “L” is input to each of the P-Side and N-Side of the bridge circuit according to the ternary quantized signal. Then, as described with reference to FIGS. 2A to 2C, the load 25 has an electrical ternary value according to the combination of “H” and “L” input to the P-Side and the N-Side. A signal is input. The ternary signal input to the load 25 is demodulated into an analog signal by a low-pass filter, and sound is output from a speaker.

(Relationship between unbalanced characteristics of bridge circuit and even harmonics)
Hereinafter, the principle that even-order harmonics are generated in ternary operation will be described. As described above, the class D amplifier 3 outputs ternary values via a bridge circuit constituted by a P-Side bridge and an N-Side bridge. The even harmonics are generated due to the difference in characteristics between the P-Side and N-Side of this bridge circuit. Hereinafter, the relationship between the difference in characteristics between the P-Side and N-Side of the bridge circuit and the generation of even harmonics will be described in more detail.

  FIG. 3 is a diagram showing a waveform of a ternary signal output from a class D amplifier, (a) is a diagram showing an output when the characteristics of P-Side and N-Side are the same, and (b) These are figures which show an output when the characteristics of P-Side and N-Side are different.

  The positive voltage pulse, negative voltage pulse, and 0 V state shown in FIG. 3 correspond to the three values “+1”, “−1”, and “0” described with reference to FIG. . As shown in FIG. 3A, if the characteristics of P-Side and N-Side are the same, the height of the pulse waveform corresponding to “+1” and the height of the pulse waveform corresponding to “−1” are the same. is there. However, normally, the output varies for each element constituting the bridge circuit due to the influence of temperature or the like, and the operation characteristics differ between the P-Side and the N-Side constituting the bridge circuit.

  Therefore, as in the example shown in FIG. 3B, the pulse waveform corresponding to “+1” has a height lower than that of the pulse waveform corresponding to “−1”. The height of the waveform differs depending on the voltage pulse. And even if a ternary signal output from such a bridge circuit having different characteristics of P-Side and N-Side is demodulated by a low-pass filter, distortion occurs, so the waveform of the original input signal is It cannot be reproduced completely.

  FIG. 4 is a diagram illustrating an image in which distortion occurs in a sine wave in a class D amplifier configured by a bridge circuit (hereinafter referred to as an unbalanced bridge) having different characteristics of P-Side and N-Side. (a) is a figure which shows the sine wave before passing the class D amplifier comprised by an unbalanced bridge, (b) is a figure which shows the operating characteristic of the class D amplifier comprised by an unbalanced bridge, c) is a diagram showing a waveform of a signal output from a class D amplifier constituted by an unbalanced bridge.

  Below, the case where the class D amplifier 3 is comprised by the unbalanced bridge is demonstrated.

  FIG. 4B shows the relationship between the original signal X shown in FIG. 4A and the output signal Y shown by the solid line in FIG. 4C. The broken line shown in FIG. 4C shows the relationship between the original signal X and the output signal Y when no distortion occurs.

  As shown in FIG. 4B, in the region where the instantaneous value is negative, the original signal X and the output signal Y show a relationship of Y = X, but in the region where the instantaneous value is positive, the original signal X and the output are output. The slope of the straight line representing the relationship with the signal Y is smaller than the slope of the straight line representing the relationship of Y = X. Then, due to the characteristics of the class D amplifier 3 shown in FIG. 4B, the waveform of the original signal does not change in the negative region when passing through the class D amplifier 3, but the region where the instantaneous value is positive. Then, it attenuates and the output signal is distorted.

  Therefore, when the original signal having the sine wave waveform shown in FIG. 4A passes through the class D amplifier 3 having the characteristics shown in FIG. 4B, the output signal has an instantaneous value as shown in FIG. 4C. Distortion occurs in the positive region. In addition, the broken line of the area | region where the instantaneous value shown by FIG.4 (c) is positive has shown the waveform of the original signal shown to Fig.4 (a).

  FIG. 5 is a diagram showing the operating characteristics of the class D amplifier 3 constituted by an unbalanced bridge. FIG. 5A is a diagram showing the relationship between the original signal X and the output signal Y from the class D amplifier 3. The relationship between the original signal X and the output signal Y shown in FIG. 5A can be expressed by Y = GX + b | X |. Here, if Y1 = GX and Y2 = b | X |, the output signal Y can be decomposed into an output signal component Y1 (= GX) and an output distortion component Y2 (= b | X |).

  FIG. 5B is a diagram showing the relationship between the original signal X and the output signal component Y1. The broken line shown in FIG. 5B is a straight line showing the relationship of Y1 = X between the original signal X and the output signal Y1. The relationship between the original signal X and the output signal component Y1 shown in FIG. 5B is expressed by Y1 = GX (G <1), compared with the case where the original signal and the output signal are the same (when Y1 = X). It is represented by a straight line with a small inclination.

  FIG. 5C is a diagram showing the relationship between the original signal X and the output distortion component Y2. The relationship between the original signal X and the output distortion component Y2 shown in FIG. 5C is expressed by Y2 = b | X | (b <0), and the relationship between the original signal X and the output distortion component Y2 is expressed by the vertical axis. The output distortion component Y2 is a negative value regardless of whether the original signal X is positive or negative.

  That is, the operating characteristics of the class D amplifier 3 can be considered by being decomposed into the characteristics shown in FIG. 5B and the characteristics shown in FIG.

  FIG. 6 is a diagram illustrating that the output signal from the class D amplifier 3 includes even-order harmonics. FIG. 6A shows the waveform of the output signal Y from the class D amplifier 3 having the characteristics shown in FIG. FIG. 6A shows the waveform of the output signal Y from the class D amplifier 3 when the original signal X is a sine wave. As described with reference to FIG. 5, the output signal Y can be decomposed into an output signal component Y1 and an output distortion component Y2.

  FIG. 6B is a diagram showing the waveform of the output signal component Y1, and is obtained by the characteristics shown in FIG. As shown in FIG. 6B, the waveform of the output signal component Y1 is a sine wave with the same frequency f as the original signal X (that is, the period 1 / f) and a small amplitude.

  FIG. 6C is a diagram showing a waveform of the output distortion component Y2, which is obtained by the characteristics shown in FIG. As shown in FIG. 6C, the waveform of the output distortion component Y2 is a repetitive waveform having a frequency of 2f (that is, a period of 1 / 2f), that is, a frequency that is twice that of the original signal X.

  Therefore, the output signal Y from the class D amplifier 3 constituted by the unbalanced bridge shown in FIG. 6A is a signal component having a frequency more than twice that of the original signal X shown in FIG. It can be seen that the second harmonic is included.

(Bridge unbalance corrector 8)
As described above, the ΔΣ modulation type digital-analog converter 1 according to the present invention is characterized in that the bridge imbalance corrector 8 outputs a feedback value that reduces even-order harmonics. The configuration of the bridge imbalance corrector 8, that is, the characteristic configuration of the present invention will be described below.

  First, the adjustment of the feedback amount in the ternary operation of the conventional ΔΣ modulation type digital-analog converter will be described. The conventional ΔΣ modulation type digital-analog converter has the same configuration as the conventional ΔΣ type 1-bit amplifier 131 shown in FIG. Therefore, the ΔΣ type 1-bit amplifier 131 will be described as a conventional ΔΣ modulation type digital analog converter 131.

  The conventional ΔΣ modulation type digital-analog converter 131 adjusts the feedback amount in the feedback adjuster 136. In the case of ternary operation, a ternary quantized signal is input from the quantizer 133 to the feedback adjuster 136. Then, the feedback adjuster 136 determines a feedback value to be fed back according to the value of the quantized signal. For example, if the quantized signal has three values of “1”, “0”, and “−1”, a feedback value of “+ τ” is fed back when “1”, and “0” when “0”. The feedback value of “0” is fed back, and in the case of “−1”, the feedback value of “−τ” is fed back. In this case, although the signal value to be fed back differs between the case where the quantized signal is “1” and the case where the quantization signal is “−1”, the magnitude of the signal value is the same.

  In other words, in the conventional ΔΣ modulation type digital-analog converter, the feedback adjuster 136 is configured to set an optimum feedback value magnitude “τ” in order for the ΔΣ modulation to operate stably. When the ΔΣ modulation unit 137 has a digital circuit configuration, a digital value representing “τ” is set in the feedback adjuster 136. However, when the ΔΣ modulation unit 137 has an analog circuit configuration, the feedback adjuster 136 has a digital value. , Analog values representing “τ” (specifically, voltage values, current values, etc.) are set.

  Hereinafter, adjustment of the feedback amount in the bridge imbalance corrector 8 according to the present invention will be described.

  As described above, the pulse signal output from the class D amplifier 3 configured by the unbalanced bridge corresponds to the height of the pulse waveform corresponding to “+1” of the quantized signal and “−1” of the quantized signal. The height of the pulse waveform is different. Therefore, distortion occurs in the output signal from the class D amplifier 3, and as a result, even-order harmonics are included.

  Therefore, in the delta-sigma modulation type digital-analog converter 1 according to the present invention, the bridge unbalance corrector 8 takes into account the difference between the positive and negative pulse heights (asymmetry and unbalance characteristics) generated in the class D amplifier 3. Thus, the output feedback value is asymmetric. In the present embodiment, when the feedback value corresponding to the quantized signal “0” is “0”, the feedback value output means outputs the feedback value “+ τ + α” when the quantized signal is “1”. In the case of the quantized signal “−1”, the feedback value “−τ” is output. Here, τ ≠ 0. Note that α ≠ 0 when the bridge configuring the class D amplifier 3 is unbalanced, but α = 0 may be used when the bridge configuring the class D amplifier 3 is balanced. There is no particular limitation.

  Further, when the feedback value corresponding to the quantized signal “0” is other than “0”, for example, “1”, in the case of the quantized signal “1”, the feedback value “+ τ + α” is output, and the quantized signal “0” is output. In the case of “−1”, a configuration of outputting a feedback value “−τ” (in this case, τ> 1) is also included.

  In the present embodiment, in order to realize the above configuration, the bridge imbalance corrector 8 includes a lookup table in which the quantized signal is associated with the signal value to be fed back. FIG. 7 is a diagram showing the lookup table 14 provided in the bridge imbalance corrector 8. As illustrated in FIG. 7, “+ τ + α”, “0”, and “−τ” are associated as feedback values with the quantized signals “+1”, “0”, and “−1”, respectively.

  In this case, as a method for determining the correction value α, for example, the power spectrum of the output of the ΔΣ modulation type digital-analog converter 1 when a single frequency sine wave is input as the original signal is observed, and the correction value α When the value is changed from “+ τ” to “−τ”, the value of the correction ground α when the maximum power spectrum is the smallest among the power spectra of the even harmonics of the input sine wave is determined. Alternatively, a method of determining the value of “α” when the maximum power spectrum is closest to the noise floor can be considered.

  FIG. 8 is a diagram showing a power spectrum of the output of the ΔΣ modulation type digital-analog converter 1 when an appropriate correction value α is set in the bridge imbalance corrector 8. As shown in FIG. 8, it can be seen that even-order harmonics are suppressed as compared with the power spectrum diagram shown in FIG.

(Correction value adjustment device)
Furthermore, the ΔΣ modulation type digital-analog converter 1 according to the present invention may have a configuration including a correction value adjusting device that determines the value of “α” by the above-described method. FIG. 9 is a block diagram illustrating a configuration of the ΔΣ modulation type digital-analog converter 10 including the correction value adjusting device 9. The ΔΣ modulation type digital-analog converter 10 has a configuration in which a correction value adjusting device 9 is added to the ΔΣ modulation type digital-analog converter 1 shown in FIG. 1 and the bridge imbalance corrector 8 and the bridge imbalance corrector 11 are replaced. It is. The correction value adjusting device 9 calculates the correction value α based on the output from the low-pass filter 4 and outputs the calculated correction value α to the bridge imbalance corrector 8. When the quantized signal is “+1”, the bridge imbalance corrector 11 adds the correction value α input from the correction value adjusting device 9 to “+ τ” and feeds back. In the present embodiment, the correction value α is added. However, the correction value α may be subtracted and is not particularly limited.

  FIG. 10 is a diagram illustrating a configuration of the bridge imbalance corrector 11. As shown in FIG. 10, the bridge imbalance corrector 11 includes a selector 12 and an adder 13. As described above, in the bridge imbalance corrector 11, the adder 13 adds the correction value “α” input from the correction value adjusting device 9 to “+ τ”, and the selector 12 receives the quantized signal from the quantizer 7. A feedback value is output in response to. In the example illustrated in FIG. 10, the selector 12 outputs feedback values of “+ τ + α”, “0”, and “−τ” to the quantized signals “+1”, “0”, and “−1”, respectively. . The configuration of the selector 12 may be in a state in which the correction value α is added or subtracted in advance without including the adder 13, and is not particularly limited.

  FIG. 11 is a flowchart showing a flow of processing in which the correction value adjusting device 9 determines the correction value α.

  First, the correction value adjusting device 9 sets initial values. Specifically, the correction value adjusting apparatus 9 sets “0” as the correction value α and “+ ∞” as the variable E (S111).

  Next, the correction value adjusting device 9 performs a determination process for comparing the correction value α with the magnitude of the variable τ (S112). As a result of the determination process, when the correction value α is smaller, the correction value adjustment device 9 performs the processes from S113 to S118. Note that an upper limit value of the correction value α is set for the variable τ.

  In S118, the correction value adjusting device 9 sets a value obtained by adding the increase value d to the correction value α as a new correction value α. After S118, the process returns to S112 again. That is, the correction value adjusting device 9 repeatedly performs the processing from S113 to S118 while increasing the correction value α by the increment value d while the correction value α is smaller than the variable τ, thereby correcting the even-order harmonics most. Search for the value α.

  Below, the flow of the processing of S113 to S118 will be described.

  First, the correction value adjusting device 9 takes in the waveform output from the class D amplifier 3 (S113). At this time, a sine wave having a single frequency is input to the ΔΣ modulation type digital-analog converter 1 as an original signal. That is, the correction value adjusting device 9 captures the output of the ΔΣ modulation type digital-analog converter 1 when a single frequency sine wave is input as an original signal.

  Next, the correction value adjusting device 9 performs frequency analysis on the captured output signal, a value N indicating the size of the noise floor (hereinafter referred to as the noise floor value N), and an even order from 2 to 2n times. A harmonic power spectrum D2i (i = 1, 2,... N) is calculated (S114).

  Next, the correction value adjusting device 9 specifies the maximum power spectrum D2k (1 ≦ k ≦ i) among the power spectra of the even-order harmonics from 2 times to 2n times calculated in S114 (S115). The power spectrum D2k is a power spectrum of even-order harmonics of 2k times.

  Next, the correction value adjusting device 9 performs determination processing for comparing the result of subtracting the power spectrum D2k from the noise floor value N (hereinafter referred to as N-D2k) with the magnitude of the variable E (S116). If N-D2k is smaller than the variable E as a result of the determination process, the correction value adjusting device 9 substitutes N-D2k for the variable E and updates the variable E (S117). Further, the correction value adjusting device 9 holds the value of the correction value α at this time in the variable A. On the other hand, when the variable E is smaller than N−D2k as a result of the determination process, the correction value adjusting device 9 does not update the variable E.

  That is, the variable E holds the minimum value of the difference between the noise floor value N and the power spectrum value D2k when the correction value α is finally increased by the increase value d. The variable A holds a correction value α that minimizes the difference between the noise floor value N and the power spectrum value D2k when the correction value α is increased by an increase value d. That is, the value finally held in the variable A is a correction value that can suppress even-order harmonics most.

  Next, the correction value adjusting device 9 adds the increase value d to the correction value α, and updates the correction value α. Then, the process returns to S112.

  As a result of the determination process in step S112, when the correction value α is greater than or equal to the variable τ, that is, after the processing from S112 to S118 is completed for all the correction values α in the adjustment range, the correction value adjustment device 9 The value held in the variable A is output as the correction value α to the balance corrector 11 (S119), and the process is terminated.

  The present invention can also be expressed as follows.

(First configuration)
A plurality of integrating means connected in cascade, an adding means for adding outputs from the integrating means, and an output from the adding means are quantized into three values based on the sampling frequency fs to output a quantized signal. Quantizing means, a negative feedback loop for negatively feeding back the output from the quantizing means to the integrating means in the first stage, means for amplifying the quantized signal by a SW amplifier, and a signal amplified by the SW amplifier A delta-sigma modulation type DA converter that has a means for demodulating an analog signal with a band-pass filter and converts the digital input signal inputted to the integrating means in the first stage into an analog signal, and is negatively fed back 3 A delta-sigma modulation type DA converter characterized in that the interval between adjacent binary values can be made variable.

(Second configuration)
In addition, the power spectrum of the output of the DA converter when a single frequency sine wave is input to the DA converter is observed, and the largest of the harmonics of the even multiple of the input sine wave among the outputs. ΔΣ modulation type characterized in that the ternary interval to be fed back is determined by the value when the one becomes the smallest when the binary interval is varied or the value closest to the output noise floor DA converter.

  In addition, the configuration of the present invention includes an adder, a ΔΣ modulator, a SW amplifier, an LPF, a selector, a bridge imbalance correction circuit, and a correction value adjustment device, and outputs an output having the same frequency as the frequency of the input sine wave. The amplitude value of the fundamental wave and the amplitude value of the even harmonics of the fundamental wave are observed. The correction value adjusting device observes even-order harmonics (a component that is an even multiple of the fundamental wave) and the noise floor, and calculates a feedback correction value (α) when the even-order harmonics are closest to the noise floor. The value of α is changed from −τ to + τ, and the feedback correction value when the largest component of the even-order harmonics is minimized or when approaching the noise floor is α. The bridge imbalance correction circuit performs correction using the calculated feedback correction value (α). As a result, even-order harmonics are suppressed.

  Alternatively, the effects of the present invention can improve SNR and THD + N as compared with (a) a complete open-loop ΔΣ modulation analog-digital. (B) Since there is no analog feedback circuit from the SW amplifier, the circuit is simplified and the cost can be reduced. (C) It is possible to suppress a plurality of even harmonics with only one parameter. (D) By suppressing unnecessary harmonic components of the amplifier output, it is possible to contribute to energy saving.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  Finally, each block of the delta-sigma modulation type digital-analog converter 1 and the delta-sigma modulation type digital-analog converter 10, particularly the correction value adjusting device 9, may be configured by hardware logic, or as described below. It may be realized by software using

  That is, the correction value adjusting device 9 includes a CPU (central processing unit) that executes instructions of a control program that realizes each function, a ROM (read only memory) that stores the program, and a RAM (random access memory) that expands the program. ), A storage device (recording medium) such as a memory for storing the program and various data. An object of the present invention is a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program of the correction value adjusting apparatus 9 which is software that realizes the above-described functions is recorded in a computer-readable manner. Can also be achieved by reading the program code recorded on the recording medium and executing it by the computer (or CPU or MPU).

  Examples of the recording medium include a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  Further, the correction value adjusting device 9 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Further, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  The ΔΣ modulation type digital-analog converter of the present invention can be mounted on, for example, an audio device or a television.

It is a block diagram which shows the structure of the delta-sigma modulation type digital analog converter based on this invention. It is a figure which shows the structure and operation | movement image of a class D amplifier. It is a figure which shows the waveform of the ternary signal output from a class D amplifier, (a) is a figure which shows an output in case the characteristic of P-Side and N-Side is the same, (b) is P-Side. It is a figure which shows an output when the characteristic of N-Side differs. FIG. 7 is a diagram showing an image of distortion occurring in a sine wave in a class D amplifier configured by a bridge circuit (hereinafter referred to as an unbalanced bridge) having different characteristics of P-Side and N-Side. FIG. It is a figure which shows the sine wave before passing through the class D amplifier comprised by the balanced bridge, (b) is a figure which shows the operating characteristic of the class D amplifier comprised by the unbalanced bridge, (c) It is a figure which shows the waveform of the signal output from the class D amplifier comprised by a balanced bridge. It is a figure which shows the operation characteristic of the class D amplifier comprised by the unbalanced bridge, (a) is a figure which shows the relationship between the original signal X and the output signal Y from a class D amplifier, (b) FIG. 8 is a diagram illustrating a relationship between the original signal X and the output signal component Y1, and FIG. 8C is a diagram illustrating a relationship between the original signal X and the output distortion component Y2. It is a figure which shows that an even-order harmonic is contained in the output signal from a class D amplifier, (a) is a figure which shows the waveform of the output signal Y from the class D amplifier which has the characteristic of Fig.5 (a). (B) is a diagram showing a waveform of the output signal component Y1, and (c) is a diagram showing a waveform of the output distortion component Y2. It is a figure which shows the look-up table with which a bridge | bridging imbalance corrector is provided. It is a figure which shows the power spectrum of the output of a delta-sigma modulation type | mold digital analog converter at the time of setting appropriate correction value (alpha) in a bridge | bridging imbalance corrector. It is a block diagram which shows the structure of the delta-sigma modulation type digital analog converter provided with the correction value adjustment apparatus. It is a figure which shows the structure of a bridge | bridging imbalance corrector. It is a flowchart which shows the flow of a process in which the correction value adjustment apparatus determines correction value (alpha). It is a figure which shows the structure of the conventional delta-sigma modulation type 1-bit amplifier including the feedback loop of analog information. It is a figure which shows the structure of the conventional delta-sigma modulation | alteration 1 bit amplifier which does not include the feedback loop of analog information. It is the figure which modeled the structure of the delta-sigma modulation part. It is a figure which shows the structure of a 5th-order delta-sigma modulator. It is a figure which shows distribution of the noise contained in the output signal at the time of inputting a sine wave into the conventional delta-sigma modulation type 1-bit amplifier.

Explanation of symbols

1 ΔΣ modulation type digital analog converter 2 ΔΣ modulation unit (ΔΣ modulator)
3 Class D amplifier (switching amplifier)
4 Low-pass filter (low-pass filter)
5 Subtractor 6 Integrator group (integration means)
7 Quantizer (quantization means)
8 Bridge imbalance corrector (feedback value output means)
9 Correction value adjustment device (correction value adjustment means)
10 ΔΣ modulation type digital analog converter 11 Bridge imbalance corrector (feedback value output means)
12 Selector 13 Adder 14 Look-up table

Claims (2)

Integrating means including at least one integrator for integrating the difference between the input signal and the feedback signal, quantizing means for modulating the output of the integrating means into a quantized signal having three values, and three values of the quantized signal A ΔΣ modulator comprising feedback value output means for outputting a feedback value to be fed back as a feedback signal according to
As candidates output as the feedback value, a first feedback value, a second feedback value, and a third feedback value are prepared in descending order of the value,
One of the first feedback value and the third feedback value is a difference between positive and negative pulse heights generated in a switching amplifier that generates a switching pulse corresponding to the quantized signal output from the ΔΣ modulator. Is corrected in advance by a correction value α for canceling, and thereby, an absolute value of a difference between the first feedback value and the second feedback value, and an absolute value of a difference between the second feedback value and the third feedback value, Is different and
The feedback value output means includes
A lookup table storing the first feedback value, the second feedback value, and the third feedback value that are associated with one of the three values of the quantized signal in advance; One of the first feedback value, the second feedback value, and the third feedback value stored in the up table is output as the feedback value according to the three values of the quantized signal. ΔΣ modulator. A ΔΣ modulator according to claim 1 ;
The switching amplifier,
A ΔΣ modulation type digital-analog converter, comprising: a low-pass filter that demodulates the switching pulse.

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