JP2000269761A - Switching amplifier using δς modulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress gain difference between two feedback loops and to suppress noise by obtaining a minimum level of an arbitrary frequency component from a result, in which a potential difference of both output ends of a switching circuit is frequency analyzed, and in response to this, changing the attenuation factor of an attenuator. SOLUTION: The potential difference between pulse signals Eo1 and Eo2 from a constant voltage switch 9b is detected by a potential difference detection circuit 31, and a level of frequency component of its output is detected at a frequency analysis circuit 32. The result is given to a minimum value hold circuit 33, a minimum value of each frequency component level, that is, and quantization noise floor level is detected. According to the result, a gain changing circuit 34 changes the attenuation rate of an attenuator FB1 and changes a feedback loop gain. The circuit 33, for example, holds the minimum value of all the frequency components in a desired reproduced frequency band. At this time, the gain changing circuit causes 34 the attenuation factor of the attenuator FB1 to change so that all over the value of a hold value becomes minimum, controls the projecting component of a noise level and makes it flat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching amplifier using .DELTA..SIGMA. Modulation which can be suitably applied to an audio signal and which can amplify the audio signal with high efficiency.

[0002]

2. Description of the Related Art A 1-bit signal obtained by the above-mentioned .DELTA..SIGMA. Modulation can be used to widen an effective frequency band or a dynamic range by appropriately selecting coefficients of an integrator and an adder described later. In addition, the frequency characteristic can be set according to the sound source and the like. For this reason, CD (compact disc) and DV
The new standard of D (Digital Video Disk) adopts this 1-bit signal, and commercialization is about to begin this year.

On the other hand, the one-bit signal obtained by the ΔΣ modulation is used not only for recording an audio signal as described above and for transmission between devices, but also for directly inputting the one-bit signal to a semiconductor power amplifier. Then, the power-amplified demodulated analog audio signal can be obtained only by passing the obtained high-voltage switching pulse through a low-pass filter. Moreover, the semiconductor power amplifying element
Since the linear region (unsaturated region) is not used as in a conventional amplifier, but is used in a nonlinear region (saturated region), a switching amplifier using such ΔΣ modulation has extremely high efficiency. It has the advantage that power amplification can be performed, and commercialization is imminent.

FIG. 4 is a block diagram showing an electrical configuration of a switching amplifier 1 using a typical prior art ΔΣ modulation. An analog input audio signal from the analog signal source 2 is input to the switching amplifier 1 and first converted by the ΔΣ modulation circuit 3 into a 1-bit digital signal.

The ΔΣ modulation circuit 3 is provided, for example, in FIG.
, An integrator comprising a cascade-connected high-order integrator for sequentially integrating the input audio signal, and an adder for mutually adding outputs from the respective integrators. An adder group 4 and a quantizer 5 for quantizing an output from the adder of the integrator / adder group 4 into a 1-bit signal;
An attenuator 6 for attenuating a large voltage pulse signal from a constant voltage switch 9 described later, and an adder 8 for subtracting a pulse signal fed back from the attenuator 6 from the input audio signal.
It is comprised including. Thereby, the quantizer 5
The feedback control is realized so that the 1-bit signal from the input device corresponds to the input analog audio signal.

The 1-bit signal from the quantizer 5 is supplied to a constant-voltage switch 9, and a pulse signal of a predetermined constant voltage corresponding to the generated 1-bit signal is converted into an analog audio signal by a low-pass filter 10. After being demodulated, it is output and sonicated by the speaker 11.

The switching amplifier 1 configured as described above does not use the linear region (unsaturated region) of the semiconductor power amplifying element as in the conventional amplifier, but uses the semiconductor power amplifier used in the constant voltage switch 9. Since the amplification element is used in a non-linear range (saturation range), there is an advantage that power amplification can be performed with extremely high efficiency.

FIG. 5 is an electric circuit diagram of a constant voltage switch 9a which is a specific configuration example of the constant voltage switch 9. As shown in FIG. The constant voltage switch 9a is provided with a series circuit of semiconductor switching elements Q11 and Q12 between a power supply having a constant high potential + E ₀ and a constant low potential −E ₀ . The control input terminal of the semiconductor switching element Q11 becomes the input terminal P1, and receives a 1-bit signal from the quantizer 5 of the ΔΣ modulation circuit 3. On the other hand, the control input terminal of the semiconductor switching element Q12 has:
The one-bit signal is applied via an inversion buffer B1. The connection point of these semiconductor switching elements Q11 and Q12 becomes an output terminal P2, and outputs a power-amplified 1-bit signal to the low-pass filter 10.

FIG. 6 is a waveform diagram for explaining the operation of the constant voltage switch 9a. In response to the input 1-bit signal from the quantizer 5, the potential of the output signal becomes + E ₀
It is understood that changes between -E ₀ and. Therefore, even when a signal having a relatively small amplitude is output, + E
₀ or outputs large amplitude -E _0, in order to cancel it, so further so that repeated operation of outputting ... large amplitude -E ₀ or + E _0, there is a problem that power efficiency is poor . In order to solve such a problem, a constant voltage switch 9b as shown in FIG. 7 has been proposed.

FIG. 7 is an electric circuit diagram of a constant voltage switch 9b as another configuration example of the constant voltage switch 9. As shown in FIG. In the constant voltage switch 9b, a series circuit of the semiconductor switching elements Q11 and Q12 and a series circuit of the semiconductor switching elements Q21 and Q22 are provided between the high potential + E ₀ power supply and the low potential −E ₀ power supply. The semiconductor switching elements Q11 and Q11 are arranged in parallel with each other.
The connection point between the switching elements 12 becomes one output terminal P21, and the connection point between the semiconductor switching elements Q21 and Q22 becomes the other output terminal P22.

The control input terminal of the semiconductor switching element Q11 is supplied with a + 1-bit signal from an input terminal P11. The control input terminal of the semiconductor switching element Q12 receives the + 1-bit signal via an inversion buffer B1. Given. The control input terminal of the semiconductor switching element Q21 is supplied with a -1 bit signal from the input terminal P12, and the control input terminal of the semiconductor switching element Q22 receives the -1 bit signal from the inversion buffer B2.
Given through.

The operation waveform of the constant voltage switch 9b is shown in FIG.
Indicated by As is clear from FIG. 8, the output terminals P21, P21
Between 22, + 2E ₀ or well voltage -2E ₀ is applied, and a timing of applying zero voltage to between both output terminals P21, P22 is short-circuited. In this way, the period during which the 0 voltage is applied becomes longer at the time of the small signal, and the power efficiency can be further improved as compared with the constant voltage switch 9a.

[0013]

In the switching amplifier 1 configured as described above, when the constant voltage switch 9a is used, since the operation is a binary operation, the semiconductor switching element Q11 is turned on (Q12 is turned on). OFF) may be fed back. Therefore, for example, the pulse signal fed back to the input audio signal of 1 [V _PP ] is, for example, + E
It is +1.0 [V] when the pulse signal of ₀ is output, and −E ₀
Even when the pulse signal is -1.1 [V] at the time of output, the operation can be performed without any problem.

However, when the constant voltage switch 9b is used, the ternary operation is performed as shown in FIG. 8, so that, for example, a pulse fed back to the input voice signal of 1 [V _PP ] Signal is +1.0
As in [V] and -1.1 [V], if there is an error in the amplitude between the output of the + E ₀ pulse signal and the output of the -E ₀ pulse signal, noise is generated. There's a problem.

Therefore, a ΔΣ modulation signal having a dynamic range exceeding 100 [dB] includes, for example, an error of 1 [%] between two feedback loops. In some cases, it becomes narrow by several tens [dB]. For example, in FIG. 9, when the noise floor of the ΔΣ modulated signal when there is no signal is indicated by reference numeral α1, the noise causes the noise floor to rise as indicated by reference numeral α2. Note that the measurement data in FIG.
Is a measurement result when a 7th-order ΔΣ modulation circuit is used and a sine wave of 1 [kHz] and 0 [dB] is used as an input audio signal.

An object of the present invention is to provide a switching circuit using Δ ス イ ッ チ ン グ modulation which can suppress a noise difference between two feedback loops and suppress noise in negatively feeding back the voltages at both output terminals of a switching circuit to an input side. It is to provide an amplifier.

[0017]

Means for Solving the Problems Δ according to the invention of claim 1
In a switching amplifier using Σ modulation, a ΔΣ modulation circuit ΔΣ modulates a differential input signal, and in response to the modulated signal, a switching circuit switches a predetermined constant voltage from a power supply, and the switching output is switched by a low-pass filter. A switching amplifier that uses analog-to-digital conversion and outputs the voltages at both output terminals of the switching circuit to the input side of the ΔΣ modulation circuit by a feedback loop via an attenuator. Potential difference detecting means for detecting a potential difference between both output terminals of the switching circuit, wherein at least one of the two attenuators for attenuating a feedback signal from the circuit is made variable, Frequency analysis means for frequency-analyzing the output; From the analysis results of the analysis means,
A minimum value detecting means for detecting a minimum value level of an arbitrary frequency component; and a feedback gain changing means for changing an attenuation rate of the attenuator in response to a detection result of the minimum value detecting means. I do.

According to the above arrangement, the differential input signal
In a switching amplifier using ΔΣ modulation in which voltage at both output terminals of a switching circuit is fed back, at least one of two attenuators is made variable in attenuation rate, and a potential difference between both output terminals of the switching circuit is determined. From the result of the frequency analysis, focus on an arbitrary frequency component, for example, a component having a highest noise level which is determined by a ΔΣ modulation algorithm within a desired effective frequency band and which determines a dynamic range. The feedback gain is changed by changing at least one of the attenuation rates so as to be the minimum.

Therefore, a gain difference between the two feedback loops can be suppressed, and noise due to the gain difference can be suppressed.

In the switching amplifier using Δ 用 い る modulation according to the present invention, the minimum value detecting means includes:
The minimum value of all the frequency components over the desired reproduction frequency band is held, and the feedback gain changing means controls the attenuation rate of the attenuator so that the all-over value of the hold value is minimized. Is changed.

According to the above arrangement, the feedback gain is adjusted in the desired reproduction frequency band so as to suppress a component having a prominent noise level.

Therefore, a relatively flat noise level distribution can be obtained in the desired reproduction frequency band.

Further, the switching amplifier using Δ 係 る modulation according to the third aspect of the present invention further comprises an audibility correction filter interposed between the potential difference detecting means and the feedback gain changing means, and the minimum value detecting means is provided with: , Holding the minimum value level of all the frequency components over the desired reproduction frequency band, the feedback gain changing means, in accordance with the desired hearing characteristics,
In order to minimize the minimum level of each frequency component,
The attenuation rate of the attenuator is changed.

According to the above-mentioned structure, instead of having a flat noise level distribution over the entire range of the desired reproduction frequency band as in the second aspect, the audibility characteristic is such that the presence of noise can be tolerated in audibility. Accordingly, the feedback gain is adjusted so as to suppress the noise level of each frequency component. For example, the audibility correction filter is formed to have a pass characteristic opposite to the audibility characteristic. That is, a noise component sensitive to audibility is multiplied by a relatively large coefficient to increase its weight, and a noise component insensitive to audibility is increased. Is multiplied by a relatively small coefficient to reduce its weight, and the feedback gain is adjusted so that the noise level of each frequency component corrected in this manner has a flat distribution.

Therefore, only by adjusting as described above, it is possible to efficiently secure a dynamic range for necessary components in consideration of audibility characteristics.

In the switching amplifier using Δ 用 い る modulation according to the present invention, a partial feedback loop for zero point control is formed in the integrator / adder group of the ΔΣ modulation circuit, and the minimum value detection is performed. The means holds the minimum value level of the zero-point frequency component, and the feedback gain changing means changes the attenuation rate of the attenuator so that the hold value becomes minimum.

According to the above-described configuration, the zero point control is performed on a component whose noise level is to be suppressed, such as a component whose noise level is high in the algorithm or a component which is effectively suppressed for securing a dynamic range. Therefore, the feedback gain is adjusted so that the noise level is minimized by paying attention to the component.

Therefore, even if the frequency component of interest is small, it is possible to efficiently secure the dynamic range and reduce the frequency analysis and minimum value calculation processing.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 and 2 and FIG.

FIG. 1 is a block diagram showing an electrical configuration of a switching amplifier 21 according to one embodiment of the present invention.
This switching amplifier 21 is a three-value ΔΣ modulation switching amplifier using the constant voltage switch 9b shown in FIG. When the differential analog input audio signal from the analog signal source 22 is input to the ΔΣ modulation circuit 23 of the switching amplifier 21, the first analog audio signal in the integrator / adder group 24
In the integrator M1 at the stage, a feedback signal described later is subtracted. The integrator / adder group 24 is generally configured to include, for example, a 7th-order integrator and an adder for mutually adding outputs from the respective integrators, as described later. The output from the adder group 24 is input to the binary quantizers Q1 and Q2.

The binary quantizers Q1 and Q2 respond to a clock signal from a clock source (not shown) to output the output from the integrator / adder group 24 at a predetermined quantization reference value, respectively. Discriminate, + 1 bit signal Vo
Two switching signals of the 1 and -1 bit signal Vo2 are generated respectively. The 1-bit signals Vo1, Vo
2 is input to the constant voltage switch 9b, and the predetermined constant voltage pulse signals Eo1 and Eo2 corresponding to the generated 1-bit signals Vo1 and Vo2 are supplied to the low-pass filter 25.
After being demodulated into an analog audio signal at, it is output and is acoustically converted by the speaker 26.

The pulse signals Eo1 and Eo2 from the constant voltage switch 9b are also attenuated by the attenuators FB1 and FB2, and then, as the feedback signal, the first-stage integrator M1 in the integrator / adder group 24. And is subtracted from the input audio signal. Thus, feedback control is implemented so that the pulse signals Eo1 and Eo2 from the constant voltage switch 9b correspond to the input analog audio signal.

It should be noted that in the switching amplifier according to the present invention, the attenuation rate of at least one of the attenuators FB1 and FB2 (the attenuator FB1 in the example of FIG. 1) is variable, and the gain of the feedback signal is adjusted. Is variable, and the potential difference between the pulse signals Eo1 and Eo2 from the constant voltage switch 9b is detected by the potential difference detection circuit 31, and the frequency analysis circuit 32
In response to the analysis result of the above, the attenuation rate of the attenuator FB1 is changed.

The level of each frequency component of the output from the potential difference detecting circuit 31 is detected by a frequency analysis circuit 32 by FFT (Fast Fourier Transform) or the like. The detection result is supplied to the minimum value holding circuit 33, and the minimum value of the level of each frequency component, that is, the quantization noise floor level is detected. In response to the detection result, the gain changing circuit 34 changes the attenuation rate of the attenuator FB1, and changes the gain of the feedback loop. The minimum value hold circuit 33 holds, for example, the minimum value of all frequency components in a desired reproduction frequency band.

Here, the gain changing circuit 34 operates so that the all-over value of the hold value is minimized.
When the attenuation rate of the attenuator FB1 is changed, a feedback gain is adjusted so as to suppress a component having a prominent noise level in the desired reproduction frequency band, and the desired reproduction frequency band has a relatively flat noise level distribution. Become.

On the other hand, the minimum value hold circuit 3
3 is determined by the ΔΣ modulation algorithm and holds the minimum value of the component with the highest noise level that will determine the dynamic range. Therefore, even if the frequency components to be focused on are small, the dynamic range can be secured efficiently, and the calculation processing of the frequency analysis and the minimum value detection can be reduced. it can.

In terms of the above-mentioned algorithm, a zero point control as described with reference to FIG. 2 below is generally performed for a component having a high noise level or a component effective to suppress for securing a dynamic range. Is Therefore,
By paying attention to the frequency at which the zero point control is performed, the arithmetic processing of the frequency analysis and the minimum value detection can be reduced.

FIG. 2 is an electric circuit diagram showing a specific configuration example of the ΔΣ modulation circuit 23. In FIG. 2, FIG.
Are denoted by the same reference numerals. The attenuator FB1 is composed of a variable resistor VR1 realized by a so-called electronic volume or the like, and the attenuator FB2 is composed of voltage dividing resistors VD1 and VD2.

The first-stage integrator in the integrator / adder group 24 includes an amplifier A1 corresponding to the differential input audio signal.
2, and an integrator M12 including an amplifier A12. On the amplifier A11 side, one of the differential input audio signals is input resistance R11
1, and on the amplifier A12 side, the other of the differential input audio signals is applied via an input resistor R121. Feedback signals from the attenuators FB1 and FB2 are input to the amplifiers A11 and A12 via input resistors R112 and R122, respectively.
Therefore, on the input sides of the amplifiers A11 and A12, the input audio signal and the feedback signal are mutually added.
Outputs from the integrators M11 and M12 are mutually added by an amplifier A13.

The output from the amplifier A13 is the input resistance R2
1, a second-stage integrator M2 including an amplifier A2
Is input to The output from the integrator M2 is the input resistance R3
1 through a third stage integrator M3 having an amplifier A3.
Is input to A resistor R23 is provided between the integrators M2 and M3.
1, R232, R233 and amplifier A23,
A partial negative feedback loop for zero point control in ΔΣ modulation is formed.

The output from the integrator M3 is the input resistance R41
Is input to a fourth-stage integrator M4 including an amplifier A4, and the output thereof is input to a fifth-stage integrator M5 including an amplifier A5 via an input resistor R51. The resistors R451, R452, and R4 are also provided between the integrators A4 and A5.
53 and an amplifier A45, and a partial negative feedback loop for the zero point control is formed.

The output from the integrator M5 is the input resistance R
61 through a sixth stage integrator M having an amplifier A6
6 and its output is input through an input resistor R71.
The signal is input to a seventh-stage integrator M7 including an amplifier A7. The resistors R671 and R67 are also provided between the integrators M6 and M7.
2, a partial negative feedback loop composed of R673 and amplifier A67 for zero point control is formed.

The outputs from the integrators M1 (M11 and M12 are collectively referred to), M2, M3, M4, M5, M6 and M7 are output from resistors R10, R20, R30 and R4, respectively.
The coefficients are processed through 0, R50, R60, and R70 and are added to each other. The adder is configured to include a negative adder including an amplifier A81, a positive adder including an amplifier A82, and an adder including an amplifier A83 for mutually adding their outputs. . In the example shown in FIG. 2, odd-order integrators M1, M3, 5, M
7 are added by an amplifier A81, and outputs from even-order integrators M2, M4, and M6 are added by an amplifier A82. The output from the amplifier A83 is input to the quantization circuit 27.

The quantization circuit 27 includes two binary quantizers Q1 and Q2 each comprising a hysteresis comparator.
And resistors R1, R2, which create their quantization reference values.
R3. The resistors R1, R2,
The series circuit of R3 includes a power supply on the high potential + 5V side and a low potential-
It is interposed between the power supply on the 5V side.

The ΔΣ modulation circuit 23 configured as described above
, The resistors R10, R20, R30, R40,
R50, R60, R70 and input resistors R21, R31, R
The noise shaping characteristics (quantization noise floor) can be changed by changing the resistance values of R41, R51, R61, R71, etc., and the gain of the partial negative feedback loop can be changed by changing the gain of FIG. It is possible to change the dip amount and the zero-point frequency of the zero-point control as indicated by reference numerals d1, d2, and d3. The gain changing circuit 34 adjusts the feedback gain as described above by changing the resistance value of the variable resistor VR1 according to the noise shaping characteristics and the zero point frequency.

Another embodiment of the present invention will be described below with reference to FIG.

FIG. 3 is a block diagram showing an electrical configuration of a switching amplifier 41 according to another embodiment of the present invention. This switching amplifier 41 is similar to the above-described switching amplifier 21, and corresponding portions are denoted by the same reference numerals and description thereof will be omitted. It should be noted that in the switching amplifier 41, any portion between the potential difference detection circuit 31 and the gain change circuit 34 (in the example of FIG. 3, the minimum value hold circuit 33 and the gain change circuit 34
) Is provided with the audibility correction filter 42.

The audibility correction filter 42 is, for example, an ATRAC (Adaptive) which is a compression encoding method for a mini disk.
Like Transform Acoustic Coding, the attenuation rate of the attenuator FB1 is changed so that the minimum value level of each frequency component is minimized in accordance with the masking characteristic of human hearing. That is, the audibility correction filter 42 is formed to have a pass characteristic opposite to the audibility characteristic. Therefore, a noise component that is sensitive to audibility is multiplied by a relatively large coefficient to increase its weight, and the audibility is insensitive. The noise component is multiplied by a relatively small coefficient to reduce its weight. The gain changing circuit 3 is configured so that the noise level of each frequency component corrected in this manner has a flat distribution.
4 adjusts the feedback gain.

As a result, the feedback gain is adjusted so as to suppress the noise level of each frequency component in accordance with the audibility characteristics, so that the adjustment can be performed with relatively easy adjustment without performing high-precision matching. The dynamic range can be efficiently secured for various components.

[0050]

As described above, the switching amplifier using ΔΣ modulation according to the first aspect of the present invention uses ΔΣ modulation in which the voltages at both output terminals of the switching circuit are fed back to the differential input signal. In the switching amplifier, based on the frequency analysis result of the potential difference between both output terminals of the switching circuit, the attenuation rate of at least one of the two attenuators is changed so that the noise level of an arbitrary frequency component is minimized. To change the feedback gain.

Therefore, a gain difference between the two feedback loops can be suppressed, and noise due to the gain difference can be suppressed.

Further, in the switching amplifier using ΔΣ modulation according to the second aspect of the present invention, as described above, the minimum value of all the frequency components over the desired reproduction frequency band has the smallest all-over value. In this manner, the feedback gain is adjusted so as to suppress a component having a prominent noise level.

Therefore, within the desired reproduction frequency band,
A relatively flat noise level distribution can be obtained.

Further, the switching amplifier using ΔΣ modulation according to the third aspect of the present invention further includes an audibility correction filter between the potential difference detecting means and the feedback gain changing means as described above. The feedback gain is adjusted so as to suppress the noise level of each frequency component in accordance with the audibility characteristics that can allow the presence of.

Therefore, the dynamic range can be efficiently secured for the necessary components in consideration of the audibility characteristics.

In the switching amplifier using ΔΣ modulation according to the fourth aspect of the present invention, as described above, a component having a high noise level, a component effective to suppress for securing a dynamic range, and the like are algorithmically used. In particular, the feedback gain is adjusted so that the minimum value of the zero-point frequency component of the zero-point control performed particularly on the component whose noise level is desired to be suppressed is minimized.

Therefore, even if the frequency component of interest is small, the dynamic range can be efficiently secured, and the calculation processing of the frequency analysis and the minimum value detection can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a switching amplifier using a ΔΣ modulation circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of a ΔΣ modulation circuit in the switching amplifier shown in FIG.

FIG. 3 is a block diagram showing an electrical configuration of a switching amplifier using a ΔΣ modulation circuit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing an electrical configuration of a switching amplifier using a typical prior art ΔΣ modulation circuit.

FIG. 5 is an electric circuit diagram illustrating a configuration example of a constant voltage switch used in a switching amplifier that performs binary ΔΣ modulation.

FIG. 6 is a waveform chart for explaining the operation of the constant voltage switch shown in FIG.

FIG. 7 is an electric circuit diagram showing another configuration example of the constant voltage switch used in the switching amplifier that performs three-value ΔΣ modulation.

FIG. 8 is a waveform chart for explaining the operation of the constant voltage switch shown in FIG. 7;

FIG. 9 is a graph showing quantization noise characteristics when there is an error in a feedback loop gain in a conventional switching amplifier of ternary ΔΣ modulation.

[Explanation of symbols]

9b Constant voltage switch 21, 41 Switching amplifier 22 Analog signal source 23 ΔΣ modulation circuit 24 Integrator / adder group 25 Low pass filter 26 Speaker 27 Quantization circuit 31 Potential difference detection circuit (potential difference detection means) 32 Frequency analysis circuit (Frequency analysis means) 33) minimum value hold circuit (minimum value detecting means) 34 gain changing circuit (feedback gain changing means) 42 audibility correction filter FB1 attenuator (feedback gain changing means) FB2 attenuator M11, M12, M2 to M7 integrators Q1, Q2 Binary quantizer R1, R2, R3 Resistance R10, R20, R30, R40, R50, R60, R
70 Resistance R21, R31, R41, R51, R61, R71
Input resistance VR1 Variable resistor (feedback gain changing means) VD1, VD2 Voltage dividing resistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J064 AA02 BA03 BB02 BB12 BC07 BC11 BC19 BD03 5J100 JA01 KA05 LA00 LA13 QA02 SA00

Claims (4)

[Claims] A .DELTA..SIGMA. Modulation circuit performs .DELTA..SIGMA. Modulation on a differential input signal, and a switching circuit switches a predetermined constant voltage from a power supply in response to the modulated signal. The switching output is converted into an analog signal by a low-pass filter. And a voltage at both output terminals of the switching circuit is negatively fed back to the input side of the ΔΣ modulation circuit by a feedback loop via an attenuator.
In a switching amplifier using modulation, at least one of two attenuators for attenuating a feedback signal from the switching circuit is made variable, and a potential difference between two output terminals of the switching circuit is detected. Means, frequency analysis means for frequency-analyzing the output from the potential difference detection means, minimum value detection means for detecting the minimum level of an arbitrary frequency component from the analysis result of the frequency analysis means, and said minimum value detection means And a feedback gain changing means for changing an attenuation rate of the attenuator in response to a detection result of (i). 2. The minimum value detecting means holds the minimum value of all frequency components in a desired reproduction frequency band, and the feedback gain changing means sets an all over value of the hold value to To be the smallest
2. The switching amplifier using ΔΣ modulation according to claim 1, wherein an attenuation rate of said attenuator is changed. 3. An audibility correction filter interposed between the potential difference detecting means and the feedback gain changing means, wherein the minimum value detecting means has a function of detecting all frequency components in a desired reproduction frequency band. The minimum gain level is held, and the feedback gain changing means changes the attenuation rate of the attenuator so that the minimum level of each frequency component is minimized in accordance with a desired auditory characteristic. The switching amplifier according to claim 1, wherein the switching amplifier uses ΔΣ modulation. 4. A partial feedback loop for zero point control is formed in an integrator / adder group of the ΔΣ modulation circuit, and the minimum value detection means holds a minimum value level of the zero frequency component. The feedback gain changing means, so that the hold value is minimized,
2. The switching amplifier using ΔΣ modulation according to claim 1, wherein an attenuation rate of said attenuator is changed.