JP4675646B2 - Liquid crystal display device - Google Patents

Description

  The present invention generally relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a function of correcting luminance unevenness.

  In a liquid crystal display (LCD), pixels including transistors are arranged vertically and horizontally, a gate bus line extending in the horizontal direction is connected to a gate of the transistor of each pixel, and a data bus line extending in the vertical direction passes through the transistor. Connected to the pixel electrode of each pixel. The pixel electrode faces the common electrode (counter electrode) through the liquid crystal layer, and forms a capacitor corresponding to each pixel. When displaying data on the liquid crystal panel, the gate bus line is sequentially driven line by line by the gate driver to turn on the transistors for one line, and the horizontal 1 to each pixel from the data driver through the conductive transistors. Write line data all at once.

  FIG. 1 is a diagram showing a configuration of a conventional liquid crystal display device.

  The liquid crystal display device in FIG. 1 includes an LCD panel 10, a timing controller 11, a plurality of gate drivers 12, and a plurality of data drivers 13. In the LCD panel 10, pixels including transistors (not shown) are arranged vertically and horizontally, a gate bus line GL extending in the horizontal direction from the gate driver 12 is connected to the gate of the transistor of each pixel, and data extending in the vertical direction from the data driver 13. The bus line DL is connected to the capacitor of each pixel through a transistor.

  The timing controller 11 receives a clock signal, display data, and a display enable signal indicating the timing of the display position from the outside via the interface I / F. The timing controller 11 determines the timing of the horizontal position by counting the clock pulses of the clock signal from the rising edge of the display enable signal, and generates various control signals. Furthermore, the timing controller 11 determines the timing of the vertical position by counting the number of display enable signals, and generates various control signals. Further, by detecting the position where the LOW period of the display enable signal continues for a certain number of clock pulses or more, the head position of each frame can be detected.

  The control signal supplied from the timing controller 11 to the gate driver 12 includes a gate clock signal and a start pulse signal. The gate clock signal is a synchronization signal for shifting the gate bus line driven in synchronization with the rising edge of the signal one line at a time. The transistors for one horizontal line where the gate is turned on are synchronized with the rising edge of the signal. This corresponds to shifting in the vertical direction line by line. The start pulse signal is a synchronization signal that specifies the timing for turning on the leading gate bus line, and corresponds to the start timing of the frame.

  The control signal supplied from the timing controller 11 to the data driver 13 includes a dot clock signal, a data start signal, a latch pulse, and a polarity signal. The dot clock signal is a clock pulse for fetching display data into the register in synchronization with the rising edge. The data start signal is a signal indicating the start position of display data for the amount displayed by the data driver 13. Using the timing of the data start signal as a starting point, display data corresponding to each pixel is sequentially taken into the register by a dot clock signal. The latch pulse is a signal for latching display data sequentially fetched into the register into the internal latch. The latched display data signal is transferred to the DA converter, converted into an analog gradation signal by the DA converter, and output to the LCD panel 10 as a data bus line drive signal. The polarity signal is a signal input to the DA converter, and indicates the output polarity of each data bus line by this signal. In order to prevent deterioration of the characteristics of the liquid crystal, an operation of inverting the output polarity of each data bus line with respect to time is necessary. Therefore, the polarity of each data bus line with respect to the common voltage is selected using this polarity signal.

In a liquid crystal display device, unevenness may occur on the screen when the display brightness on the screen is locally darker or brighter than the desired brightness. Such unevenness is caused by variation in the thickness of the liquid crystal display cell, variation in the thickness of the electrode pattern, and the like in the liquid crystal display device. In order to improve the quality and yield rate of the liquid crystal display device, it is necessary to devise correction for luminance unevenness of an image displayed on the liquid crystal panel.
JP 7-129127 A JP-A-8-184809

  Some of the uneven brightness of an image depends on the image data to be displayed, and one such unevenness is crosstalk. As shown in FIG. 2, the crosstalk is caused by the pattern 16 in the upper and lower regions 17 or the left and right regions 18 of the pattern 16 when a specific pattern 16 is partially displayed in the display region 15 of the liquid crystal panel. The brightness change is generated. Thereby, when the periphery of the pattern 16 should be displayed with, for example, uniform brightness (uniform gradation), nonuniform brightness unevenness appears. The luminance change that occurs in the upper and lower portions of the pattern 16 is called vertical crosstalk, and the luminance change that occurs in the left and right portions is called horizontal crosstalk.

  As a cause of the lateral crosstalk, a fluctuation of the common electrode potential due to capacitive coupling between the data bus line and the common electrode can be mentioned. The common electrode is a common electrode that extends over the entire display area. There is a liquid crystal layer between the data bus line and the common electrode, which causes capacitive coupling.

  As described above, it is necessary to invert the output polarity of each data bus line with respect to time in order to prevent deterioration of liquid crystal characteristics. In the dot inversion driving method, the output polarity of the data bus line is inverted between adjacent data bus lines, and is further inverted every horizontal cycle in terms of time. In such a dot inversion driving method, for example, if the data is the same for all the pixels in the horizontal direction, the sum of the potentials of the positive data bus line and the potential of the negative data bus line in a certain horizontal cycle. The total is balanced and the total potential of all data bus lines is zero. In this case, when moving from one horizontal cycle to the next horizontal cycle, the total potential of all data bus lines does not change, and the potential of the common electrode is not affected by capacitive coupling with the data bus lines.

  However, when one pixel white dot and one pixel black dot are alternately arranged in the horizontal direction, the sum of the potentials of the positive data bus lines and the sum of the potentials of the negative data bus lines are not balanced, The total potential of all data bus lines becomes a positive or negative value. In this case, the potential of the common electrode swings positively or negatively due to capacitive coupling with the data bus line. In the dot inversion driving method, the polarity of each data bus line is inverted every horizontal period. Therefore, assuming that the pixel data does not change in the vertical direction (that is, a vertical stripe pattern), from one horizontal period to the next horizontal period When moving, the total potential of all data bus lines will vary from positive to negative or from negative to positive. Therefore, the potential of the common electrode also varies due to capacitive coupling with the data bus line.

  When the common electrode potential fluctuates from a predetermined potential (0 V) in a certain horizontal period, the potential difference between the common electrode and the pixel electrode becomes excessive and insufficient for all the pixels on the horizontal line, and an incorrect pixel voltage is generated by one frame. It will be retained for a period. Therefore, for example, in FIG. 2, when the pattern 16 is a vertical stripe having a width of one pixel, a luminance change occurs in the left and right regions 18.

  The cause of vertical crosstalk is a change in pixel potential due to capacitive coupling between the data bus line and the pixel electrode. A parasitic capacitance between the drain and the source of the thin film transistor exists between the data bus line and the pixel electrode. When the potential of the data bus line changes after writing the data potential to a certain pixel, the potential change is transmitted to the pixel electrode through capacitive coupling, and the potential of the already written pixel fluctuates. Thereby, for example, in FIG. 2, when the pattern 16 has a luminance different from the surrounding area, a luminance change occurs in the upper and lower regions 17.

  In view of the above, an object of the present invention is to provide a liquid crystal display device in which luminance unevenness due to crosstalk is reduced.

A liquid crystal display device according to the present invention includes a liquid crystal panel that includes a plurality of pixels that function to hold a data potential and displays an image according to the data potential; receives display data of the plurality of pixels; A potential fluctuation calculation circuit for calculating a potential change that the display data of at least one other pixel gives to the data potential of one of the pixels through capacitive coupling; and the potential fluctuation calculated by the potential fluctuation calculation circuit A data correction circuit that corrects the display data of the one pixel, and a data driver that supplies a data potential corresponding to the corrected display data to the liquid crystal panel, and the liquid crystal panel includes one common electrode If, it includes a plurality of pixel electrodes respectively corresponding to the pixels of the plurality of, the said potential variation calculation circuit of the one generated via the capacitance between the pixel electrode and the data bus lines of the pixel the one And calculates the potential variation of the pixel electrodes of the unit as a said potential change.

  According to at least one embodiment of the present invention, the potential fluctuation calculation circuit calculates the potential fluctuation causing the crosstalk based on the display data. This potential fluctuation is a potential fluctuation of the common electrode when correcting the horizontal crosstalk due to the capacitive coupling between the data bus line and the common electrode, and when correcting the vertical crosstalk due to the capacitive coupling between the data bus line and the pixel electrode. Is the potential fluctuation of the pixel electrode. The data correction circuit corrects the display data based on the potential fluctuation calculated by the potential fluctuation calculation circuit.

  In this way, the display data supplied to the data driver is corrected by the amount corresponding to the potential variation of the common electrode or the amount corresponding to the potential variation of the pixel electrode. As a result, the data potential written to each pixel from the data driver via the data bus line can be corrected to reduce crosstalk.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram showing a configuration around the timing controller in the liquid crystal display device according to the present invention. The timing controller shown in FIG. 3 shows a portion for driving the data driver, and the crosstalk reduction of the present invention is realized by correcting the display data supplied to the data driver. By incorporating the configuration shown in FIG. 3 into the timing controller 11 of the liquid crystal display device shown in FIG. 1, the liquid crystal display device according to the present invention can be configured.

  The timing controller 21 in FIG. 3 includes a crosstalk potential fluctuation calculation circuit 31 and a data correction circuit 32. A display data storage RAM 22 and a panel parameter storage RAM 23 are connected to the timing controller 21.

  When the timing controller 21 receives the display data, the crosstalk potential fluctuation calculation circuit 31 calculates the potential fluctuation causing the crosstalk based on the display data. This potential fluctuation is a potential fluctuation of the common electrode when correcting the horizontal crosstalk due to the capacitive coupling between the data bus line and the common electrode, and when correcting the vertical crosstalk due to the capacitive coupling between the data bus line and the pixel electrode. Is the potential fluctuation of the pixel electrode. The data correction circuit 32 corrects the display data based on the potential fluctuation calculated by the crosstalk potential fluctuation calculation circuit 31.

  When correcting the horizontal crosstalk, the potential change of the data bus line at the time of transition from one horizontal line to the next horizontal line is summed up for all the data bus lines, and based on the sum of this potential change, the common electrode The potential fluctuation is calculated. When correcting the vertical crosstalk, after the display data potential is written to the target pixel in a certain frame, the sum of the potential fluctuations of the adjacent data bus line until the display data is written to the target pixel in the next frame is obtained. The potential fluctuation of the pixel electrode of the target pixel is calculated.

  The display data storage RAM 22 stores display data. In the configuration of FIG. 3, the display data supplied to the timing controller 21 is not corrected in real time, but the display data is corrected based on the potential fluctuation after the potential fluctuation is calculated based on the display data. become. Accordingly, display data is temporarily stored in the display data storage RAM 22 and correction processing is executed on the stored display data.

  The panel parameter storage RAM 23 stores various parameters of the LCD panel to be driven. For example, the potential fluctuation amount of the common electrode is not only the total potential variation amount for all the data bus lines, but also the capacitance between the data bus line and the common electrode, the impedance between the common electrode and the common power source, the data bus It depends on the time from the switching of the data potential of the line until the gate voltage is turned off. These parameters are different for each LCD panel model or for each individual model. Therefore, parameters necessary for potential fluctuation calculation are set in the panel parameter storage RAM 23 for each model or individual of the LCD panel. The panel parameter storage RAM 23 also stores data indicating the relationship between display data gradation and data voltage, as will be described later.

  Hereinafter, a case where lateral crosstalk is reduced will be described as a first embodiment of the crosstalk reduction processing according to the present invention.

  FIG. 4 is a diagram for explaining the horizontal crosstalk reduction processing. In the lower part of FIG. 4, the potential of the even data bus line is indicated by a dotted line, and the potential of the odd data bus line is indicated by a solid line. In this example, a pattern is assumed in which white dots and black dots appear alternately for each pixel in the horizontal direction. For example, even data bus lines are displayed in white and odd data bus lines are displayed in black. . Since the data potential of the data bus line is inverted every horizontal period, the even data bus line shows a large potential fluctuation from negative to positive and the odd data bus line is positive from the positive as shown by the arrow in the lower part of FIG. It will show a small potential fluctuation to negative.

  The potential of the common electrode that is capacitively coupled to the data bus line varies according to the difference in potential variation. The upper part of FIG. 4 shows the common electrode potential and the gate potential applied to the gate of the pixel transistor. The common potential changes by ΔVcom0 according to the potential fluctuation of the data bus line. Thereafter, as the positive charge is released from the common electrode to the common power supply with time, the common electrode potential gradually decreases.

  The gate potential applied to the gate of the pixel transistor is turned on at the timing of writing display data to the pixel electrode. In the example of FIG. 4, the gate is on and the transistor is in a conducting state in the period between T1 and T2. Since the gate is closed at the timing T2, the difference between the common electrode potential and the pixel electrode potential at T2 is accumulated in the pixel as a data potential. Therefore, the potential fluctuation of the common electrode that appears as an error in display data is ΔVcom at the timing T2.

  ΔVcom0 and ΔVcom can be calculated by the following equations.

ΔVcom0 ＝ Vdto × Cdc / Ctot (1)
ΔVcom = ΔVcom0 × (1-exp (−ton / (RCtot)) (2)
Here, R is the connection resistance between the common power supply and the common electrode, Ctot is the total capacitance of the common electrode, Cdc is the drain-common coupling capacitance, and ton is the time from the switching of the data voltage to the gate-off. Vdto is the sum of potential fluctuations for all data bus lines.

  The potential of the display data written to each pixel is corrected through the data bus line by the amount of the common electrode potential variation ΔVcom thus obtained. Thereby, crosstalk can be reduced.

  FIG. 5 is a flowchart showing a process for reducing lateral crosstalk. With reference to FIG. 5, processing for reducing lateral crosstalk will be described using a specific example.

  In step S1, the power of the liquid crystal display device is turned on. In step S <b> 2, data indicating the correspondence between gradation and applied voltage and pulse parameters are read from the panel parameter storage RAM 23 to the timing controller 21.

  In step S3, the display data of the (N-1) th horizontal line is supplied from the outside to the timing controller 21 of the liquid crystal display device. FIG. 6 is a diagram illustrating an example of display data.

  In the example of the display data in FIG. 6, in the lines X <b> 1-1 and X <b> 1, a uniform halftone of gradation 128 is given over the entire horizontal line. Here, one horizontal line is composed of the first dot to the 3072th dot. In the line X1-1, odd dots are negative and even dots are positive. In line X1, odd dots are positive and even dots are negative.

  In the lines X2-1 and X2, from the first dot to the 1536th dot, the odd dots are white (gradation ± 255) and the even dots are black (gradation ± 0). A uniform halftone of gradation 128 is given from the 1357th dot to the 3072st dot. In line X2-1, odd dots are negative and even dots are positive. In line X2, odd dots are positive and even dots are negative.

  Returning to FIG. 5, in step S4, pixel data of each color of RGB is converted from gradation values to voltage values for the display data of the (N-1) th horizontal line. This conversion is performed based on data indicating the correspondence between the gradation read from the panel parameter storage RAM 23 and the applied voltage. FIG. 7 is a diagram illustrating an example of data indicating correspondence between gradations and applied voltages.

  As shown in FIG. 7, voltage values corresponding to each gradation from 0 to 255 are stored at predetermined addresses in the panel parameter storage RAM 23. For example, at gradation 0, the applied voltage value to the pixel electrode is 0.8V, and at gradation 255, the applied voltage value to the pixel electrode is 5.5V. The panel parameter storage RAM 23 further stores, for example, a value of Cdc / Ctot (1-exp (−ton / (RCtot)) as a panel parameter.

  Returning to FIG. 5, the sum of the voltage values of each pixel is calculated in step S5. For example, when the current horizontal line N-1 is X1-1 in FIG. 6, the voltage + 2.5V corresponding to the gradation +128 is added by 1356 dots, and the voltage corresponding to the gradation -128 is -2. 5V is added by 1356 dots. The sum in this case is zero.

  In step S6, display data of the Nth horizontal line is input from the outside to the timing controller 21 of the liquid crystal display device. In step S 7, the display data of the Nth horizontal line is stored from the timing controller 21 into the display data storage RAM 22. In step S8, pixel data of each color of RGB is converted from gradation values to voltage values for the display data of the Nth horizontal line. In step S9, the sum of the voltage values of each pixel is calculated. For example, when the current horizontal line N is X1 in FIG. 6, the voltage + 2.5V corresponding to the gradation +128 is added by 1356 dots, and the voltage −2.5V corresponding to the gradation −128 is further 1356 dots. It is added together. The sum in this case is zero.

  In step S10, a change in the sum of voltages from the previous horizontal line (N-1st horizontal line) to the current horizontal line (Nth horizontal line) is calculated. For example, when the current horizontal line N is X1 in FIG. 6, the sum of the voltages of the previous horizontal line is zero, and the sum of the voltages of the current horizontal line is zero. Therefore, in this case, the change in the total voltage is zero.

  On the other hand, for example, when the current horizontal line N is X2 in FIG. 6, the change in the sum of the voltages does not become zero. That is, the sum of the voltages in the immediately preceding horizontal line X2-1 is obtained by adding 768 dots to the voltage -5.5V corresponding to the gradation -255 from the first dot to the 1536th dot, and further to the gradation +0. Corresponding voltage + 0.8V is added by 768 dots. The positive and negative values are canceled out from the other 1537 dots to 3072 dots. Therefore, the sum of the voltages is (0.8−5.5) × 768. Further, the sum of the voltages on the current horizontal line X2 is obtained by adding 768 dots to the voltage + 5.5V corresponding to the gradation +255 from the first dot to the 1536th dot, and further adding the voltage −0. 8V is added by 768 dots. The positive and negative values are canceled out from the other 1537 dots to 3072 dots. Therefore, the sum of the voltages is (5.5-0.8) × 768. In this case, the change amount Vdto of the sum of the voltages is 2 × (5.5-0.8) × 768.

In step S11, the potential fluctuation of the common electrode is calculated based on the panel parameter. For example, if the connection resistance R between the power source and the common electrode is 20Ω, the common electrode total capacitance Ctot is 3000 nF, the drain-common coupling capacitance Cdc is 100 pF, and the time ton from the switching of the data voltage to the gate off is 17 μs. /Ctot(1−exp(−ton/(RCtot))=8.22×10 ⁻⁶ Therefore, when the current horizontal line N is X2 in FIG. × (5.5-0.8) × 768 × 8.22 × 10 ⁻⁶ ≈0.06V.

  In step S12, the display data of the Nth horizontal line stored in the display data storage RAM 22 is corrected with a value obtained by converting the potential fluctuation Vcom into a gradation value, and is output to the data driver. This process is executed during the horizontal blanking period and the display data input period of the (N + 1) th horizontal line. In the above example, when the current horizontal line N is X2 in FIG. 6, the potential fluctuation ΔVcom of the common electrode is 0.06V, and thus, for example, negative gradation −128 (−2.50V) is −2. .44V gradation 125 (see FIG. 7) is corrected, positive polarity gradation +128 (+ 2.50V) is corrected to + 2.56V gradation 131 (see FIG. 7).

  As described above, the display data supplied from the timing controller 21 to the data driver is corrected by the amount of the common electrode potential fluctuation ΔVcom. As a result, the potential of the display data written to each pixel from the data driver via the data bus line can be corrected to reduce crosstalk.

  In the description of the above embodiment, the common electrode potential fluctuation is calculated based on the difference between the display data of the target horizontal line and the display data of the previous horizontal line in the target frame. Instead of calculating in this way, the common electrode potential fluctuation in the target horizontal line in the target frame may be estimated based on the display data of the corresponding horizontal line in the frame immediately before the target frame. For example, the display data of the frame of interest may be estimated to be the same as the display data in the previous frame. In this case, for example, when there is no movement in the display data, the estimation is completely correct. As described above, when estimation is performed based on the display data of the previous frame, a memory for storing the display data of the target horizontal line of the target frame is not necessary.

  FIG. 8 is a configuration diagram showing the configuration shown in FIG. 3 in more detail for the horizontal crosstalk reduction processing. The display data storage RAM 22 is a RAM that stores display data for one horizontal line, and the panel parameter storage RAM 23 is a ROM that stores panel parameters and data indicating the relationship between gradation and voltage.

  The circuit 41 for sending display data for one horizontal line to the RAM stores the current one line of the display data signal supplied from the outside in the display data storage RAM 22. The circuit 42 for converting RGB bit data into voltage values converts a display data signal supplied from the outside into voltage values based on data indicating the relationship between gradation and voltage stored in the panel parameter storage RAM 23.

  The circuit 43 that adds the voltage values of each pixel for one line obtains the sum of the potentials of the data bus lines for one horizontal line by adding the voltage values converted from data by the circuit 42 for one horizontal line. The circuit 44 that holds the voltage value deviation of one line total is a storage circuit that holds the sum of the potentials of the data bus lines for one horizontal line obtained by the circuit 43. The circuit 45 that calculates the difference in voltage value deviation between the previous line and the corresponding line calculates the previous potential stored in the circuit 44 from the total potential of the current horizontal line (target line) obtained by the circuit 43. By subtracting the total potential of the horizontal lines, the change in the total potential is calculated.

  The circuit 46 for converting the bias difference into the common voltage shift according to the panel parameter refers to the panel parameter stored in the panel parameter storage RAM 23, and converts the change in the total potential obtained by the circuit 45 into the common electrode potential change ΔVcom. Convert. The circuit 47 for correcting the display data by converting the voltage fluctuation into gradation converts the common electrode potential change ΔVcom obtained by the circuit 46 into gradation change, and stores the gradation change only in the display data storage RAM 22. The display data is corrected by shifting the display data.

  The corrected display data is supplied to the bus driver. In FIG. 8, for example, the circuits 42 to 46 correspond to the crosstalk potential fluctuation calculation circuit 31, and the circuit 47 corresponds to the data correction circuit 32.

  Hereinafter, a case of reducing vertical crosstalk will be described as a second embodiment of the crosstalk reduction processing according to the present invention.

  FIG. 9 is a flowchart showing processing for reducing vertical crosstalk. With reference to FIG. 9, processing for reducing vertical crosstalk will be described.

  In step S1, the power of the liquid crystal display device is turned on. In step S <b> 2, data indicating the correspondence between gradation and applied voltage and pulse parameters are read from the panel parameter storage RAM 23 to the timing controller 21.

  In step S3, display data of the pixel (x, y) in the Mth frame is supplied from the outside to the timing controller 21 of the liquid crystal display device. That is, the data (x = 1, 2,...) Of each pixel in the yth horizontal line of the Mth frame are sequentially supplied.

  In step S4, the data of the yth horizontal line of the (M−1) th frame is read from the display data storage RAM 22 and the gradation value of the data is converted into a voltage value. This conversion is performed based on data indicating the correspondence between the gradation read from the panel parameter storage RAM 23 and the applied voltage. The display data storage RAM 22 is a RAM for storing display data having a capacity for one frame. In step S5, the display data of the yth horizontal line of the (M-1) th frame in the display data storage RAM 22 is rewritten as needed with the display data of the yth horizontal line of the Mth frame supplied from the outside in step S3.

  In step S6, the contents of the vertical line memory that stores the sum of the display data voltages for one frame for each vertical line are updated. In this embodiment, focusing on the fact that the cause of the vertical crosstalk is the potential fluctuation of the data bus line, the vertical line memory for storing the potential fluctuation for one frame is provided for each data bus line that sequentially supplies display data. Provide. In the update process in step S6, the data of the xth pixel in the yth horizontal line of the Mth frame is converted into a voltage value, and the obtained voltage value is added to the data of the xth vertical line in the vertical line memory. Further, the voltage value data of the xth pixel of the yth horizontal line of the M−1th frame is subtracted from the data of the xth vertical line of the vertical line memory. As a result, the data of the xth vertical line in the vertical line memory is updated.

  As a result of the update process, the data of the xth vertical line in the vertical line memory is the last from the y + 1th horizontal line of the M−1th frame when the pixel (x, y) of the Mth frame is the target pixel. The display data voltage value of the xth pixel of each horizontal line is added up to the horizontal line and from the first horizontal line to the yth horizontal line of the Mth frame. That is, the potential fluctuation of the xth data bus line from the time when the pixel (x, y) of the M-1th frame is written to the pixel electrode to the time when the pixel (x, y) of the Mth frame is written to the pixel electrode. Will be obtained.

  In step S7, the sum of the data bus lines located on both sides of the pixel of interest, for example, the xth data bus line and the x + 1th data bus line is obtained, and the sum is divided by the number of horizontal lines per frame, Find the average potential around one horizontal line. Further, the difference between the average potential and the pixel (x, y) in the M−1th frame is obtained, and the potential fluctuation of the pixel electrode is calculated by multiplying the difference by the panel parameter. The panel parameter used in this case is a parasitic capacitance between the data bus line and the pixel electrode.

  In step S8, display data of the pixel (x, y + 1) in the Mth frame is supplied from the outside to the timing controller 21 of the liquid crystal display device. That is, the data (x = 1, 2,...) Of each pixel on the y + 1th horizontal line of the Mth frame is sequentially supplied. In parallel with the display data input, the following steps S9 and S10 are executed.

  In step S9, based on the data indicating the relationship between gradation and voltage stored in the panel parameter storage RAM 23, the potential fluctuation of the pixel electrode obtained in step S7 is converted into gradation. In step S10, the display data of the pixel (x, y) in the (M−1) th frame read from the display data storage RAM 22 is corrected with the gradation value corresponding to the pixel electrode potential fluctuation obtained in step S9. The corrected display data is supplied to the data driver. This process is executed during a period in which display data of the pixel (x, y + 1) in the Mth frame (that is, each pixel data in the y + 1th horizontal line in the Mth frame) is input.

  As described above, the display data supplied from the timing controller 21 to the data driver is corrected by the amount of potential fluctuation of the pixel electrode. As a result, the potential of the display data written to each pixel from the data driver via the data bus line can be corrected to reduce crosstalk.

  FIG. 10 is a configuration diagram showing the configuration shown in FIG. 3 in more detail for the vertical crosstalk reduction processing. The display data storage RAM 22 is a RAM for storing display data for one frame, and the panel parameter storage RAM 23 is a ROM for storing data indicating the relationship between panel parameters and gradation and voltage. The above-described vertical line memory is a RAM 24 that stores the display data of each vertical line after converting it into a voltage value and adding it.

  The circuit 51 for sending display data for one frame to the RAM writes the display data for one frame in the display data storage RAM 22 when the display data is supplied from the outside to the timing controller 21 of the liquid crystal display device. The circuit 52 for converting the y-line data of the (M-1) th frame into a read voltage value reads the display data of the yth horizontal line of the (M-1) th frame from the display data storage RAM 22 and reads it from the panel parameter storage RAM 23. Based on the data indicating the correspondence between the gradation and the applied voltage, the gradation value of the display data is converted into a voltage value.

  The circuit 53 that converts the data of the M frame y line into a voltage value converts the gradation of the display data into a voltage value for each pixel of the y th horizontal line of the M frame. A circuit 54 that reads the value obtained by adding the voltage values for one frame of each x line from the RAM, adds the data of the M frame y line, subtracts the data of (m−1) frames, and writes the new value to the RAM. The obtained voltage value of the xth pixel is added to the data of the xth vertical line of the vertical line memory 24, and the voltage value data of the xth pixel of the yth horizontal line of the M−1th frame is further obtained. The data of the x-th vertical line in the vertical line memory 24 is subtracted to update the data in the vertical line memory 24.

  The circuit 55 for multiplying the voltage value obtained by adding one frame of the x and x + 1 lines by the panel parameter and calculating the voltage variation of the frame pixel (x, y) is 1 for the data bus line that affects the pixel of interest. The average potential is obtained by dividing the sum of the potential fluctuations for the frame by the number of horizontal lines per frame, and the difference between this average potential and the pixel (x, y) of the M-1st frame is obtained. The potential fluctuation of the pixel electrode is calculated by multiplying the parameter. (M-1) The circuit 56 for correcting the display data of the frame (x, y) pixel is a pixel obtained by the circuit 55 based on the data indicating the relationship between the gradation and the voltage stored in the panel parameter storage RAM 23. The potential fluctuation of the electrode is converted into a gradation, and the display data of the pixel (x, y) in the (M−1) th frame is corrected with the gradation value after this conversion.

  The corrected display data is supplied to the bus driver. In FIG. 10, for example, circuits 52 to 55 correspond to the crosstalk potential fluctuation calculation circuit 31, and circuit 56 corresponds to the data correction circuit 32.

  In the description of the above embodiment, the pixel electrode potential fluctuation is calculated based on the fluctuation of display data for one frame after writing the display data for the target pixel. Instead of calculating in this way, the pixel electrode potential variation for the pixel of interest may be estimated based on the variation in display data for one frame after writing the display data for the corresponding pixel one frame before. For example, the change in display data for one frame after writing the display data for the pixel of interest may be estimated to be the same as the change in display data for one frame after writing the display data for the corresponding pixel one frame before. In this case, for example, when there is no movement in the display data, the estimation is completely correct.

  In the description of the above embodiment, the pixel of interest is configured to add up all the display data fluctuations for one frame after writing the display data. However, the pixel of interest is configured to add up only for a display data voltage above a certain threshold. Also good.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
A liquid crystal panel including a plurality of pixels functioning to hold a data potential and displaying an image according to the data potential;
A potential variation calculation circuit that receives display data of the plurality of pixels and calculates a potential change that the display data of at least one other pixel gives to a data potential of one of the plurality of pixels through capacitive coupling. When,
A data correction circuit for correcting the display data of the one pixel in accordance with the potential change calculated by the potential fluctuation calculation circuit;
A liquid crystal display device comprising: a data driver that supplies a data potential corresponding to the corrected display data to the liquid crystal panel.
(Appendix 2)
The liquid crystal panel
One common electrode,
The liquid crystal display device according to appendix 1, wherein the liquid crystal display device includes a plurality of pixel electrodes respectively corresponding to the plurality of pixels, and the potential fluctuation calculation circuit calculates a potential fluctuation of the common electrode as the potential change.
(Appendix 3)
The liquid crystal panel further includes a plurality of data bus lines for supplying a data potential to the plurality of pixels, and the potential fluctuation calculation circuit is configured to detect the potential of the data bus line at the time of transition from one horizontal line to the next horizontal line. 3. The liquid crystal display device according to appendix 2, wherein the change is summed for all data bus lines, and the potential fluctuation of the common electrode is calculated based on the sum.
(Appendix 4)
The memory according to claim 3, further comprising a memory for storing a parameter indicating characteristics of the liquid crystal panel, wherein the potential fluctuation calculation circuit calculates the potential fluctuation of the common electrode according to the sum and the parameter. Liquid crystal display device.
(Appendix 5)
The additional potential calculation circuit according to claim 2, wherein the potential fluctuation calculation circuit estimates the potential fluctuation of the common electrode based on the total obtained for the corresponding pixel of the previous frame preceding the frame of the one pixel. Liquid crystal display device.
(Appendix 6)
The liquid crystal panel
One common electrode,
The liquid crystal display according to claim 1, further comprising a plurality of pixel electrodes respectively corresponding to the plurality of pixels, wherein the potential fluctuation calculation circuit calculates a potential fluctuation of the pixel electrode of the one pixel as the potential change. apparatus.
(Appendix 7)
The liquid crystal panel further includes a plurality of data bus lines for supplying data potentials to the plurality of pixels, and the potential fluctuation calculating circuit is configured to write a data potential to the one pixel in a frame and then to the next frame. The sum of the potential fluctuations of the data bus line adjacent to the one pixel until the writing of the data potential to the one pixel in the pixel is obtained, and the potential fluctuation of the pixel electrode of the one pixel is calculated based on the sum The liquid crystal display device according to appendix 6, wherein:
(Appendix 8)
A memory for storing a parameter indicating characteristics of the liquid crystal panel, wherein the potential fluctuation calculation circuit calculates the potential fluctuation of the pixel electrode of the one pixel according to the sum and the parameter; The liquid crystal display device according to appendix 7.
(Appendix 9)
The potential fluctuation calculation circuit is configured to write data potential to the one pixel in the frame of the one pixel after writing the data potential to the corresponding pixel of the previous frame preceding the frame of the one pixel. The supplementary note 7, wherein a total sum of potential fluctuations of the data bus line adjacent to the one pixel is obtained, and the potential fluctuation of the pixel electrode of the one pixel is estimated based on the obtained sum. Liquid crystal display device.

It is a figure which shows the structure of the conventional liquid crystal display device. It is a figure which shows the crosstalk brightness | luminance change which generate | occur | produces in the up-and-down and right-and-left area | region when a specific pattern is displayed on a part of liquid crystal panel display area. It is a figure which shows the structure of the timing controller periphery in the liquid crystal display device by this invention. It is a figure for demonstrating the reduction process of a horizontal crosstalk. It is a flowchart which shows the process which reduces horizontal crosstalk. It is a figure which shows an example of display data. It is a figure which shows an example of the data which show a response | compatibility with a gradation and an applied voltage. It is the block diagram which showed the structure shown in FIG. 3 further in detail about the horizontal crosstalk reduction process. It is a flowchart which shows the process which reduces vertical crosstalk. It is the block diagram which showed the structure shown in FIG. 3 further in detail about the vertical crosstalk reduction process.

Explanation of symbols

10 LCD panel 11 Timing controller 12 Gate driver 13 Data driver 21 Timing controller 22 Display data storage RAM
23 Panel parameter storage RAM
31 Crosstalk potential fluctuation calculation circuit 32 Data correction circuit

Claims (2)

A liquid crystal panel including a plurality of pixels functioning to hold a data potential and displaying an image according to the data potential;
A potential variation calculation circuit that receives display data of the plurality of pixels and calculates a potential change that the display data of at least one other pixel gives to a data potential of one of the plurality of pixels through capacitive coupling. When,
A data correction circuit for correcting the display data of the one pixel in accordance with the potential change calculated by the potential fluctuation calculation circuit;
A data driver that supplies the liquid crystal panel with a data potential corresponding to the corrected display data;
One common electrode,
A plurality of pixel electrodes respectively corresponding to the plurality of pixels, and the potential fluctuation calculating circuit includes a pixel electrode of the one pixel generated via a capacitance between the pixel electrode and the data bus line of the one pixel. A liquid crystal display device characterized by calculating a potential variation as the potential variation.   The liquid crystal panel further includes a plurality of data bus lines for supplying data potentials to the plurality of pixels, and the potential fluctuation calculating circuit is configured to write a data potential to the one pixel in a frame and then to the next frame. The sum of the potential fluctuations of the data bus line adjacent to the one pixel until the writing of the data potential to the one pixel in the pixel is obtained, and the potential fluctuation of the pixel electrode of the one pixel is calculated based on the sum The liquid crystal display device according to claim 1.

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