JP4666963B2 - Driving method for aging display device - Google Patents

Description

The present invention relates to a display device in which pixels including a liquid crystal element or a light emitting element and a transistor are arranged in a matrix, and a driving method thereof.

In recent years, a display device having a liquid crystal element or a light emitting element has been actively developed. Liquid crystal display devices are rapidly spreading by taking advantage of space saving and low power consumption. In addition to the advantages of existing liquid crystal display devices, display devices with light-emitting elements have features such as fast response speed, excellent video display, and a wide viewing angle. Attention has been paid.

The display device includes a pixel portion in which a plurality of pixels each including a liquid crystal element or a light emitting element and a transistor are arranged in a matrix. It is preferable that all the transistors included in the pixel portion are formed of one conductivity type from the viewpoint of manufacturing cost and manufacturing process. Also, in the case where a driver circuit is formed over a substrate over which the pixel portion is manufactured, it is preferable that all the transistors included in the pixel portion and the driver circuit are configured with one conductivity type. In the case of a single-conductivity-type transistor, it is preferable to use a P-type transistor that has a much smaller hot carrier deterioration than an N-type transistor even with a simple single drain structure.

However, when a P-type transistor is used as a transistor arranged in a pixel, there is a problem that an image is not displayed accurately due to the high off-state current of the P-type transistor. Therefore, an object of the present invention is to provide a display device that suppresses display disturbance caused by an off-current of a P-type transistor arranged in a pixel and a driving method thereof.

In order to solve the above-described problems of the prior art, the following measures are taken in the present invention. The present invention actively utilizes the phenomenon that off-state current decreases when a certain stress condition is applied to a P-type transistor.

The display device of the first configuration of the present invention includes first and second P-type transistors connected in series, and a source electrode or a drain electrode of the second transistor is connected to a first power source, An aging circuit having a scanning line connected between the first and second P-type transistors is provided.
Further, a third P-type transistor in which a gate electrode is connected to the scanning line and one of a source electrode and a drain electrode is connected to a signal line, and a first electrode is the source electrode of the third P-type transistor And a pixel including a liquid crystal element connected to the other of the drain electrodes and having a second electrode connected to a second power source. An equivalent circuit diagram of the display device having the first configuration is as illustrated in FIG.

The display device of the second configuration of the present invention includes first and second P-type transistors connected in series, and a source electrode or a drain electrode of the second transistor is connected to a first power source, A first aging circuit in which a signal line is connected between the first and second P-type transistors, and third and fourth P-type transistors connected in series, And a second aging circuit in which a source electrode or a drain electrode is connected to a second power source, and a scanning line is connected between the third and fourth P-type transistors.
Further, a fifth P-type transistor in which a gate electrode is connected to the scanning line and one of a source electrode and a drain electrode is connected to the signal line, and a first electrode is the source of the fifth P-type transistor. And a pixel including a liquid crystal element connected to the other of the electrode and the drain electrode, and the second electrode connected to a third power source. An equivalent circuit diagram of the display device having the second configuration is as shown in FIG.

A display device having a third configuration according to the present invention includes first and second P-type transistors connected in series, and a source electrode or a drain electrode of the second transistor is connected to a first power supply, An aging circuit having a scanning line connected between the first and second P-type transistors is provided.
Further, a third P-type transistor having a gate electrode connected to the scanning line, a source electrode or a drain electrode connected to a signal line, and the first or second electrode are electrically connected to a second power source. And a pixel including a light emitting element. An equivalent circuit diagram of the display device having the third configuration is as illustrated in FIG.

A display device having a fourth configuration of the present invention includes first and second P-type transistors connected in series, and a source electrode or a drain electrode of the second transistor is connected to a first power source, A first aging circuit in which a first scanning line is connected between the first and second P-type transistors, and third and fourth P-type transistors connected in series. And a second aging circuit in which a source electrode or a drain electrode of the first transistor is connected to a second power source, and a second scanning line is connected between the third and fourth P-type transistors. It is characterized by.
Further, a fifth P-type transistor having a gate electrode connected to the first scan line, a source electrode or a drain electrode connected to the signal line, and a gate electrode connected to the second scan line, A sixth P-type transistor in which an electrode or a drain electrode is connected to a third power source, and a pixel including a light-emitting element in which the first or second electrode is electrically connected to the third power source. It is characterized by having. An equivalent circuit diagram of the display device having the fourth configuration is as shown in FIG.

As described above, the display device of the present invention includes an aging circuit. More specifically, the display device includes a pixel portion in which a plurality of pixels including a display element and a P-type transistor are arranged in a matrix, a signal line driver circuit, and a scan line driver circuit, and the signal line driver circuit and the scan line driver are provided. One or both of the circuits are provided with an aging circuit.
The transistors included in each pixel and the aging circuit are preferably transistors using a crystalline semiconductor (polysilicon, p-Si) as a channel portion. The reason is that a transistor using a crystalline semiconductor as a channel portion has good characteristics such as field effect mobility and is suitable for displaying moving images. Compared to a transistor using a crystalline semiconductor (amorphous silicon, a-Si) as a channel portion, the electron mobility is high and it is easy to obtain a current necessary for driving the light emitting element.

In the driving method of the display device having the first structure according to the invention, the first transistor is turned off, the second transistor is turned on, and the potentials of the first power supply and the scanning line are set to the same potential. It is characterized by that.
At this time, the potential difference between the potential of the first power supply and the drain voltage of the third transistor is | 24 | V or more.

According to a second method of driving a display device of the present invention, the first transistor is turned off, the second and fifth transistors are turned on, and the first power source, the signal line, and the liquid crystal are turned on. A first step of setting the potential of the first electrode included in the element to the same potential; turning off the first and third transistors; turning on the second and fourth transistors; The second power source and the signal line have the same potential, and the second power source and the scanning line have the same potential.
At this time, the potential difference between the potential of the first power supply in the first step and the potential of the second power supply in the second step is | 24 | V or more.

In the driving method of the display device having the third structure according to the present invention, the first transistor is turned off, the second transistor is turned on, and the potential of the first power supply and the scanning line is set to the same potential. It is characterized by that.
At this time, the potential difference between the potential of the first power supply and the drain voltage of the third transistor is | 24 | V or more.
According to a third aspect of the present invention, there is provided a display device driving method in which the second power source has the same potential as the other of the source electrode and the drain electrode of the third P-type transistor. And a second step of turning off the first transistor and turning on the second transistor so that the potential of the first power supply and the scanning line are the same. .
At this time, the potential difference between the potentials of the first and second power supplies is | 24 | V or more.

According to a fourth aspect of the present invention, there is provided a display device driving method, wherein the other of the source electrode and the drain electrode of the fifth transistor is set to the same potential as the third power source. The first and third transistors are turned off, the second and fourth transistors are turned on, and the potential of the first power supply and the first scanning line are set to the same potential. A second step of setting the potential of the power source and the second scanning line to the same potential is provided.
At this time, the potential difference between the potentials of the first and third power sources is | 24 | V or more, and the potential difference between the potentials of the second and third power sources is | 24 | V or more. It is characterized by being.

Further, the present invention is not limited to a configuration including an aging circuit like the display devices having the first to fourth configurations described above. A method for driving a display device that does not include an aging circuit will be described below.

The present invention includes a P-type transistor and a liquid crystal element, wherein a gate electrode of the P-type transistor is connected to a scanning line, one of a source electrode and a drain electrode is connected to a signal line, and the other is a first liquid crystal element. Alternatively, in the driving method of the display device connected to the second electrode, the first step of turning on the P-type transistor and setting the potential of the signal line and the potential of the drain electrode of the P-type transistor to the same potential; A second step of making the potential of the scanning line the same as the potential of the drain electrode of the P-type transistor is provided.
Note that in the first step, the potentials of the first and second electrodes included in the liquid crystal element are set to the same potential.
In the second step, the potential difference between the potential of the scanning line and the potential of the drain electrode of the P-type transistor is set to be greater than or equal to | 24 | V.

The present invention includes a P-type transistor and a light-emitting element, the gate electrode of the P-type transistor is connected to a scanning line, one of the source electrode and the drain electrode is connected to a signal line, and the other is a first light-emitting element included in the light-emitting element. Alternatively, in the driving method of the display device electrically connected to the second electrode, the P-type transistor is turned on, and the potential of the signal line and the potential of the drain electrode of the P-type transistor are set to the same potential. And a second step of setting the potential of the scanning line and the potential of the drain electrode of the P-type transistor to the same potential.
Note that in the second step, a potential difference between the potential of the scanning line and the potential of the drain electrode of the P-type transistor is set to be equal to or higher than | 24 | V.

The present invention having the above driving method can apply a stress condition for reducing off-state current to a transistor arranged in a pixel, more specifically, a transistor having a gate electrode connected to a scan line. The stress condition is preferably such that the gate voltage of the transistor is large on the positive side, the drain voltage is large on the negative side, and the gate-drain voltage is as large as possible.
More specifically, it is preferable to apply a gate-drain voltage about 1.5 times the voltage condition used for normal operation. For example, the gate-drain voltage is preferably | 24 | V or more. By providing such a stress condition to the transistor, it is possible to reduce the off-state current of the transistor, and as a result, it is possible to provide a method for driving a display device that suppresses display disturbance caused by the decrease in off-state current. it can.

Note that the display device in the present invention includes a light source such as an image display device, a light emitting device, and a lighting device. In addition, a panel in which a pixel portion and a drive circuit are enclosed between a substrate and a cover material, a module in which an FPC is attached to the panel, a module in which a driver IC is provided at the end of the FPC, a driver by a COG method or the like This category includes modules with ICs and displays used for monitors.

According to the present invention, it is possible to provide a display device that suppresses display disturbance caused by an off-state current of a P-type transistor and a driving method thereof.

(Embodiment 1)

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

The display device of the present invention includes an aging circuit. This embodiment includes a pixel portion in which a plurality of pixels including a liquid crystal element and a P-type transistor are arranged in a matrix, and a signal line driver circuit and a scan line driver circuit each including an aging circuit. The structure of the display device will be described with reference to FIG.

The aging circuit 31 included in the signal line driver circuit includes P-type transistors 11 and 12 (hereinafter referred to as transistors 11 and 12) connected in series, and the source electrode or the drain electrode of the transistor 12 is a power supply line. 21. S_OUT is supplied to the source electrode or the drain electrode of the transistor 11. S_OUT indicates a signal output from a circuit adjacent to the aging circuit 31, for example, a signal output from a latch. The aging circuit 31 sets the power supply line 21 and the signal line 18 to the same potential, and sets the drain voltage of the transistor 15 to an appropriate value.

The aging circuit 32 included in the scanning line driving circuit includes P-type transistors 13 and 14 (hereinafter referred to as transistors 13 and 14) connected in series, and the source electrode or drain electrode of the transistor 14 is a power supply line. 22 is connected. G_OUT is supplied to the source electrode or the drain electrode of the transistor 13. G_OUT indicates a signal output from a circuit adjacent to the aging circuit 32, for example, a signal output from a buffer. The aging circuit 32 sets the power supply line 22 and the scanning line 19 to the same potential, and sets the gate voltage of the transistor 15 to an appropriate value.

A plurality of pixels 101 arranged in the pixel portion are surrounded by signal lines 18 arranged in the column direction and scanning lines 19 arranged in the row direction. A liquid crystal material is interposed between the P-type transistor 15 and the pair of electrodes. A sandwiched liquid crystal element 16 and a capacitor element 17 that holds a potential difference between both electrodes of the liquid crystal element 16 are provided. The gate electrode of the P-type transistor 15 is connected to the scanning line 19, and one of the source electrode or the drain electrode is connected to the signal line 18. The first electrode (pixel electrode) 24 of the liquid crystal element 16 is connected to the other of the source electrode and the drain electrode of the P-type transistor 15, and the second electrode (counter electrode) 25 is connected to the power supply line 23.

The transistors 11 to 14 included in the aging circuits 31 and 32 and the transistor 15 disposed in the pixel 101 are all P-type. Therefore, the transistors 11 to 15 are preferably transistors using a crystalline semiconductor (polysilicon, p-Si) as a channel portion. A transistor using a crystalline semiconductor as a channel portion has favorable characteristics such as field-effect mobility and is suitable for displaying moving images. In addition, it is preferable that the pixel portion and the circuit formed integrally on the substrate on which the pixel portion is formed are all formed using P-type transistors, and this structure reduces manufacturing costs and simplifies the manufacturing process. Is realized.

Next, a method for driving the display device of the present invention including the aging circuits 31 and 32 will be described. Here, the description is divided into a period T1 for setting the drain voltage of the transistor 15 and a period T2 for setting the gate voltage of the transistor 15 and performing aging. Note that the voltage value conditions used in the following description are merely examples, and signals input to the gates of the transistors 11 to 14 are denoted as Vin1 to Vin4.

In the period T1, Vin1 is -12V, Vin2 is -17V, Vin3 is -17V, Vin4 is -22V, the power supply line 21 is -12V, the power supply line 22 is -17V, and the power supply line 23 is -12V. It is. Accordingly, the transistors 11 and 13 are turned off and the transistors 12 and 14 are turned on. In addition, the potential of the power supply line 21 is transmitted to the signal line 18 through the transistor 12, and the power supply line 21 and the signal line 18 become the same potential (−12V). Further, the potential of the power supply line 22 is transmitted to the scanning line 19 through the transistor 14, and the power supply line 22 and the scanning line 19 become the same potential (−17V). Then, the transistor 15 is turned on, and the potential of the power supply line 21 and the potential of one electrode 24 of the liquid crystal element 16 become the same potential (−12 V). At this time, since the potential of the other electrode 25 of the liquid crystal element 16 is −12 V, the potential difference between both electrodes of the liquid crystal element 16 becomes zero. Thus, it is preferable that there is no potential difference between both electrodes of the liquid crystal element 16 before aging. Further, the drain voltage of the transistor 15 is −12V, and the gate voltage is −17V.

In the period T2, Vin1 is 0V, Vin2 is -5V, Vin3 is 12V, Vin4 is 7V, the power supply line 21 is 0V, the power supply line 22 is 12V, and the power supply line 23 is -12V. Accordingly, the transistors 11 and 13 are turned off and the transistors 12 and 14 are turned on. Further, the potential of the power supply line 21 is transmitted to the signal line 18 through the transistor 12, and the power supply line 21 and the signal line 18 have the same potential (0 V). Further, the potential of the power supply line 22 is transmitted to the scanning line 19 through the transistor 14, and the power supply line 22 and the scanning line 19 become the same potential (12V). At this time, the drain voltage of the transistor 15 is −12 V, the gate voltage is 12 V, and the gate-drain voltage is | 24 | V. In this way, a desired stress condition can be applied to the transistor 15.

In the present invention having the above driving method, a stress condition for reducing off-state current can be applied to the transistor 15 disposed in the pixel 101. The stress condition is preferably such that the gate voltage of the transistor 15 is large on the positive side, the drain voltage is large on the negative side, and the gate-drain voltage is as large as possible.
More specifically, it is preferable to apply a gate-drain voltage about 1.5 times the voltage condition used for normal operation. For example, the gate-drain voltage is preferably | 24 | V or more. By providing such a stress condition to the transistor, it is possible to reduce the off-state current of the transistor, and as a result, it is possible to provide a method for driving a display device that suppresses display disturbance caused by the decrease in off-state current. it can.

Next, an embodiment mode of the present invention in which an aging circuit is provided only in a scan line driver circuit will be described with reference to FIG. 2A has a configuration in which the aging circuit 31 in the configuration shown in FIG. 1 is omitted, detailed description thereof will be omitted, and the operation will be described with a period T1 for setting the drain voltage of the transistor 15. The description will be divided into a period T2 in which the gate voltage of the transistor 15 is set and aging is performed. Note that the voltage value conditions used in the following description are merely examples.

In the period T1, Vin3 is −10V, Vin4 is 0V, the potential of the power supply line 22 is 0V, the potential of the power supply line 23 is 0V, and G_OUT is −5V. Accordingly, the transistor 13 is turned on, the transistor 14 is turned off, the transistor 15 is turned on, and the drain voltage of the signal line 18 and the transistor 15 becomes the same potential (here, 0 V). In this period, the potential of the pixel electrode 24 of the liquid crystal element 16 and the potential of the counter electrode 25 are preferably set to the same potential.

In the period T2, Vin3 is 24V, Vin4 is 19V, and the potential of the power supply line 22 is 24V. Accordingly, the transistor 13 is turned off and the transistor 14 is turned on. Then, the potential of the power supply line 22 is transmitted to the scanning line 19 via the transistor 14, and the power supply line 22 and the scanning line 19 become the same potential (24V). At this time, the drain voltage of the transistor 15 is 0V, the gate voltage is 24V, and the gate-drain voltage is 24V. In this way, a desired stress condition can be applied to the transistor 15.

1 and 2A, capacitive coupling may occur between the gate and the drain of the transistor 15 in some cases. Corresponding to the case where capacitive coupling occurs in this way, it is preferable that the power supply line 22 has a margin of about several volts (preferably 5 V). Specifically, it is preferable to provide a margin for the potential of the power supply line 22 so that the maximum VGD is about 24 + 5 = 29 V. In the case of the above voltage conditions, the potential of the power supply line 22 is set to 12 + 5 at the maximum. It is preferable to set to about 17V.

The timing for performing aging includes before starting the product, when starting the panel after product shipment, and when ending the panel. Further, it may be performed periodically after the product is shipped, or may be arbitrarily performed by the user when a problem occurs in the panel display. When it is performed after product shipment, aging can be performed at a timing not used by the user or at an arbitrary timing even after the panel is passed to the end user, so that the product life can be extended.
(Embodiment 2)

In this embodiment mode, a structure of a display device of the present invention will be described by using a light emitting element as a display element as an example. More specifically, the structure of the aging circuit will be described with reference to FIG.

The aging circuit 61 included in the scanning line driving circuit includes P-type transistors 41 and 42 (hereinafter referred to as transistors 41 and 42) connected in series, and the source electrode or the drain electrode of the transistor 42 is a power supply line. 51. G_OUT is supplied to the source electrode or drain electrode of the transistor 41. G_OUT indicates a signal output from a circuit adjacent to the aging circuit 61, for example, a signal output from a buffer. The aging circuit 61 sets the power supply line 51 and the scanning line 56 to the same potential, and sets the gate voltage of the transistor 43 to an appropriate value.

A plurality of pixels 101 arranged in the pixel portion are surrounded by power supply lines 52 and signal lines 55 arranged in the column direction, and scanning lines 56 arranged in the row direction. Transistors 43 and 64), a light-emitting element 47 in which a light-emitting material is sandwiched between a pair of electrodes, and a capacitor 63 that holds the gate-source voltage of the transistor 64.
The gate electrode of the transistor 43 is connected to the scanning line 56, and one of the source electrode and the drain electrode is connected to the signal line 55. The first electrode (pixel electrode) 48 of the light emitting element 47 is connected to the other of the source electrode and the drain electrode of the transistor 64, and the second electrode (counter electrode) 49 is connected to the power supply line 53. One of the first and second electrodes 48 and 49 of the light-emitting element 47 is an anode and the other is a cathode according to the direction of the current flowing between the two electrodes.

Note that the transistors 41 and 42 included in the aging circuit 61 and the transistor 43 disposed in the pixel 101 are all P-type. Therefore, the transistors 41 to 43 are preferably transistors using a crystalline semiconductor as a channel portion. The reason is that a transistor using a crystalline semiconductor as a channel portion has higher electron mobility than a transistor using an amorphous semiconductor (amorphous silicon, a-Si) as a channel portion, and is necessary for driving a light emitting element. It is easy to obtain a large current. In addition, it is preferable that the pixel portion and the circuit formed integrally on the substrate on which the pixel portion is formed are all formed using P-type transistors, and this structure reduces manufacturing costs and simplifies the manufacturing process. Is realized.

The transistor 43 (switching transistor 43) controls input of a video signal to the pixel 101. The transistor 64 (driving transistor 64) supplies a drain current corresponding to the gate-source voltage to the light emitting element 47.

Next, a method for driving the display device of the present invention having the aging circuit 61 will be described. Here, the description is divided into a period T1 for setting the drain voltage of the transistor 43 and a period T2 for setting the gate voltage of the transistor 43 and performing aging. Note that the voltage value conditions used in the following description are merely examples, and signals input to the gates of the transistors 41 and 42 are expressed as Vin1 and Vin2.

In the period T1, Vin1 is −10V, Vin2 is 0V, the potential of the power supply line 51 is 0V, the potential of the power supply line 52 is 8V, and G_OUT is −5V. Accordingly, the transistor 41 is turned on, the transistor 42 is turned off, the transistor 43 is turned on, and the drain voltage of the signal line 55 and the transistor 43 becomes the same potential (here, 8 V). In this period, it is preferable that the gate-source voltage of the transistor 64 be zero.

In the period T2, Vin1 is 32V, Vin2 is 27V, the potential of the power supply line 51 is 32V, and the potential of the power supply line 52 is 8V. Accordingly, the transistor 41 is turned off and the transistor 42 is turned on. Then, the potential of the power supply line 51 is transmitted to the scanning line 56 through the transistor 42, and the power supply line 51 and the scanning line 56 become the same potential (32V). Then, the drain voltage of the transistor 43 is 8V, the gate voltage is 32V, and the gate-drain voltage is 24V. Therefore, a desired stress condition can be applied.

In the present invention having the above driving method, a stress condition for reducing off-state current can be applied to the transistor 43 provided in the pixel 101. The stress condition is preferably such that the gate voltage of the transistor 43 is large on the positive side, the drain voltage is large on the negative side, and the gate-drain voltage is as large as possible.
More specifically, it is preferable to apply a gate-drain voltage about 1.5 times the voltage condition used for normal operation. For example, the gate-drain voltage is preferably | 24 | V or more. By providing such a stress condition to the transistor, it is possible to reduce the off-state current of the transistor, and as a result, it is possible to provide a method for driving a display device that suppresses display disturbance caused by the decrease in off-state current. it can.

Next, a configuration in which the transistor 76 is added to the pixel 101 illustrated in FIG. 2A and the aging circuit 92 is newly disposed in accordance with the transistor 76 will be briefly described with reference to FIG.

The aging circuit 91 provided in the scanning line driving circuit has P-type transistors 71 and 72 (hereinafter referred to as transistors 71 and 72) connected in series, one end connected to the power line 81 and the other end. Is supplied with G_OUT1. The aging circuit 91 sets the potential of the power supply line 81 and the scanning line 86 to the same potential, and sets the gate voltage value of the transistor 75 to an appropriate value. The aging circuit 92 includes P-type transistors 73 and 74 (hereinafter referred to as transistors 73 and 74) connected in series, one end is connected to the power supply line 82, and the other end is supplied with G_OUT2. The aging circuit 92 sets the power supply line 82 and the scanning line 87 to the same potential, and sets the gate voltage value of the transistor 76 to an appropriate value.

A plurality of pixels 101 arranged in the pixel portion are surrounded by power supply lines 83 and signal lines 85 arranged in the column direction, and scanning lines 86 and 87 arranged in the row direction, and P-type transistors 75, 76, 94 (hereinafter referred to as transistors 75, 76, 94), a light emitting element 77, and a capacitor 93.

When the transistor 76 (erasing transistor 76) is turned on, the charge held in the capacitor 93 is discharged and the transistor 94 is turned off. Accordingly, it is possible to create a state in which no current flows through the light emitting element 77 forcibly. With the arrangement of the transistors 76, the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels, so that the duty ratio can be improved.

The transistors 71 to 74 included in the aging circuits 91 and 92 and the transistor 75 disposed in the pixel 101 are all P-type. Therefore, the transistors 71 to 75 are preferably transistors using a crystalline semiconductor as a channel portion. The reason is that a transistor using a crystalline semiconductor as a channel portion has higher electron mobility than a transistor using an amorphous semiconductor as a channel portion, and it is easy to obtain a current necessary for driving a light-emitting element. There are some. In addition, it is preferable that the pixel portion and the circuit formed integrally on the substrate on which the pixel portion is formed are all formed using P-type transistors, and this structure reduces manufacturing costs and simplifies the manufacturing process. Is realized.

Subsequently, in the driving method of the display device of the present invention including the aging circuits 91 and 92, aging is performed by setting the drain voltage of the transistors 75 and 76 and the gate voltage of the transistors 75 and 76. The description will be divided into the period T2. Note that the voltage value condition used in the following description is merely an example, and signals input to the gates of the transistors 71 to 74 are denoted as Vin1 to Vin4.

The period T1 is a period in which the drain voltages of the transistors 75 and 76 are set. Vin1 and Vin3 are -10V, Vin2 and Vin4 are 0V, the power supply lines 81 and 82 are 0V, the power supply line 83 is 8V, and G_OUT1. , G_OUT2 is −5V. Accordingly, the transistors 71, 73, 75, and 76 are turned on, the transistors 72 and 74 are turned off, and the drain voltage of the signal line 85 and the transistor 75 becomes the same potential (here, 8V). In this period, it is preferable that the gate-source voltage of the transistor 94 be zero.

The period T2 is a period in which aging is performed by setting the gate voltages of the transistors 75 and 76, Vin1 and Vin3 are 32V, Vin2 and Vin4 are 27V, the potentials of the power supply lines 81 and 82 are 32V, and the potential of the power supply line 83 is 8V. Accordingly, the transistors 71 and 73 are turned off and the transistors 72 and 74 are turned on. Then, the potential of the power supply line 81 is transmitted to the scanning line 86 through the transistor 72, and the power supply line 81 and the scanning line 86 become the same potential (32V). Similarly, the power supply line 82 and the scanning line 87 are at the same potential (32V). Then, the drain voltage of the transistor 76 is 8V, the gate voltage is 32V, and the gate-drain voltage is 24V. Therefore, a desired stress condition can be applied.

In the present invention having the above driving method, a stress condition for reducing off-state current can be applied to the transistors 75 and 76 arranged in the pixel 101. The stress condition is preferably such that the gate voltages of the transistors 75 and 76 are large on the positive side, the drain voltage is large on the negative side, and the gate-drain voltage is as large as possible.
More specifically, it is preferable to apply a gate-drain voltage about 1.5 times the voltage condition used for normal operation. For example, the gate-drain voltage is preferably | 24 | V or more. By providing such a stress condition to the transistor, it is possible to reduce the off-state current of the transistor, and as a result, it is possible to provide a method for driving a display device that suppresses display disturbance caused by the decrease in off-state current. it can.

2B and FIG. 3, capacitive coupling may occur between the gates and drains of the transistors 43, 75, and 76 in some cases. Corresponding to the case where capacitive coupling occurs in this way, it is preferable that the power supply lines 51, 81, 82 have a margin of about several volts (preferably 5V). Specifically, it is preferable to provide a margin for the potentials of the power supply lines 51, 81, and 82 so that the VGD is about 24 + 5 = 29V at the maximum.

Note that the structure of the pixel including a light-emitting element is not limited to that illustrated in FIGS. 2B and 3, and may have any structure.

The timing for performing aging includes before starting the product, when starting the panel after product shipment, and when ending the panel. Further, it may be performed periodically after the product is shipped, or may be arbitrarily performed by the user when a problem occurs in the panel display. When it is performed after product shipment, aging can be performed at a timing not used by the user or at an arbitrary timing even after the panel is passed to the end user, so that the product life can be extended.
(Embodiment 3)

In the first and second embodiments, the configuration including the aging circuit has been described. However, the present invention is not necessarily limited to this, and the aging circuit may not be provided. Thus, a method for driving a display device that does not include an aging circuit in FIGS. 1 and 2 described in Embodiment Mode 1 is briefly described.

First, as a first step, in order to set the drain voltage of the transistor 15, the transistor 15 is turned on and a desired signal is input from the signal line 18.
Next, as a second step, the gate-drain voltage of the transistor 15 is preferably about | 24 | V or more so that it is about 1.5 times the voltage condition used for normal operation. The gate voltage of the transistor 15 is set. That is, the potential of the scanning line 19 is changed. Then, aging can be performed.
Therefore, if the potential of the scanning line 19 can be changed, the aging circuit may not be provided. This also applies to the configurations shown in FIGS. 2B and 3, and description of the operation is omitted here.

In this embodiment, experimental results obtained by examining the time change of off-state current (Ioff) when stress is applied to the gate voltage (VG) and drain voltage (VD) of a transistor will be described with reference to FIGS.

FIG. 4A shows the relationship between the off-state current and time (sec) when VG of the P-type transistor is fixed at 2V and VD is changed to −14, −16, −18, −20V. It is a graph. In the graph, the line connecting the markers with circles (◯) is VD of -14V, the line connecting the markers with square marks (□) is VD of -16V, and the line connecting the markers with diamonds (◇) is VD. The line connecting the markers of −18V and the triangle mark (Δ) is the result obtained under the condition that VD is −20V. The vertical axis shows a logarithmic scale. E + 00 is 1, 1,. E + 01 is 10,1. E + 02 is 100; E + 03 is 1000; E + 04 corresponds to 10,000, and the same applies to the subsequent graphs.
From this graph, it can be seen that the off-state current decreases with time under any condition. It can also be seen that the off-current is the lowest under the condition of VD of −20V. Therefore, it can be seen that a condition in which VD is large on the negative side is effective for reducing the off-state current.

FIG. 4B is a graph showing the relationship between the off-state current and time when VD of the P-type transistor is fixed to −14V and VG is changed to 2, 4, 6, 8, 10V. In the graph, VG is 2V for the line connected with the circle (◯) marker, VG is 4V for the line connected with the square mark (□), and VG is 6V for the line connected with the diamond mark (◇). The line connecting the triangle (Δ) markers is the result of VG being 8V, and the line connecting the rice (*) markers is the result of VG being 10V.
From this graph, it can be seen that the off-state current decreases with time under any condition. Further, it can be seen that the off-state current is the lowest when VG is 10V. Therefore, it can be seen that a condition in which VG is large on the positive side is effective for reducing the off-state current.

FIG. 5A shows a case where the gate-drain voltage (VGD) of the P-type transistor is fixed to −20V, VD is changed from −26 to −1V, and VG is changed to −6 to 19V. It is the graph which showed the relation between off current and time. This experiment shows the stress voltage dependence when VGD is fixed. In the graph, the lines connecting the white square markers (□) are VD -1V, VG 19V, and white lines. The line connecting the diamond (◇) markers is VD -3V, VG 17V, and the line connecting the white triangles (△) is VD -4V, VG 16V, cross (×) The line connecting the markers of VD is -5V, VG is 15V, the line connecting the US (*) marker is VD of -6V, VG of 14V, and the line connecting the black rectangular marker is VD Is -8V, VG is 12V, the line connecting the black rectangular marker is VD is -10V, VG is 10V, the line connecting the white circle (o) is VD is -14V and VG is 6V, the line connecting the crossed markers is VD -18V, VG The line connecting the V and black square markers is VD -20V, VG 0V, and the black diamond (♦) line is connected to the VD is -22V and VG is -2V. The line connecting the markers marked with triangles () is the result obtained under the conditions where VD is −26V and VG is −6V.
From this graph, it can be seen that the off-state current decreases with time under any condition. It can also be seen that the off-current is the lowest under the conditions of VD of −26V and VG of −6V. Therefore, it can be seen that a condition in which VD is large on the negative side is effective for reducing the off-state current.

FIG. 5B is a graph showing the relationship between the off-state current and time when the drain voltage (VD) is changed from −14 to −24 V while VG of the P-type transistor is fixed to 2 V. This experiment shows VD dependence when VG is fixed. In the graph, the line connecting the circled (◯) markers is the line connecting VD is -14V and the crossing (×) markers. A line with a marker of VD -16V and diamond mark (◇) is a line with a marker of VD -18V and a triangle mark (△), a line with a marker of VD -20V and a rice mark (*) Is the result of VD being −22V, and the line connecting square markers is the result of VD being −24V.
From this graph, it can be seen that the off-state current decreases with time under any condition. Further, it can be seen that the off-current is the lowest when VD is −24V and VG is 2V. Therefore, it can be seen that a condition where VGD is as large as possible is effective in reducing the off-state current.
Furthermore, when the off-current that does not cause a problem in display is 10 pA and the stress application time is 1 second, it can be seen from FIG. 5B that the optimum stress application condition is that VGD is | 24 | V or more. .

Summarizing the above experimental results, the stress conditions applied to the transistors are as follows: VD is large on the negative side from the graphs of FIGS. 4A and 5A, and VG is large on the positive side from FIG. 4B. It can be seen that is effective. From FIG. 5B, it is more effective that the gate-drain voltage (VGD) of the transistor is as large as possible.
As a more specific condition, it is preferable to apply a gate-drain voltage that is about 1.5 times the voltage condition used for normal operation. This is based on the result of this experiment. In this experiment, the stress applied to the P-type TFT in the normal condition is such that VD is -14V, VG is 2V, and VGD is | 16V | This decrease is based on what was confirmed when VGD was set to | 24 | V (about 1.5 times).
The present invention makes it possible to reduce the off-state current of the transistor by giving such a stress condition to the transistor, and as a result, a display device driving method that suppresses display disturbance caused by the reduction of off-current. Can be provided.

In this embodiment, the structure of the display device will be described with reference to FIG.

In FIG. 6A, a pixel portion 102 in which a plurality of pixels 101 are arranged in a matrix is provided over a substrate 107. A signal line driver circuit 103 and a first scan line driver are provided around the pixel portion 102. A circuit 104 and a second scan line driver circuit 105 are included. In FIG. 6A, the signal line driver circuit 103 and the two scan line driver circuits 104 and 105 are provided; however, the present invention is not limited to this, and the number of driver circuits depends on the pixel structure. Any setting may be made accordingly. These drive circuits are supplied with signals from the outside via the FPC 106.

FIG. 6B illustrates the structure of the first scan line driver circuit 104 and the second scan line driver circuit 105, which include a shift register 114, a buffer 115, and an aging circuit. 116. FIG. 6C illustrates a structure of the signal line driver circuit 103. The signal line driver circuit 103 includes a shift register 111, a first latch circuit 112, a second latch circuit 113, and an aging circuit 117. Have. As described above, the aging circuits 116 and 117 are arranged around the pixel portion 102.

Note that the structures of the scan line driver circuit and the signal line driver circuit are not limited to the above description, and may include a sampling circuit, a level shifter, or the like, for example. Further, it is not necessary to provide an aging circuit in both the scanning line driving circuit and the signal line driving circuit, and they may be provided in only one of them.

Further, in addition to the driving circuit, a circuit such as a CPU or a controller may be integrally formed on the substrate 107. Then, the number of external circuits (IC) to be connected is reduced, and the weight and thickness can be further increased. In addition, since the aging circuit has a configuration including two transistors, and thus the number of elements to be configured is small, even if the aging circuit is incorporated in the drive circuit, the mounting area is not increased.

When aging is performed, it is necessary to change the potential of a predetermined power supply line. In many cases, this is performed by supplying a predetermined signal from the controller to the power supply circuit connected via the FPC 106.

This embodiment can be freely combined with the above embodiment modes and embodiments.

As an example of an electronic device manufactured by applying the present invention, a digital camera, a sound reproducing device such as a car audio, a personal computer, a game device, a portable information terminal (a mobile phone, a portable game machine, etc.), a consumer game machine An image reproducing apparatus provided with a recording medium such as Specific examples of these electronic devices are shown in FIGS.

FIG. 7A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. FIG. 7B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. FIG. 7C illustrates a personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like.

FIG. 7D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. FIG. 7E illustrates a portable image reproducing device provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, a recording medium reading portion 2405, operation keys 2406, a speaker portion 2407, and the like. Including. A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. FIG. 7F shows a goggle type display which includes a main body 2501, a display portion 2502, and an arm portion 2503.

FIG. 7G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . FIG. 7H illustrates a mobile phone among mobile terminals, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. Including.

In the above electronic apparatus, the present invention is applied to a structure of a display portion and a driving method of the display portion. The timing for performing aging includes before starting the product, when starting the panel after product shipment, and when ending the panel. Further, it may be performed periodically after the product is shipped, or may be arbitrarily performed by the user when a problem occurs in the panel display. When it is performed after product shipment, aging can be performed at a timing not used by the user or at an arbitrary timing even after the panel is passed to the end user, so that the product life can be extended. In addition, when an electronic device using the display device of the present invention is applied to a mobile terminal or the like and can be connected to the Internet, data of optimal stress conditions may be downloaded. This embodiment can be freely combined with the above embodiment modes and embodiments.

In this embodiment, first, the drain-gate voltage (Vdg) of the transistor when the off-current is measured, and the drain-gate voltage (Vdg) of the transistor that the off-current becomes 10 pA when applied for 1 second. The experimental results of investigating the relationship will be described with reference to FIG.
Note that the drain-gate voltage of the transistor when the off-state current is measured is in accordance with the voltage condition of normal operation, and this value is taken as the horizontal axis of the graph. In addition, the drain-gate voltage of a transistor whose off-current becomes 10 pA when applied for 1 second is a stress condition for the purpose of reducing the off-current, and this value is taken as the vertical axis of the graph. Note that 10 pA is an off-current value that does not cause trouble in normal operation.

In the graph, a black circle (●) marker is obtained by applying a metal element (for example, nickel) functioning as a catalyst on an amorphous semiconductor formed on a glass substrate, and then performing laser crystallization. A transistor using the formed crystalline semiconductor as a channel portion is used as a sample.
The black square marker is a sample of a transistor that has undergone the same manufacturing process as the round marker. However, the thickness of the gate insulating film differs between the two samples.
A black triangle mark (▲) marker is a sample of a transistor having a channel portion made of a crystalline semiconductor prepared by the same manufacturing method as the circle mark marker sample, except for the laser crystallization irradiation conditions. It is a thing.
The US Mark (*) marker is a sample of a transistor using a crystalline semiconductor channel portion formed by laser crystallization directly on an amorphous semiconductor without applying a metal element to the amorphous semiconductor. It is.
The black diamond mark (♦) marker is a sample of a transistor formed on a silicon substrate (SIMOX substrate).
All samples were P-channel type transistors having a channel length of 10 μm and a channel width of 8 μm.

When the approximate curves of the markers of all samples were drawn, the slope was 1.4777. That is, if a stress condition of 1.34 to 1.61 times, preferably 1.44 to 1.51 times, more preferably 1.48 times the normal drain-gate voltage condition is applied for 1 second, It can be seen that the off-current is 10 pA. It can also be seen that such a tendency does not depend on the crystallinity of the channel portion of the transistor or the thickness of the gate insulating film.

Next, the relationship between time (horizontal axis) and off-current value (vertical axis) will be described with reference to FIG.
There are three samples, sample A to sample C. In all samples, the stress condition for the purpose of reducing the off-current is that the drain voltage is -17V and the gate voltage is 3V, and applied for 1 second. It was. All the samples were single-drain P-channel transistors, and the channel length was 12 μm and the channel width was 4 μm.
Sample A is a transistor to which no voltage was applied after application of stress conditions. Sample B is a transistor to which a voltage condition of a source voltage of −5 V, a drain voltage of 5 V, and a gate voltage of −8 V is applied after applying the stress condition. Sample C is a transistor to which an AC voltage having a source voltage of −5 to + 5V, a drain voltage of 5V, and a gate voltage of 8V are applied.

According to the graph above, after applying a stress condition for the purpose of lowering the off-current, the off-current tends to increase, but it does not increase greatly, and the off-current value is such that it does not hinder the operation. is there. That is, it can be seen that the effect is not lost immediately after the stress condition is applied, and is maintained for a long time.

Next, the relationship between the stress condition application time (horizontal axis) and the off-current value (vertical axis) for the purpose of reducing the off-current will be described with reference to FIG.
There are four graphs of FIGS. 10A to 10D, and the horizontal axes of FIGS. 10A to 10D indicate the off-state current when the gate voltage of the transistor is 2V and the drain voltage is −14V. The value is shown. The stress conditions for the purpose of reducing the off-state current are as follows. In FIG. 10A, the drain voltage is −18V and the gate voltage is 2V. In FIG. 10B, the drain voltage is −20V and the gate voltage is FIG. 10C shows a drain voltage of −22V and a gate voltage of 2V. FIG. 10D shows a drain voltage of −24V and a gate voltage of 2V. is there.

In all the graphs shown in FIGS. 10A to 10D, the asterisk (*) marker is a sample of a transistor with L / W = 10/8, and the vertical rectangular marker is L / W A transistor with W = 3/8 is used as a sample, a triangle (Δ) marker is a sample with a transistor with L / W = 10/200, and a marker with a cross (×) is L / W = 10/4 transistor sample, square (□) marker is L / W = 400/8 transistor sample, horizontal rectangular marker is L / W = 12/4 transistor as a sample.

The off current value in FIG. 10 is a value per unit channel width of each transistor, and the off current value of any sample does not change the way of reducing the off current. That is, it can be seen that the method for reducing the off-state current of the transistor does not depend on the transistor size.

4A and 4B illustrate a display device and a driving method thereof according to the present invention. 4A and 4B illustrate a display device and a driving method thereof according to the present invention. 4A and 4B illustrate a display device and a driving method thereof according to the present invention. The graph which shows the experimental result which investigated the time change of the off-state current (Ioff) when stress is applied to the gate voltage (VG) and drain voltage (VD) of a transistor. The graph which shows the experimental result which investigated the time change of the off-state current (Ioff) when stress is applied to the gate voltage (VG) and drain voltage (VD) of a transistor. FIG. 6 illustrates a panel, a scan line driver circuit, and a signal line driver circuit. FIG. 11 illustrates an electronic device to which the present invention is applied. The experimental results of investigating the relationship between the drain-gate voltage (VDG) of the transistor when the off-current was measured and the drain-gate voltage (VDG) of the transistor that would have an off-current of 10 pA if applied for 1 second. Graph showing. The graph which shows the experimental result which investigated the relationship between time and an off-current value. The graph which shows the experimental result which investigated the relationship between the application time (horizontal axis) and the off-current value (vertical axis) of the stress condition aiming at the fall of off-current.

Explanation of symbols

11 to 15 transistor 16 liquid crystal element 17 capacitive element 18 signal line 19 scanning line 21 to 23 power supply lines 24 and 25 electrodes 31 and 32 aging circuits 41 to 43 transistor 47 light emitting elements 48 and 49 electrodes 51 to 53 power supply line 55 signal lines 56 Scanning line 61 Aging circuit 63 Capacitor element 64 Transistors 71 to 73, 75, 76 Transistor 77 Light emitting element 78, 79 Electrodes 81 to 83 Power supply line 85 Signal lines 86, 87 Scanning lines 91, 92 Aging circuit 93 Capacitor element 94 Transistor 101 pixel

Claims (2)

A gate electrode of the P-type transistor is connected to the scanning line, one of the source electrode or the drain electrode is connected to the signal line, and the other of the source electrode or the drain electrode is the liquid crystal element In the driving method during aging of the display device connected to the first electrode or the second electrode,
A first step of turning on the P-type transistor and setting the potential of the signal line and the other potential of the source or drain electrode to the same potential and a large potential on the negative side ;
The potential of the scanning lines, to the other of the potential of the source electrode or the drain electrode, and the other of the potential of the potential of the scanning line is not large potential to the positive side of the source electrode or the drain electrode is large in the negative side a have the potential, and have a second step of applying a stress condition in the P-type transistor by applying a potential difference to be 1.34 to 1.61 times the voltage conditions used for normal operation,
A driving method during aging of a display device , wherein when the stress condition is applied for 1 second, the off-state current of the P-type transistor becomes 10 pA or less . A gate electrode of the P-type transistor is connected to the scanning line, one of the source electrode or the drain electrode is connected to the signal line, and the other of the source electrode or the drain electrode is the light-emitting element In a driving method at the time of aging of a display device electrically connected to a first electrode or a second electrode including a driving transistor,
A first step of turning on the P-type transistor and setting the potential of the signal line and the other potential of the source or drain electrode to the same potential and a large potential on the negative side ;
The potential of the scanning lines, to the other of the potential of the source electrode or the drain electrode, and the other of the potential of the potential of the scanning line is not large potential to the positive side of the source electrode or the drain electrode is large in the negative side a have the potential, and have a second step of applying a stress condition in the P-type transistor by applying a potential difference to be 1.34 to 1.61 times the voltage conditions used for normal operation,
A driving method during aging of a display device , wherein when the stress condition is applied for 1 second, the off-state current of the P-type transistor becomes 10 pA or less .

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