JP4662387B1 - Image sensor control signal generator and method thereof - Google Patents

Abstract

A plurality of control signals for an image sensor are set by executing one command.
An image sensor control signal generating apparatus according to the present invention is configured to provide a plurality of control signals for a specific direction of the plurality of directions with respect to an image sensor controlled by a plurality of control signals for a plurality of directions. An instruction code for designating one or more groups including one or more of a plurality of control signals for the specific direction and a value of a control signal included in the group And an instruction code generating means for simultaneously generating a control signal of a value included in the group specified in the generated instruction code and specified in the instruction code.
[Selection] Figure 5

Description

  The present invention relates to an image sensor control signal generating apparatus and method for generating a control signal for controlling an image sensor.

For example, Patent Document 1 discloses a CCD charge transfer driving circuit that decodes channel selection information and determines an output state of a selected channel.
Further, for example, Patent Document 2 discloses a CCD charge transfer driving device in which timing signals are time-division multiplexed.
Further, for example, Patent Literature 3 discloses a solid-state imaging device that selects and changes a direct drive signal based on a combination of data signal values.
However, Patent Documents 1 to 3 do not disclose a configuration in which a plurality of control signals for the image sensor are set at a time.

JP 2002-64753 A JP 2003-8995 A JP 2005-110140 A

  The present invention has been made from the above-described background, and it is an object of the present invention to provide an image sensor control signal generating apparatus and method for setting a plurality of control signals for the image sensor by executing one command. And

  In order to achieve the above object, an image sensor control signal generator according to the present application provides a plurality of control signals for a plurality of directions with respect to an image sensor (2) controlled by a plurality of control signals for a plurality of directions. An image sensor control signal generator (3, 112) that generates (ternary signal, binary signal), and includes a group (G) including a plurality of control signals in any of the plurality of directions, Instruction code creating means (300, 302, 34) for creating an instruction code for designating the value of the included control signal, and a group (G, STG) designated in the created instruction code. Control signal generating means (5, 7, 42, 44, 84, 86) for simultaneously generating a control signal having a value specified in the code.

  Preferably, each of the imaging elements (2) is controlled by a control signal indicating a plurality of directions or any one of them, and the instruction code includes at least one of the control signal groups (G, STG). The group designation information to be designated (G and STG in FIGS. 10B and 11B and the toggle instruction in FIGS. 20 to 23) and each of the control signal groups (G and STG). Including the value information (L / M / H in FIG. 10B, FIG. 11B) specifying the value (L / M / H) of the included control signal, and the instruction code creating means (300, 302). , 34) is one piece of the group designation information (FIG. 10B; G) and the value information (the same L / M /) for designating the value of the control signal included in the group designated by the group designation information. H) is associated with Each of the plurality of group designation information (FIG. 11B; STG) and control signals included in each of the plurality of groups (G) designated by the group designation information (G, STG). Instruction code including the value information designating the value (L / M / H) of the corresponding data is generated, and the control signal generating means (5, 7, 42, 44, 84, 86) Simultaneously generates the control signals included in the group (G, STG) according to the generated instruction code.

  In addition, an image sensor control signal generation method according to the present invention provides a plurality of control signals (three-value signals, ternary signals, A group (G) including a plurality of control signals for any one of the plurality of directions, and a value of the control signal included in the group; An instruction code creation step (300, 302, 34) for creating an instruction code for designating the value of the value specified in the group (G, STG) designated in the created instruction code. The control signal generation step (5, 7, 42, 44, 84, 86) that simultaneously generates the control signal is executed.

  Preferably, each of the imaging elements (2) is controlled by a control signal indicating a plurality of directions or any one of them, and the instruction code includes at least one of the control signal groups (G, STG). The group designation information to be designated (G and STG in FIGS. 10B and 11B and the toggle instruction in FIGS. 20 to 23) and each of the control signal groups (G and STG). Including the value information (L / M / H in FIG. 10B, FIG. 11B) specifying the value (L / M / H) of the included control signal, and the instruction code creating step (300, 302) , 34) is one piece of the group designation information (FIG. 10B; G) and the value information (the same L / M /) for designating the value of the control signal included in the group designated by the group designation information. H) Included in each of the plurality of group designation information (FIG. 11B; STG) and the plurality of groups (G) designated by the group designation information (G, STG). An instruction code including the value information specifying the signal value (L / M / H) is created in association with each other, and the control signal generation step (5, 7, 42, 44, 84, 86) simultaneously generates the control signals included in the group (G, STG) according to the created instruction code.

  An image sensor control signal generation program according to the present invention is a computer program for generating a plurality of control signals (3 for a plurality of directions) with respect to an image sensor (2) controlled by a plurality of control signals for a plurality of directions. Group (G) including a plurality of control signals for any one of the plurality of directions and a control signal included in the group in the image sensor control signal generation device (3, 112) that generates a value signal and a binary signal) An instruction code creating step (300, 302, 34) for creating an instruction code for designating the value of the value, and a group (G, STG) designated in the created instruction code. A control signal generation step (5, 7, 42, 44, 84, 86) for simultaneously generating a control signal having a predetermined value. To be executed.

Preferably, each of the imaging elements (2) is controlled by a control signal indicating a plurality of directions or any one of them, and the instruction code includes at least one of the control signal groups (G, STG). The group designation information to be designated (G and STG in FIGS. 10B and 11B and the toggle instruction in FIGS. 20 to 23) and each of the control signal groups (G and STG). Including the value information (L / M / H in FIG. 10B, FIG. 11B) specifying the value (L / M / H) of the included control signal, and the instruction code creating step (300, 302) , 34) is one piece of the group designation information (FIG. 10B; G) and the value information (the same L / M /) for designating the value of the control signal included in the group designated by the group designation information. H) Included in each of the plurality of group designation information (FIG. 11B; STG) and the plurality of groups (G) designated by the group designation information (G, STG). The control signal generation step (5, 7, 42, 42) causes the computer to generate an instruction code including the value information specifying the signal value (L / M / H) in association with each other. 44, 84, 86) cause the computer to execute the simultaneous generation of the control signals included in the group (G, STG) according to the created instruction code.
In this part, the constituent parts of the present invention are given the reference numerals in the present specification and drawings. This is intended to clarify the correspondence between them, and is technical in the present invention. It is not intended to limit the scope.

  According to the present invention, setting of a plurality of control signals for the image sensor can be performed by executing one command.

It is a 1st figure which illustrates the timing of switching (toggle) of the image sensor control signal in this embodiment. It is a figure which illustrates the external appearance of the digital camera to which this invention is applied. It is a figure which illustrates the structure of the digital camera shown in FIG. It is a figure which illustrates the structure of the CCD image pick-up element shown in FIG. It is a figure which shows the structure of the control signal data generation part shown in FIG. It is a figure which illustrates the structure of the instruction code output with respect to an instruction code decoder from the microcontroller shown in FIG. FIG. 6 is a diagram showing a configuration of an STG (simultaneous toggle group) decoder shown in FIG. 5 and data stored in a register. It is a figure which shows the structure of the update logic shown in FIG. It is a figure which shows the structure of the ID comparison circuit shown in FIG. FIGS. 2A and 2B are diagrams illustrating generation of control signals by a method indicated by a in FIG. 1, in which FIG. 1A shows waveforms of control signals, and FIG. 1B shows the control shown in FIG. The command for obtaining a signal is illustrated. It is a figure which illustrates generation | occurrence | production of a control signal by the method concerning this invention, Comprising: (A) shows the waveform of each control signal, (B) shows the command for obtaining the control signal shown in (A). Illustrate. It is a figure which illustrates the structure of the 2nd digital camera to which this invention is applied. It is a figure which shows the structure of the control signal generation part shown in FIG. It is a figure which illustrates the toggle command which the command generation part shown in Drawing 13 generates. 14 is a first flowchart illustrating the operation (S72) of the transfer unit illustrated in FIG. FIG. 16 is a second flowchart illustrating the count signal generation process (S74) shown in FIG. It is a figure which illustrates the structure of the command execution part shown in FIG. It is a figure which shows the structure of the update logic shown in FIG. It is a figure which shows the structure of the STG decoder in the command execution part shown in FIG. An example of an instruction sequence including ID data ID1 to ID7 generated by the command generation unit and transfer unit illustrated in FIG. 13 and supplied to the command execution unit and level data LV1 to LV7 in association with each other is illustrated. FIG. FIG. 14 is a second diagram illustrating an instruction sequence generated by the command generation unit and the transfer unit illustrated in FIG. 13 and supplied to the command execution unit 8 and includes eight instructions including every other delimiter. FIG. 10 is a diagram illustrating an instruction sequence and a storage state of toggle instructions of registers (R1 <1> to R1 <3>, R2 <1>, R2 <2>, R3 <1>) at each value of a counter signal. . FIG. 14 is a third diagram illustrating an instruction sequence generated by the command generation unit and the transfer unit illustrated in FIG. 13 and supplied to the command execution unit 8, and includes 11 command sequences including a delimiter and each clock; FIG. 5 is a diagram illustrating toggle instructions of registers (R1 <1> to R1 <3>, R2 <1>, R2 <2>, R3 <1>) in FIG. FIG. 14 is a fourth diagram illustrating an instruction sequence generated by the command generation unit and the transfer unit illustrated in FIG. 13 and supplied to the command execution unit 8.

[Background to the Invention]
In order to help understanding of the embodiment of the present invention, first, the background of the present invention will be described.
As a method for controlling an image sensor such as a CCD imaging device or a CMOS imaging device and controlling the timing of a signal for reading out an image signal obtained as a result of imaging, the following method (1-1) is used. , (1-2) can be cited as an example.
(1-1) Method using a register (Register type):
Data (Data) indicating signal timing (Timing) for the image sensor is stored in advance in a register, read using a sequencer, and used for signal timing control for the image sensor.
(1-2) Method using CPU (CPU type):
Signal timing for the image sensor is controlled by software processing using a micro-controller to control the signal timing for the image sensor.

However, the method (1-1) is suitable for switching a large number of signals and supplying them to the image pickup device. Since hardware means for execution is required, the scale of hardware for realization becomes large.
On the other hand, the method (1-2) can be realized by hardware having a smaller scale than the method (1-1).
However, since the length of the instruction code that can be executed by the CPU is limited, a large number of signals cannot be switched by executing one instruction code.
In this method (1-2), since the number of executable instruction codes is limited by the control time interval for the image sensor, the number of switchable signals is smaller than in the above method (1). End up.
Therefore, a method for generating an image sensor control signal that has the advantages of both the methods (1-1) and (1-2) is desired.

A semiconductor chip used in an AFE integrated circuit (AFE IC; “AFE IC”) including an analog front end (AFE) that converts an analog output signal of a CCD imaging device into a digital signal is called an “AFE chip”. ) Can be roughly classified into the following types (2-1) and (2-2).
(2-1) 3-in-1 type:
(AFE integrated circuit of the type in which the V driver 112 and the control signal data generator 3 shown in FIG. 3 are configured on the same IC chip)
The 3-in-1 type AFE IC has a configuration in which an AFE, a vertical driver (V driver), and a timing generator (TG) are accommodated in one package, and the TG and the V driver are connected inside the IC.
(2-2) 2-in-1 type:
(AFE integrated circuit of the type in which the V driver 112 and the control signal data generator 3 shown in FIG. 3 are configured on different IC chips)
The AFE and the V driver are configured in one package, and the TG and the V driver are connected to each other outside the IC (on the printed board).

When the 3-in-1 type AFE IC is adopted, the TG and the V driver are connected to each other inside the IC. Therefore, when this type of AFE IC is adopted, the printed wiring of the device becomes easy. By using an expensive high withstand voltage process required for the V driver, a TG circuit to be manufactured by an inexpensive process is realized.
Therefore, the 3-in-1 type AFE IC is more expensive than the 2-in-1 type AFE IC in which TG is included in an image processing ASIC manufactured by a normal process.
On the other hand, when the 2-in-1 type AFE IC is employed, the TG and V driver are connected on the printed circuit board outside the IC, so the circuit scale inside the IC requiring an expensive high-voltage process. Is smaller than when 3-in-1 type AFE IC is adopted, but the number of printed wirings of the device increases.

That is, even when the 2-in-1 type AFE IC is employed, an image sensor control signal generation method that can suppress the number of printed wirings of the device is desired.
The invention according to the present application has been devised to meet such demands, has the advantages of both the methods (1-1) and (1-2), and further, the 2-in-1 type AFE IC. Is employed, the circuit scale inside the IC can be reduced, and the number of printed wirings of the device can be reduced.

[Outline of the embodiment of the present application]
FIG. 1 is a first diagram illustrating the timing of switching (toggling) the image sensor control signal in the embodiment of the present application.
As a method of switching control signals for controlling an imaging device such as a CCD imaging device, a method of grouping a plurality of control signals so as to have the same value at the same timing as indicated by reference numeral a in FIG. (An instruction for toggling a control signal included in such a group G is referred to as “toggle instruction G”. For example, “TGL G1, L” sets a control signal included in the group G1 to an L level, “TGL G2, H” indicates that control signals included in group G2 are set to H level).
On the other hand, there is a method of switching all control signals included in a plurality of groups to the same value at the same time as indicated by reference numerals b and c in FIG. 1 (toggling the control signals included in such a group STG). The instruction is described as “toggle instruction STG”. For example, “TGL STG1, L” sets the control signal included in the group STG1 to L level, “TGL STG2, H”, and the control signal included in the group STG2 is H. To set to level).
Each of the plurality of groups can include one or more ternary control signals, one or more binary control signals, or both, depending on the setting.
In addition, as indicated by the symbol b in FIG. 1, there is actually a case where each of the plurality of signals should be set to different values. In such a case, the plurality of signals are set. Each value is handled by being divided into a plurality of groups.

The image sensor control signal generation method shown as the embodiment of the present invention is a plurality of (for example, as shown by attaching b and c in FIG. Or a method of grouping a plurality of control signals so as to have the same value at the same timing, as indicated by the symbol a in FIG. And can be used together.
Note that the image sensor control signal generation method shown below is a program that is executed by specifically using hardware resources such as a CPU and a DSP, whether using dedicated hardware or a combination of general-purpose hardware. However, for the sake of concreteness and clarification of the description, a case where this method is realized by dedicated hardware (IC) will be taken as a specific example.
The specific examples shown below are intended only to clarify and embody the present invention and are not intended to limit the technical scope of the present invention.

[Digital camera 1]
FIG. 2 is a diagram illustrating the appearance of a first digital camera 1 to which the present invention is applied.
FIG. 3 is a diagram illustrating the configuration of the digital camera 1 shown in FIG.
As shown in FIG. 3, the digital camera 1 shown in FIGS. 1 and 2 includes an optical system 100, a CCD imaging device 2, an image memory 102, an image processing unit 104, a recording device 106, a recording medium 108, a user interface (UI). User Interface) section 110, V driver 112, control section 114, AFE 116, and control signal data generation section (CSDG) 3.
With these components, the digital camera 1 converts an optical image input via the optical system 100 into an electrical analog image signal by the CCD imaging device 2, and converts the analog image signal into a digital format. The image data is converted into image data, and further compressed and stored.

The CCD image pickup device 2 can be replaced with another image pickup device such as a CMOS image pickup device by appropriate modification of the configuration of the digital camera 1.
Each component of the digital camera 1 can be realized by dedicated hardware or software on an OS executed by a DSP or a CPU (not shown).
In addition, any two or more of the constituent parts of the digital camera 1 can be integrally configured, and the arbitrary constituent parts of the digital camera 1 are realized by dividing them into more constituent parts for each function. sell.

In FIG. 3, the control signal data generation unit 3 can generate a maximum of 26 control signal data. The case where the control signal is supplied is illustrated, but the number of the control signal data and the control signal is an example, and the number of the control signal data and the control signal is arbitrarily changed according to the configuration of the digital camera 1. Can be done.
2 and 3 illustrate the case where the present invention is applied to a digital still camera, but the present invention is not limited to other digital video cameras or the like. Applicable to image processing equipment.
In the following drawings, substantially the same components and processes are denoted by the same reference numerals.
The matters described here are the same for the second embodiment described later.

[CCD imaging device 2]
FIG. 4 is a diagram illustrating the configuration of the CCD image pickup device 2 shown in FIG.
As shown in FIG. 4, the CCD image pickup device 2 is a frame readout type CCD image pickup device, which includes n vertical CCD cells 204-rs and 2n photodiodes, respectively. It includes vertical CCDs 200-1 to 200-m having (PD; Photo Diode) 200-r-2s, a horizontal CCD 206, and an output amplifier 208.
Note that i, j, m, n, r, and s are integers, and m ≧ i, r ≧ 1, n ≧ j, and s ≧ 1, and m and n are not always the same number.
Further, hereinafter, when any of a plurality of possible components such as the vertical CCDs 200-1 to 200-m is described without being specified, the vertical CCD 200 may be simply abbreviated.

With these components, the CCD image pickup device 2 converts an optical signal of an image of an object to be picked up (not shown) formed on the image pickup surface of the CCD image pickup device 2 by the optical system 100 into an electrical signal by the PD 202. To do.
The vertical CCD 200 of the CCD image pickup device 2 has a ternary control signal corresponding to two ternary control signal data generated by the control signal data generation unit 3 from the V driver 112 and 2 corresponding to two binary control signal data. In response to the value control signal, the charge of the PD 202 is transferred to the horizontal CCD 206 and output as an image signal to the image memory 102 via the output amplifier 208.
In the CCD image pickup device 2, the ternary control signal is used as a vertical control signal for charge readout and charge vertical transfer, and the binary control signal is used as a vertical control signal for charge vertical transfer. It is done.

The image memory 102 (FIG. 3) stores digital image data input from the CCD image sensor 2 via the AFE 116 and outputs the image data to the image processing unit 104.
The image processing unit 104 processes the image data input from the image memory 102 and outputs the processed image data to the recording device 106 and the UI unit 110.
The recording device 106 records the image data input from the image processing unit 104 on a recording medium 108 such as a nonvolatile memory.
Further, the recording device 106 reads out data recorded on the recording medium 108 and causes the image processing unit 104 to store the data.

The UI unit 110 performs operations such as displaying an image to be imaged for a user (User) and pressing a shutter (Shutter).
The V driver 112 converts each of the ternary control signal data generated by the control signal data generation unit 3 to an L level voltage (for example, −7 V), an M level voltage (for example, −1 to +1 V), or an H level voltage. This is converted and output as a control signal to the CCD image pickup device 2 to control the PD 202 and the vertical CCD 200 included in the CCD image pickup device 2.
Further, the V driver 112 converts each of the binary control signal data generated by the control signal data generation unit 3 into an L level voltage or an M level voltage, and outputs it as a control signal to the CCD image sensor 2. The vertical CCD included in the CCD image sensor 2 is vertically controlled.
The control unit 114 includes, for example, a CPU and a memory, executes a program for controlling the entire digital camera 1 and each component on an OS (none of which is shown), and performs user operations on the UI unit 110. Accordingly, processing for realizing various functions of the digital camera 1 is performed, and data is written to the register 34 (described later with reference to FIG. 5 and the like) of the control signal data generation unit 3.

[Control signal data generator 3]
FIG. 5 is a diagram showing the configuration of the control signal data generation unit 3 shown in FIG.
FIG. 6 is a diagram exemplifying a configuration of an instruction code output from the microcontroller 302 illustrated in FIG. 5 to the instruction code decoder 4.
FIG. 7 is a diagram showing a configuration of the STG (simultaneous toggle group) decoder 40 shown in FIG. 5 and data stored in the register 34.
FIG. 8 is a diagram showing a configuration of the update logic 5-i (i = 1 to m; m is an integer of 1 or more, here m = 26) shown in FIG.
FIG. 9 is a diagram showing a configuration of the ID comparison circuit 50-k (k = 1 to n; n is an integer of 1 or more; here, k = 3) shown in FIG.

In the control signal data generating unit 3, any number of groups can be used. However, in the following description, the control signal data generating unit 3 uses eight groups STG1 to STG1 that can be designated by data of 3 bits. The case where STG8 is used is a specific example.
An arbitrary number of toggle instructions can be set for each of these eight groups STG1 to STG8. In the following description, a set of eight toggle instructions STGij ( Here, a case where i, j = 1 to 8) is used is a specific example.
The control signal data generation unit 3 can execute other instructions such as a branch instruction in addition to the signal switching instruction described below. In the following description, the control signal data generation unit 3 outputs the switching instruction. Only the case of execution is taken as a specific example.

As shown in FIG. 5, the control signal data generation unit 3 includes a program memory 300, a microcontroller 302 such as a CPU core, a register 34 that can be written from the control unit 114 (FIG. 3), and an instruction code decoder 4.
The instruction code decoder 4 includes x STG decoders 40 (x = 3 in the specific example shown in FIG. 5), m (also m = 26) update logic 5 and r (also r = 14) It is composed of three ternary decoders 42-1 to 42-r and s binary decoders 44-1 to 44-s (also r + s = m).
With these components, the control signal data generation unit 3 uses the instruction code input from the microcontroller 302, r ternary signals (H / M / L) from the data stored in the register 34, and s The binary signal (M / L) is generated and output to the V driver 112.

The instruction code output from the microcontroller 302 to the decoder 4 includes, as shown in FIG. 6, an operation code including three ID data ID1 to ID3 and level data LV1 to LV3 each having 9 bits, and control signal data. Operation codes such as a signal switching instruction and a branch instruction executed in the generation unit 3 are included.
However, the number of sets of ID data and level data included in the instruction code can be an arbitrary number of 1 or more.

Table 1 shows the contents of the level data [1: 0] included in the instruction code.
As shown in Table 1, the level data [1: 0] indicates the value of the ternary or binary control signal designated by the level data LVk corresponding to each of the ID data IDk (k = 1 to 3).
Each 6-bit ID data ID [5: 0] stores an operand ID shown in Table 2 below. The value of this operand ID is one of V1 to V26, G1 to G23, and STG1 to STG8. Specify the signal.

Table 2 shows the meaning of the value of the 6-bit data ID [5: 0] of each ID data IDk.
As shown in Table 2, V1 to V26 are specified by the values (000001 to 011010) of the ID data IDk [5: 0], G1 to G23 are specified by the values (100001 to 110111), and the value (111000 111111) designates STG1 to STG8.

  In addition, the value of ID data IDk [5: 0] other than these is not defined, and each update logic 5 is the ID data IDk [5: 0] for other ID data IDk [5: 0]. ], The values of V1 to V26, G1 to G23, and STG1 to STG8 immediately before the input are not changed.

Table 3 shows the contents of the group assignment data ViG [4: 0] stored in the register ViG340 of the register 34 shown in FIG.
As shown in FIG. 7, the STG decoder 40-k (here, k = 1 to 3) includes comparison circuits 402-1 to 402-8, a logical sum (OR) circuit 404, and a selector 406.
The register 34 includes a register ViG340-i (here, i = 1 to 26), a register ViL342, and a register STG344 (the same applies hereinafter).
In the register 34, a register ViG 340-i is provided corresponding to each of the update logics 5-i shown in FIG. ] Is memorized.

Table 4 shows the contents of the STG data [4: 0] stored in the register STG344 of the register 34 shown in FIG.
The register ViL is provided corresponding to each of the update logics 5-i. When the update logic 5-i outputs a binary signal, a logical value 0 (the logical values shown below are examples, and depending on the circuit configuration, When the update logic 5-i outputs a ternary signal, the 1-bit ternary / binary data ViL having a logical value of 1 is stored.

The register STGij 344 includes a set of eight pieces of data STG11 [4: 0] to 18 [4: 0], 21 [4: 0] to 28 [4: 0],. 4: 0] to 88 [4: 0] are stored.
In the example shown in FIG. 5, the value of ViL (i = 15 to 26) is fixed only to 0, while the value of ViL (i = 1 to 14) can be set to 0 or 1. .

When the ID data IDk [5: 0] designates any one of the groups STG1 to STG8, the group data IDkSTGM1 [4: 0] to IDkSTGM8 [4: 0] are respectively represented by the ID data IDk [5: 0]. The values of up to eight vertical control signals (V signals) included in the designated group STGk are designated.
For example, when the ID data IDk [5: 0] designates the group STG3, each of the group data IDkSTGM1 [4: 0] to IDkSTGM8 [4: 0] shows the following values.

IDkSTGM1 [4: 0]: value stored in register STG31 [4: 0];
IDkSTGM2 [4: 0]: value stored in register STG32 [4: 0];
IDkSTGM3 [4: 0]: value stored in register STG33 [4: 0];
・
・
IDkSTGM7 [4: 0]: value stored in register STG37 [4: 0]; and
IDkSTGM8 [4: 0]: value stored in the register STG38 [4: 0].

Any one of the comparison circuits 402-1 to 402-8 indicates that each value of the ID data ID1 [5: 0] to ID3 [5: 0] is any of (111000) to (111111) shown in Table 1. When the value is taken, a logical value 1 is output, otherwise a logical value 0 is output.
The OR circuit 404 sets the logical value of the logical value IDkSTGVALID indicating that the ID data IDk is valid when the logical value output from any of the comparison circuits 402-1 to 402-8 is 1, In other cases, the logical value is set to 0 and output to the update logic 5.

  When the lower 3 bits of the ID data IDk [5: 0] of the instruction code (FIG. 6) input from the microcontroller 302 indicate the numerical value i (= 000 to 111), the selector 406 selects the registers STG344-i1 to 344- Group data IDkSTGM1 [4: 0] to select i8 and designate data STGi1 to i8 stored in registers STG344-i1 to 344-i8 as groups corresponding to the input instruction code (FIG. 6). Output to the update logic 5 as IDkSTGM8 [4: 0].

As illustrated in FIG. 8, the update logic 5 includes an ID comparison circuit 50-k (k = 1 to 3), an update control unit 52, a selector 54, and a latch circuit 56.
As shown in FIG. 9, the ID comparison circuit 50 includes comparison circuits 500-1, 500-2, 500-3-1 to 500-3-8, AND circuits 502-1 and 502-2, and a logical sum (OR). The circuit 504 is configured.
In the ID comparison circuit 50-k, the comparison circuit 500-1 has, for example, the value of the most significant bit of the ID data IDk [5: 0] is 0, and ID data IDk [4: 0] outputs a logical value 1 when it matches the 5-bit ID data ViID set in each of the update logics 5 as shown in Table 2 and FIG. 6, and outputs a logical value 0 otherwise. To do.

  In the comparison circuit 500-2, for example, the value of the most significant 3 bits [5: 3] of the ID data IDk [5: 0] indicates one of G1 to G23 as shown in Table 2 (100 to 110), when the lower 5 bits [4: 0] of the ID data IDk [5: 0] match the data stored in the register ViG [4: 0], a logical value 1 is output. Otherwise, a logical value 0 is output.

The comparison circuit 500-3-i (i = 1 to 8) transmits the group data IDkSTGMi [4: 0] input from the STG decoder 40-k and the update logic 5 as shown in Table 2 and FIG. When the set ID data ViID of the 5-bit configuration matches, the logical value 1 is output to the OR circuit 504 as the logical value of the logical value IDkSTGVALID. Otherwise, the logical value 0 is output to the OR circuit 504. Output.
The AND circuit 502-i is a logical product of the logical value of the logical value IDkSTGVALID input from the STG decoder 40-k and indicating that the ID data IDk is valid, and the logical value output from the comparison circuit 500-3-i. Is output to the OR circuit 504.
The OR circuit 504 updates the logical value 1 when the logical value output from any of the AND circuits 502-1 to 502-3-8 is 1, and the logical value 0 otherwise, as shown in FIG. Output to the update control unit 52 of the logic 5.

In the update logic 5-i shown in FIG. 8, the update control unit 52 uses the level data LVk [1: 0] is selected and output to the latch circuit 56 as control signal data.
In other words, in the update control unit 52, the output signal of the ID comparison circuit 50-1 shown in FIG. Sometimes, the selector 54 is controlled so as to select the level data LV1 [1: 0] and output to the latch circuit 56.

Further, the update control unit 52 outputs the level data when the output signal of the ID comparison circuit 50-2 has a logical value 1 and the output signals of the other ID comparison circuits 50-1 and 50-3 have a logical value 0. LV2 [1: 0] is selected and output to the latch circuit 56.
The update control unit 52 also outputs level data when the output signal of the ID comparison circuit 50-3 has a logical value 1 and the output signals of the other ID comparison circuits 50-1 and 50-2 have a logical value 0. The selector 54 is controlled so as to select LV3 [1: 0] and output to the latch circuit 56.

In addition, the update control unit 52 has the logical value 0 as the value of the ternary / binary data ViL input from the register ViL 342 (eg, FIG. 7) of the register 34 and the selected level data LVk [1: 0. ] Indicates the H level of the ternary signal (high level; there is no H level in the binary signal), the latch enable signal (Latch Enable; EN) to the latch circuit 56 is inactivated and the selector 54 selects The stored value is not stored in the latch circuit 56.
In addition, the update control unit 52 has a logical value of 0 for the ternary / binary data ViL input from the register ViL342, and the selected level data LVk [1: 0] is at the H level of the ternary signal. In other cases, the latch enable signal EN to the latch circuit 56 is activated, and the value selected by the selector 54 is stored in the latch circuit 56.

That is, when the value of the ternary / binary data ViL input from the register ViL 342 is a logical value 1, the update control unit 52 stores the value selected by the selector 54 in the latch circuit 56, and the ternary / binary value. When the value of the data ViL is a logical value 0 and the value selected by the selector 54 indicates the M level (medium level) or the L level (low level), the latch circuit 56 stores the value selected by the selector 54. In other cases, the value selected by the selector 54 is not updated in the latch circuit 56.
The control signal data stored in the latch circuit 56 of the update logic 5-i (here, i = 1 to 26; FIG. 5) is output to the ternary decoder 42 and the binary decoder 44 (FIG. 5).

5 converts the control signal data input from the update logic 5-i into a ternary (H / M / L) control signal. And output to the V driver 112.
The binary decoder 44-i (here, i = 15 to 26) converts the control signal data input from the update logic 5-i into a binary (M / L) control signal, and sends it to the V driver 112. Output.

[Overall operation of digital camera 1]
The overall operation of the digital camera 1 (FIGS. 2 and 3) will be described below with an emphasis on the operation of the control signal data generator 3 (FIGS. 3, 5, and 7 to 9).
When an optical signal of an image to be photographed is input to the CCD image sensor 2 (FIG. 4) via the optical system 100 (FIG. 3), the CCD image sensor 2 receives the optical signal of the input image. Is converted into an electrical signal (charge).
When the control unit 114 controls the control signal data generation unit 3 in response to a user operation on the UI unit 110, the microcontroller 302 (FIG. 5) of the control signal data generation unit 3 stores it in the program memory 300. The generated program (not shown) is executed, an instruction code (FIG. 6) is generated, and output to the STG decoders 40-1 to 40-3 and the update logic 5-1 to 5-26 of the instruction code decoder 4. To do.

In the STG decoder 40-k, the register 34 is assigned to the register ViG340, the register ViL342, and the register STG344 (FIG. 7 and the like) in advance by the control unit 114 and the like. Data [4: 0] (Tables 1 to 3) is stored.
In the STG decoder 40-k, the selector 406 (FIG. 7) sets the register in accordance with the value indicated by the lower 3 bits (IDk [2: 0]) of the ID data IDk (k = 1 to 3) of the operand of the instruction code. Simultaneous toggle groups STG11 [4: 0] to STG18 [4: 0], simultaneous toggle groups STG21 [4: 0] to STG28 [4: 0] stored in the STG 344,. , Simultaneous toggle groups STG81 [4: 0] to STG88 [4: 0], one set of simultaneous toggle groups STGi1 [4: 0] to STGi8 [4: 0] is selected and group data IDkSTGM1 [4: 0] is selected. ] To IDkSTGM8 [4: 0] and output to the update logic 5.
Further, the comparison circuits 402-1 to 402-8 respectively compare the ID data IDk [5: 0] with the STG IDs (111000) to (111111) shown in Table 1, and the OR circuit 404 compares them. Based on the comparison result of the circuit 402, when the ID data IDk [5: 0] matches any of the STG IDs (111000) to (111111), the logical value of the logical value IDkSTGVALID is set to 1 and the update logic 5 Output.

In the ID comparison circuit 50-k (FIG. 8), the comparison circuit 500-1 (FIG. 9) sets the operand IDk [5; 0] input from the microcontroller 302 (FIG. 5) and the update logic 5. The obtained ViID is compared, and when they match, a logical value 1 is output to the OR circuit 504, and otherwise, a logical value 0 is output.
The comparison circuit 500-2 compares the operand IDk [5: 0] with the group assignment data ViG [4: 0] input from the register ViG340 of the register 34 (FIG. 5). 1 is output to the OR circuit 504 at other times.

Each of the comparison circuits 500-3-1 to 500-3-8 has ViID set for the update logic 5 and group data IDkSTGM1 [4: 0] to IDkSTGM8 [4: input from the STG decoder 40-k. 0] are compared with each other, and when these coincide with each other, a logical value 1 is output to the OR circuit 504. Otherwise, a logical value 0 is output to the OR circuit 504.
Each of the AND circuits 502-1 to 502-8 has a logical value of 1 input from each of the comparison circuits 500-3-1 to 500-3-8, and a logical value IDkSTGVALID input from the STG decoder 40-k is A logical value 1 is output to the OR circuit 504 only when it is 1, and a logical value 0 is output otherwise.
The OR circuit 504 outputs a logical value 1 when the logical value output from any of the comparison circuits 500-1, 500-2, 500-3-1 to 500-3-8 is 1, and outputs a logical value when the value is higher. The value 0 is output to the update control unit 52 (FIG. 8).

The update control unit 52 of the update logic 5-i (FIG. 8) has a logical value input from the ID comparison circuit 50-k of 1, and the ternary / binary data ViL input from the register ViL342 of the register 34. When the logical value of 1 is 1, the level data LVk (Table 1) of the instruction code (FIG. 6) is selected by the selector 54, the selected level data k is stored in the latch circuit 56, and the ternary decoder 42 is stored. (FIG. 5).
Further, the update control unit 52 has a logical value of 1 input from the ID comparison circuit 50-k and a logical value of the ternary / binary data ViL input from the register ViL342 of the register 34 is 0. , The level data LVk (Table 1) of the instruction code (FIG. 6) is selected by the selector 54, and the update control unit 52 only displays when the selected level data k indicates the level M or the level L. The selected level data k is stored in the latch circuit 56 and output to the binary decoder 44.

In other cases, the update control unit 52 does not store the selected level data k in the latch circuit 56, and maintains the value stored in the latch circuit 56 until then.
The ternary decoder 42 and the binary decoder 44 convert the level data input from the update logic 5-i into a control signal and output it to the V driver 112 (FIG. 3).
As described above, all of the one or more control signals included in each of the STG groups 1 to 8 are simultaneously set to values specified by the level data by the STG toggle instruction indicated by one instruction code (FIG. 6). Is set.

The V driver 112 controls the CCD image pickup device 2 (FIG. 4) using the control signal input from the control signal data generation unit 3, and outputs the image data obtained by the conversion to the image memory 102.
The image processing unit 104 performs processing such as compression on the image data stored in the image memory 102, and stores it in the recording medium 108 attached to the recording device 106.

FIG. 10 is a diagram illustrating the generation of control signals by the method indicated by the symbol a in FIG. 1, where (A) shows the waveform of each control signal, and (B) shows (A) The command for obtaining the control signal shown in FIG.
FIG. 11 is a diagram illustrating generation of a control signal by the method according to the present invention, in which (A) shows the waveform of each control signal and (B) obtains the control signal shown in (A). The instruction for is illustrated.

The waveforms of the control signals shown in FIGS. 10 (A) and 11 (A) are the same.
In the examples shown in FIGS. 10A, 10B, 11A, and 11B, the ID data of the instruction code (FIG. 6) is set so that a plurality of signals can be toggled by one instruction. Although the number of level data sets can be increased up to 3, eventually, the instruction size of one instruction increases in proportion to the number, so for the sake of specific explanation and clarification, one instruction code is A specific example is a case where a set of one ID data and level data is included.

For example, as shown in FIG. 10A, the control signals V1 and V2 are group G1, V13 and V14 are group G2, V15 and V16 are group G3, V17 and V18 are group G4, and V19 and V20 are In order to obtain the waveforms of the control signals shown in FIG. 10A when the group G5 is set and the values of the control signals are changed in units of the groups G1 to G6 with the groups G21 and V22 as the group G6, for example, As shown in FIG. 10B, 48 toggle instructions are required.
On the other hand, as shown in FIG. 11A, the control signals V1, V2, V13 to V16 are the simultaneous toggle group STG1 in the method according to the present invention, the control signals V17 to V22 are the group STG2, and the control signals V13 to V16 are used. 11 is the simultaneous toggle group STG3, the control signals V17 to V20 are the simultaneous toggle group STG4, and when the value of the control signal is changed by the method according to the present invention for each of these simultaneous toggle groups STG1 to STG4, FIG. In order to obtain the waveform of each control signal shown in FIG. 10, for example, 20 toggle commands are sufficient as shown in FIG.

[Characteristics of Control Signal Data Generation Unit 3]
When each of the plurality of control signals V is included in one or more groups and the value is changed for each group, for example, as illustrated in this embodiment, there are 26 control signals V and one control signal Can be included redundantly in the eight groups G1 to G8, 26 (number of control signals) × 4 bits (unassigned, designation of G1 to G8) × 8 (number of groups that can be overlapped) = An 832-bit register is required.
According to the embodiment of the present application, a register required for allowing one control signal V to be included so that the simultaneous toggle groups STG1 to STG8 can be overlapped is 8 (the number of overlapping groups) × 5 bits (control) (Designation of signals V1 to V26) × 8 (maximum number of simultaneous toggles) = 320 bits, so the adoption of the control signal data generation unit 3 makes the circuit scale for generating control signal data smaller than in the prior art.
Furthermore, in the present embodiment, since the group G and the simultaneous toggle group STG can be used in combination, the CCD image pickup device 2 can be realized with a small number of instruction codes with various and precise controls.
Therefore, according to the present embodiment, a 3-in-1 type AFE IC timing generator having a small circuit scale and capable of simultaneously toggling many signals is realized.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described.
FIG. 12 is a diagram illustrating the configuration of the second digital camera 6 to which the present invention is applied.
For example, the second digital camera 6 has the same appearance as the first digital camera 1 shown in FIG. 2, and the digital camera 6 is similar to the first digital camera 1 as shown in FIG. , An optical system 100, a CCD image pickup device 2 (FIG. 4), an image memory 102, an image processing unit 104, a recording device 106, a recording medium 108, and a UI unit 110.

In addition to the components common to those of the first digital camera 1, the digital camera 6 further generates a horizontal control signal and supplies it to the CCD image pickup device 2, and a switching signal. Generating unit 60, generating a vertical control signal and supplying the CCD image pickup device 2 with the control signal generating unit 7, and generating a clock signal used for operating each component of the digital camera 6 A (CG; Clock Generator) unit 606 is included as a component.
As with the first digital camera 1, the second digital camera 6 converts an optical image input via the optical system 100 into an electrical analog image signal by the CCD image sensor 2. The analog image signal is converted into digital image data and stored.

  In the digital camera 6, the switching signal generation unit 60 includes a CPU 600 and a memory 602, executes a program stored in the memory 602 in advance, and performs switching signals VGRP <1> to VGRP <6>, VLVL <1>, VLVL <2> is generated, and the generated switching signals VGRP <1> to VGRP <6>, VLVL <1>, and VLVL <2> are generated by the clock signal supplied from the CG 606 to the control signal generator 7. Output at the specified timing.

Table 5 is a table illustrating the contents of the switching signals VGRP <1> to VGRP <6>, VLVL <1>, and VLVL <2> output from the switching signal generator 60 shown in FIG.
As illustrated in Table 5, the switching signals VGRP <1> to VGRP <6> are expressed as 6-bit data VGRP [1: 6], and VGRP [1: 6] is (100001) to (110111). The switching signals VGRP <1> to VGRP <6> have the values of the signal groups G1 to G23 corresponding to the values of VGRP [1: 6] as the switching signals VLVL <1> and VLVL <. Toggle to the level specified by the value of 2>.
Note that an instruction sequence as will be described later with reference to FIGS. 20 to 22 can also be generated from the switching signal generator 60.

Further, when VGRP [1: 6] takes the values (111000) to (111111), the values of the signals included in the simultaneous toggle groups STG1 to STG8 corresponding to the values of these VGRP [1: 6] This indicates that the signal is toggled to a level specified by the values of the switching signals VLVL <1> and VLVL <2>.
When VGRP [1: 6] takes a value of (000000), VGRP [1: 6] of this value indicates a delimiter signal.
The delimiter signal (hereinafter, “delimiter signal” is also referred to as “delimiter instruction (delimiter instruction)”) is used as a series of toggle instruction sequence (executed simultaneously) or as an instruction code indicating a NOP (No Operation) operation. It is done.

For example, when a delimiter signal is input after three toggle instructions are sequentially input, the three input toggle instructions are executed simultaneously.
On the other hand, for example, when one toggle instruction, one delimiter signal, two toggle instructions, and one delimiter are sequentially input, one clock cycle is executed after the previous one toggle instruction is executed. The latter two toggle instructions are executed at the same time.
When only the delimiter signal is input continuously, no toggle command is input other than the delimiter signal, so that the toggle operation does not occur.

The delimiter signal is added as a signal indicating the end of the synchronized switching signal when the number of synchronized switching signals is less than the maximum number.
However, when VGRP [1: 6] takes a value of (000001) to (011010), the delimiter signal is changed from the signals V1 to V26 corresponding to the values of VGRP [1: 6] to the switching signal VLVL < Toggle to the level specified by the values of 1> and <2>.

FIG. 13 is a diagram showing the configuration of the control signal generator 7 shown in FIG.
FIG. 14 is a diagram illustrating a toggle instruction generated by the command generation unit 70 shown in FIG.
As shown in FIG. 13, the control signal generation unit 7 includes a command generation unit 70, a transfer unit 72 including a counter unit 720, registers R0, R1 <1> to R <3>, R2 <1>, R <2>. To R6 <1>, a multiplexer (MUX) 726-1 and 726-2, a command execution unit 8, and a register 34 (FIGS. 5 and 7).
The control signal generator 7 processes the switching signals VGRP <1> to VGRP <6>, VLVL <1>, and VLVL <2> input from the switching signal generator 60 (FIG. 12) using these components. Thus, ternary vertical synchronization signals XV1 / XP1 to XV26 / XP26 and binary vertical control signals XV15 to XV26 for the CCD image pickup device 2 are generated.
If the ternary signal is expressed by ordinary binary logic, x2 binary signals are required (for example, 00 => L, 01 => M, 10 => H level). A ternary signal V1 is expressed by this set.
In the V driver, this is finally converted into one signal (in a buffer circuit realized by a high withstand voltage process).
This buffer circuit can output three kinds of voltages, while the binary signal is the same as the normal binary logic, so it can be expressed by one signal (for example, the binary signal V15 can be expressed only by XV15). .
The signal name XV / XP is derived from the name of the input signal when the V driver is configured as one independent IC and is widely used.

In the control signal generation unit 7, the command generation unit 70 processes VGRP [6: 1] and VLVL [2: 1] input from the switching signal generation unit 60, generates a toggle instruction, and transfers the transfer unit. 72 is output.
In addition, the command generation unit 70 outputs the generated switching command to the transfer unit 72 at a predetermined timing defined by the clock signal generated by the CG 606 (FIG. 12).
As shown in FIG. 14, the toggle instruction includes, for example, identifier (ID) data indicating VGRP [6: 1] and level (LV) data indicating VLVL [2: 1].
The transfer unit 72 accepts the command generated by the command generation unit 70 via the register R0.

The CG 606 generates and supplies a clock signal used for processing of each component of the control signal generator 7.
The counter unit 720 of the transfer unit 72 counts the clock signal supplied from the CG 606, and the transfer unit 72 outputs the toggle command or initial value stored in the register 722 to the MUXs 726-1 and 726-2 and the command execution unit 8. Counter values defining the transfer timing are generated and stored, and supplied to these components.

The value of the counter signal is an integer from 1 to 7, for example, and is incremented by 1 in synchronization with the CG 606, with 1 being an initial value.
When the value of the counter reaches 7, the transfer unit 72 transfers the toggle instruction or initial value stored in the register 722 to the command execution unit 8, and initializes the count value to 1 after this transfer.
A plurality of counter signals can be generated. In this case, for example, counter value 1, counter value 2,..., Counter value n (n is an integer of 1 or more) are named in the order of generation. Is managed.

[Transfer unit 72]
FIG. 15 is a first flowchart illustrating the operation (S72) of the transfer unit 72 shown in FIG.
FIG. 16 is a second flowchart illustrating the count signal generation process (S74) shown in FIG.
The transfer unit 72 controls the toggle instruction register 722 to store data in the register 722 and transfer (shift) it.

Hereinafter, the operation of the transfer unit 72 will be described with reference to FIGS. 15 and 16.
As shown in FIG. 15, in step 720 (S720), the transfer unit 72 displays s indicating the row number of the register 722 (FIG. 13) stored therein (for example, if s = 1, then s is R1 <1> to R1 <3> indicating the line number 1) is initialized to “1”.
In step 722 (S722), the transfer unit 72 stores the toggle instruction input from the command generation unit 70 (FIG. 13) in the register R0, and proceeds to the process of S740 (FIG. 16).

In step 74 (S74; FIG. 16), the counter unit 720 of the transfer unit 72 generates a counter signal according to a predetermined condition (the processing content of S74 will be described later with reference to FIG. 16).
In step 726 (S726), the transfer unit 72 determines whether 7 exists in the value of the generated one or more counter signals.
When 7 is present in the value of the generated one or more counter signals, the transfer unit 72 proceeds to the process of S728, and otherwise proceeds to the process of S730.

In step 728 (S728), the transfer unit 72 outputs the following toggle commands (1) to (3) or initial values to the command execution unit 8.
(1) A toggle instruction or initial value selected by outputting a toggle instruction or initial value stored in the register 722 (R1 <1> to R1 <3>) to the MUX 726-1;
(2) A toggle instruction or initial value selected by outputting a toggle instruction or initial value stored in the registers R2 <1> and R2 <2> to the MUX 726-2; or (3) Registers R0 and R3 <1> -toggle instruction or initial value stored in R6 <1>.

In the following, for the sake of concreteness and clarification of the description, when the toggle command shown in FIG. A specific example is a case where the toggle instruction 1-2 is given in the second period,..., And the toggle instruction 4-2 is given in the eighth clock.
The toggle instruction 1-1 is sequentially stored in the register 722 (R1 <1>; FIG. 13) as one of the “first toggle instructions” of the input toggle instruction sequence before the delimiter signal is input. The

Next, the toggle instruction 2-1 is also input to the register 722 (R1 <1>) as one of the “first toggle instructions” of the next toggle instruction sequence.
At this time, since the toggle instruction 1-1 is already stored in the register 722 (R1 <1>), the register 722 (R1 <1> to R1 <3>) stores 3 in order to save it. Before the value is newly written to the register 722 (R1 <1>), the contents of the register 722 (R1 [2: 1]) are stored in advance in the register 722 (R1 [3: 2]). Shifted to.
The reason why the register 722 (R1 <1> to R1 <3>) has a three-stage configuration is that a short instruction sequence of “toggle instruction” and “delimiter signal” is repeated as can be understood with reference to FIG. This is because it is necessary to hold a maximum of three instructions when input.

However, here, it is assumed that the toggle instruction is executed 8 clocks after the first toggle instruction (here, toggle instruction 1-1) is received.
This premise is to receive and store a maximum of seven toggle instructions so that these toggle instructions can be executed simultaneously.
Although different from the example shown in FIG. 21, for example, when the toggle instructions 1-1 to 1-7 are sequentially input without inserting a delimiter signal between them, the register 722 Seven toggle instructions stored in (R1 <1>, R2 to R6, R0) are executed simultaneously.

In step 730 (S730), the transfer unit 72 determines whether the toggle instruction stored in the register R0 in the process of S722 is a delimiter command.
If the toggle instruction stored in the deregister R0 is a limiter command, the transfer unit 72 proceeds to the process of S720, and otherwise proceeds to the process of S732.

In step 732 (S732), the transfer unit 72 moves the value stored in the register Rs <k> (here k = 1 to 3) in the s-th row of the register 722 (FIG. 13) to the right in FIG. Shift (shift right).
That is, for example, when s = 1, the transfer unit 72 stores the values stored in each of R1 <1> to R1 <3> in the register 722 (R1 <2>, R1 <3>) ( In this case, the stored contents of the register 722R1 <3> are discarded).
However, in the configuration of the control signal generation unit 7 illustrated in FIG. 13, the registers R3 <1> to R6 <1> have only one register in one row. Therefore, when s = 3 to 6, The transfer unit 72 does not shift the register 722 to the right.

In step 734 (S734), the transfer unit 72 causes the register Rs <1> in the register 722 to store the toggle instruction stored in the register R0 in S722.
In step 736 (S736), the transfer unit 72 determines whether s = 6.
When S = 6, the transfer unit 72 proceeds to the process of S720, and otherwise proceeds to the process of S738.
In step 738 (S738), the transfer unit 72 increments the value of s (increases the value of s by 1), and returns to the process of S722.

[Counter generation processing]
In the counter generation process by the transfer unit 72, when a toggle instruction other than the delimiter command is output to the register R1 <1> (FIG. 13) of the register 722, the counter unit 720 generates a new counter signal. To do.

As shown in FIG. 16, in step 740 (S740), the counter unit 720 (FIG. 13) of the transfer unit 72 determines whether or not s = 1.
When s = 1, the transfer unit 72 proceeds to the process of S742, and otherwise returns to the process of S726 (FIG. 15).

In step 742 (S742), the counter unit 720 determines whether the toggle instruction is a delimiter command.
When the toggle instruction is a delimiter command, the transfer unit 72 returns to the process of S726, and otherwise, proceeds to the process of S744.
In step 744 (S744), the counter unit 720 generates a new counter signal and returns to the process of S726.

Registers 722 (R0, R1 <1> to R1 <3>, R2 <1>, R2 <2>, R3 <1>, R4 <1>, R5 <1>, R6 <1>) are digital cameras. For example, a numerical value 0 is stored as an initial value when it should be initialized, such as at the time of activation of 6.
The register R 0 of the register 722 stores the toggle instruction input from the command generation unit 70 and outputs it to the transfer unit 72.

When the MUX 726-1 accepts the toggle instruction or initial value stored in the registers R1 <1> to R1 <3>, the column number is the largest among the registers R1 <1> to R1 <3> to which the toggle instruction is input. The toggle instruction stored in the register is output to the command execution unit 8.
Also, the MUX 726-1 outputs an initial value to the command execution unit 8 when none of the registers R1 <1> to R1 <3> stores a toggle instruction.

When the MUX 726-2 receives the toggle instruction or the initial value stored in the registers R2 <1> and R2 <2>, the column number of the registers R2 <1> and R2 <2> having the toggle instruction input is the largest. The toggle instruction stored in the register is output to the command execution unit 8.
The MUX 726-2 outputs an initial value to the command execution unit 8 when neither of the registers R2 <1> and R2 <2> stores a toggle instruction.

Although there are seven STG decoders 40-k, the control signal generator 7 contains only signals from six registers / MUX.
However, in FIG. 13, an instruction is directly transmitted from the transfer unit 72 to the command execution unit 8 as indicated by an arrow of the command execution unit 8 from the transfer unit 72 immediately below the portion surrounded by a dotted line. Since it is output, the control signal generator 7 can execute a total of seven instructions.

FIG. 17 is a diagram illustrating a configuration of the command execution unit 8 illustrated in FIG.
As shown in FIG. 17, the command execution unit 8 includes seven STG decoders 40-k-1 to 40-7 (FIG. 5), update logic (3 <1> to 3 <14>, 2 <1> to 2 [2: 1]) 5-1 to 5-26 (FIGS. 8 and 9), a ternary signal for vertical control and a ternary value for generating a binary signal output directly to the CCD image pickup device 2, respectively. It comprises decoders 84-1 to 84-14 and binary decoders 86-1 to 86-12.
Actually, the command execution unit 8 corresponds to the registers and output circuits for realizing the following operation examples 1 to 3 to the ternary signals XV1 / XP1 to XV14 / XP14 and the binary signals XV15 to XV26, respectively. However, in order to prevent complication of the illustration and clarify, these components are omitted in FIGS. 17 to 19 and only the configuration for realizing the following operation example 4 is provided. It is shown.

The update logics 5-1 to 5-26 may be created as the same logic. In this case, for example, the update logics 5-15 to 5-26 generate binary signals. For example, a numerical value 0 indicating the data ViL supplied from the register 34 (in this case, i = 1 to 26) is set, and the update logic 5 thus set is binary. The update logic 5 that is used for signal generation and for which this setting has not been made is used for generation of a ternary signal.
With these components, the command execution unit 8 performs toggle instructions or initial values input from the registers 722 and MUX 726 (FIG. 13) and group assignment data ViG [4: 0] (from the register 34). The command execution unit 8 processes i = 1 to 26 and the simultaneous toggle groups STG1 to STG8) to generate ternary signals XV1, XP1 to XV14, XP14 and binary signals XV15 to XV26, and the CCD is used as a vertical control signal. Output to the image sensor 2 (FIG. 12).

FIG. 18 is a diagram showing a configuration of the update logic 5 shown in FIG.
FIG. 19 is a diagram showing a configuration of the STG decoder 40-k in the command execution unit 8 shown in FIG.
As illustrated in FIG. 18, the update logic 5 has the same configuration as the update logics 5-1 to 5-26 in the first control signal data generation unit 3 illustrated in FIG. 9 except for the number of ID comparison circuits 50.
Similarly, as shown in FIG. 19, in the command execution unit 8, the number of STG decoders 40-k is seven for the reason described above, and as shown in FIG. 19, the command execution unit 8 In FIG. 7, the number of ID comparison circuits 50 of the update logic 5 is seven.
That is, the update logic 5 in the first control signal data generation unit 3 and the update logic 5 in the second command execution unit 8 differ only in the number of ID comparison circuits 50 inside (more precisely, The difference is that the number of level data input to the selector 54 is also 7).

[Operation of Control Signal Generator 7]
Hereinafter, the operation of the control signal generator 7 shown in FIG. 12 will be described.
In FIG. 20, the ID data ID1 to ID7 generated by the command generation unit 70 and the transfer unit 72 shown in FIG. 13 and supplied to the command execution unit 8 are associated with the level data LV1 to LV7, respectively. It is a figure which illustrates the command sequence contained.
FIG. 21 is a second diagram illustrating an instruction sequence generated by the command generation unit 70 and the transfer unit 72 shown in FIG. 13 and supplied to the command execution unit 8, and every other delimiter. And a storage state of toggle instructions in the register 722 (R1 <1> to R1 <3>, R2 <1>, R2 <2>, R3 <1>) at each value of the counter signal including eight instructions FIG.
FIG. 22 is a third diagram illustrating an instruction sequence generated by the command generation unit 70 and the transfer unit 72 shown in FIG. 13 and supplied to the command execution unit 8, and includes 11 delimiters. It is a figure which illustrates a command sequence and the toggle instruction | indication of the register | resistor 722 (R1 <1> -R1 <3>, R2 <1>, R2 <2>, R3 <1>) in each clock.

[First operation example]
The operation of the control signal generator 7 (FIGS. 12 and 13) when the instruction sequence shown in FIGS. 14 and 20 is generated will be described below.
The command generation unit 70 (FIG. 13) performs the processing shown in FIG. The toggle instruction sequence shown in FIG. 20 is output and stored.
Since the toggle instruction 1 is output to the register R1 <1> and is not a delimiter command, the counter unit 720 generates the counter 1.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
Further, the transfer unit 72 receives the toggle instruction 1 stored in the register R0 and outputs it to the register 722 (R1 <1>).

When the value of the counter 1 takes 2 to 6, the command generator 70 outputs and stores toggle instructions 2 to 6 to the register R0 of the register 722, respectively.
When the value of the counter 1 takes 2 to 6, the transfer unit 72 performs the same processing as that for the value 1 and accepts the toggle instructions 2 to 6 stored in the register 722 (R0), respectively. The toggle instructions are stored in registers 722 (R2 <1> to R6 <1>), respectively.
When the value of the counter 1 is 7, the transfer unit 72 uses the toggle instruction 1 stored in the register 722 (R1 <1>) and the initial value stored in the register 722 (R1 <2>, R1 <3>). Are output to the MUX 726-1.
When the value of the counter 1 is 7, the transfer unit 72 receives the toggle instruction 2 stored in the register 722 (R2 <1>) and the initial value stored in the register 722 (R2 <2>). Output to MUX726-2.

That is, the toggle instruction 1 stored in the register 722 (R1 <1>) and the toggle instruction 2 stored in the register 722 (R2 <1>) are respectively transmitted to the command execution units via the MUXs 726-1 and 726-2. 8 is output.
When the value of the counter 1 is 7, the transfer unit 72 outputs the toggle instructions 3 to 7 stored in the registers R3 <1> to R6 <1> and R0 to the command execution unit 8.
By the operation described above, the command execution unit 8 executes the toggle instructions 1 to 7, stores the vertical control data obtained by the executed toggle instruction, and simultaneously performs the ternary decoder 84 and the binary decoder 86. A ternary and binary vertical control signal is generated and output to the CCD image pickup device 2.

[Second operation example]
The operation of the control signal generator 7 (FIGS. 12 and 13) when the instruction sequence shown in FIG. 20 is generated will be described below.
The command generation unit 70 (FIG. 13) outputs and stores a toggle instruction 1-1 to the register 722 (register R0).
The toggle instruction 1-1 is not a delimiter instruction but is output to the register 722 (R1 <1>), and the counter unit 720 generates the counter 1.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
Further, the transfer unit 72 accepts the toggle instruction 1-1 stored in the register 722 (R0), and outputs and stores the toggle instruction 1-1 in the register 722 (R1 <1>).

The command generation unit 70 outputs and stores the toggle instruction 1-2 to the register 722 (R0).
Since the toggle instruction 1-2 is a delimiter instruction, the transfer unit 72 does not output the toggle instruction 1-2 received from the register 722 (R0) to any of the registers 722.
That is, as shown in FIG. 21, when the value of the counter 1 is 2, the toggle instruction 1-1 is only stored in the register 722 (R1 <1>).

The command generation unit 70 (FIG. 13) outputs and stores the toggle instruction 2-1 to the register 722 (R0).
The toggle instruction 2-1 is not a delimiter instruction but is output to the register 722 (R1 <1>), and the counter unit 720 generates the counter 2.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
That is, the toggle instruction 1-1 stored in the register 722 (R1 <1>) is output to and stored in the register R1 <2>, and the transfer unit 72 performs the toggle instruction stored in the register 7222 (R0). 2-1 is received and output to the register 722 (R1 <1>) for storage.

The command generation unit 70 outputs and stores the toggle instruction 2-2 to the register 722 (R0).
The toggle instruction 2-2 is a delimiter instruction, and the transfer unit 72 does not output the toggle instruction 2-2 received from the register 722 (R0) to any of the registers 722.
That is, as shown in FIG. 21, when the value of the counter 1 is 4, toggle instructions 1-1 and 2-1 are stored in the registers 722 (R1 <2> and R1 <1>), respectively.

The command generation unit 70 (FIG. 13) outputs and stores the toggle instruction 3-1 to the register 722 (R0).
The toggle instruction 3-1 is not a delimiter instruction but is output and stored in the register 722 (R1 <1>), and the counter unit 720 generates the counter 3.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
That is, the toggle instruction 2-1 stored in the register 722 (R1 <1>) is output to and stored in the register 722 (R1 <2>), and the toggle instruction 2-1 stored in the register 722 (R1 <2>). The instruction 1-1 is output to the register R1 <3> and stored.
In addition, the transfer unit 72 receives the toggle instruction 3-1 stored in the register 722 (R0), and outputs and stores the toggle instruction 3-1 in the register 722 (R1 <1>).

The command generation unit 70 outputs and stores the toggle instruction 3-2 to the register 722 (R0).
Since the toggle instruction 3-2 is a delimiter command, the transfer unit 72 does not output the toggle instruction 3-2 received from the register R0 to any register of the register 722.
That is, as shown in FIG. 21, when the value of the counter 1 is 6, the toggle instructions 1-1, 2-1, and 3-1 are registered in the registers 722 (R1 <3>, R1 <2>, R1 <, respectively). 1>).

When the value of the counter 1 is 7, the transfer unit 72 (FIG. 13) sets the toggle instructions 3-1, 2-1 and 1-1 stored in the registers 722 (R1 <1> to R1 <3>), respectively. Is output to the MUX 726-1, and the toggle instruction 1-1 is output to the command execution unit 8 via the MUX 726-1.
The command execution unit 8 outputs the control signal belonging to the group indicated by the group identification information of the toggle instruction 1-1 in the output state indicated by the output state information of the toggle instruction 1-1.

When the transfer unit 72 performs the same processing as described above for the toggle instructions 4-1 and 4-2, when the value of the counter 2 is 7, the registers 722 (R1 <1> to R1 <3> (toggle instructions 4-1, 3-1, 2-1 stored respectively to MUX 726-1 and toggle instruction 2-1 to command execution unit 8 via MUX 726-1. Output.
The command execution unit 8 generates, holds, and holds the vertical control data indicating the value of the vertical control signal belonging to the group indicated by the group identification information of the toggle instruction 2-1, for the ternary decoder 84 and the binary decoder 86. At the same time, a binary signal and / or a ternary signal having a value indicated by the toggle command is generated or output to the CCD image pickup device 2.

[Third operation example]
The operation of the control signal generator 7 (FIGS. 12 and 13) when the instruction sequence shown in FIG. 22 is generated will be described below.
The command generation unit 70 (FIG. 11) outputs and stores a toggle instruction 1-1 to the register 722 (R0).
The toggle instruction 1-1 is not a delimiter command but is output and stored in the register 722 (R1 <1>), and the counter unit 720 generates the counter 1.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
Further, the transfer unit 72 accepts the toggle instruction 1-1 stored in the register 722 (R0) and outputs it to the register 722 (R1 <1>).

The command generation unit 70 outputs and stores the toggle instruction 1-2 to the register 722 (R0).
The toggle instruction 1-2 is not a delimiter command, but is not a toggle instruction output to the register R1 <1>. Therefore, the counter unit 720 does not generate a new counter.
The transfer unit 72 shifts the register 722 (R2 <1>, R2 <2>) to the right.
In addition, the transfer unit 72 receives the toggle instruction 1-2 stored in the register R0, and outputs and stores the toggle instruction 1-2 in the register 722 (R2 <1>).

The command generation unit 70 outputs and stores the toggle instruction 1-3 to the register 722 (R0).
The toggle instruction 1-3 is not a delimiter command, but is not a toggle instruction output to the register R1 <1>. Therefore, the counter unit 720 does not generate a new counter.
In addition, the transfer unit 72 receives the toggle instruction 1-3 stored in the register R0, and outputs and stores the toggle instruction 1-3 in the register 722 (R3 <1>).

The command generation unit 70 (FIG. 11) outputs and stores a toggle instruction 1-4 to the register R0 of the register 722.
Since the toggle instruction 1-4 is a delimiter command, the transfer unit 72 does not output the toggle instruction 1-4 received from the register R0 to any of the registers 722.
That is, as shown in FIG. 22, when the value of the counter 1 is 5, the toggle instructions 1-1, 1-2, 1-3 are registered in the registers 722 (R1 <1>, R2 <1>, R3 <1 respectively). >).

The command generation unit 70 (FIG. 11) outputs and stores the toggle instruction 2-1 to the register 722 (R0).
The toggle instruction 2-1 is not a delimiter instruction, but is output and stored in the register 722 (R1 <1>), and the counter unit 720 generates the counter 2.
The transfer unit 72 shifts the register 722 (R1 <1> to R1 <3>) to the right.
That is, the toggle instruction 1-1 stored in the register 722 (R1 <1>) is output to the register 722 (R1 <2>) and stored.
In addition, the transfer unit 72 receives the toggle instruction 2-1 stored in the register R0, and outputs and stores the toggle instruction 2-1 in the register 722 (R1 <1>).

When the transfer unit 72 performs the same processing on the toggle instruction 2-2, as shown in FIG. 22, when the value of the counter 1 is 7, the toggle instructions 2-1, 1-1, 2-2. , 1-2, 1-3 are stored in registers 722 (R1 <1>, R1 <2>, R2 <1>, R2 <2>, R3 <1>), respectively.
When the value of the counter 1 is 7, the transfer unit 72 uses the toggle instructions 2-1 and 1-1 stored in the register 722 (R1 <1>, R1 <2>) and the register 722 (R1 <3). >) Is output to the MUX 726-1.
When the value of the counter 1 is 7, the transfer unit 72 sends toggle instructions 2-2 and 1-2 stored in the registers 722 (R2 <1> and R2 <2>) to the MUX 726-2. Output.

That is, the toggle instruction 1-1 stored in the register 722 (R1 <2>) and the toggle instruction 1-2 stored in the register 722 (R2 <2>) are respectively connected via the MUXs 726-1 and 726-2. Are output to the command execution unit 8.
When the value of the counter 1 is 7, the transfer unit 72 outputs the toggle instruction 1-3 stored in the register 722 (R3 <1>) to the command execution unit 8.
The command execution unit 8 generates and holds vertical control data indicating the value of the vertical control signal belonging to the group indicated by the group identification information of the toggle instructions 1-1 to 1-3, and holds the ternary decoder 84 and the binary decoder. A binary signal and a ternary signal having a value indicated by the toggle command are generated or any one of them is output to the CCD image pickup device 2.

When the transfer unit 72 performs the same processing on the toggle instructions 2-3, 2-4, 3-1, 3-2, 4-1, the value of the counter 2 is 7 as shown in FIG. At some time, the toggle instructions 3-1, 2-1, 2-2, 2-3 are stored in the registers 722 (R1 <1>, R1 <2>, R2 <1>, R3 <1>), respectively. .
When the value of the counter 2 is 7, the transfer unit 72 performs the toggle instructions 3-1, 2-1 stored in the register 722 (R1 <1>, R1 <2>) and the register 722 (R1 <3). >) Is output to the MUX 726-1.
When the value of the counter 2 is 7, the transfer unit 72 uses the toggle instruction 2-2 stored in the register 722 (R2 <1>) and the initial value stored in the register 722 (R2 <2>). Is output to the MUX 726-2.

That is, the toggle instruction 2-1 stored in the register 722 (R1 <2>) and the toggle instruction 2-2 stored in the register 722 (R2 <1>) are respectively connected via the MUXs 726-1 and 726-2. Are output to the command execution unit 8.
When the value of the counter 2 is 7, the transfer unit 72 outputs the toggle instruction 2-3 stored in the register 722 (R3 <1>) to the command execution unit 8.
The command execution unit 8 generates and holds vertical control data indicating the value of the vertical control signal belonging to the group indicated by the group identification information of the toggle instructions 2-1 to 2-3, and holds the ternary decoder 84 and the binary decoder. A binary signal and a ternary signal having a value indicated by the toggle command are generated or any one of them is output to the CCD image pickup device 2.

[Fourth operation example]
Hereinafter, the operation (fourth operation example) of the control signal generator 7 (FIGS. 12 and 13) under the following operation conditions 1 to 3 will be described.
FIG. 23 is a fourth diagram illustrating an instruction sequence generated by the command generation unit 70 and the transfer unit 72 illustrated in FIG. 13 and supplied to the command execution unit 8.
[Operation Condition 1] The switching signal generator 60 sends the control signal switching signals VGRP <1> to VGRP <6>, VLVL shown in Table 5 to the command execution unit 8 via the command generator 70 and the transfer unit 72. <1> and VLVL <2> are output;
[Operation condition 2] The command generation unit 70 issues the instruction shown in FIG. 23 and outputs it to the STG decoder 40-k (FIG. 17);
[Operating Condition 3] Data STG11 [4: 0] to 88 [4: 0] and group allocation data ViG [4: 0] shown in FIGS. 7 and 18 are transferred from the register 34 to the STG decoders 40-1 to 40-7. ] And 1-bit ternary / binary data ViL are input.

[Operation related to simultaneous toggle group STG]
First, the operation related to the simultaneous toggle group STG of the control signal generator 7 will be described.
As described in the first to third operations of the control signal generator 7 (FIG. 13), the STG decoders 40-1 to 40-7 (FIGS. 17 and 18) have MUXs 726-1 and 726-2, respectively. The toggle instructions 1 to 7 shown in FIGS. 14 and 20, the ID data ID1 to ID7 included in these toggle instructions, and the level data LV1 to LV7 are input via the registers 722 (R3 to R6). .
The comparison circuits 402-1 to 402-7 (FIG. 18) of the STG decoders 40-1 to 40-7 are respectively shown in Table 5 and ID data ID1 to ID7 included in the input toggle instructions 1 to 7, respectively. The contents of the data VGRP [1: 6] ((000000) to (111111)) are compared.
When each of the input ID data ID1 to ID7 is a value corresponding to the simultaneous toggle groups STG1 to 8 shown in Table 5 (111000 to 111111), each of the comparison circuits 402-1 to 402-7 is a logical value. 1 is output to the OR circuit 404, and in other cases, a logical value 0 is output to the OR circuit 404.
The OR circuit 404 of the STG decoder 40 sets the logic value of IDkSTGVALID (here, k = 1 to 7) to 1 when one or more of the comparison circuits 402-1 to 402-7 output the logic value 1. In other cases, 0 is output to the update logic 5.

  Each of the selectors 406 (FIG. 18) of the STG decoders 40-1 to 40-7 has ID data IDk (here, instruction code ID data) input from the registers 722 (R3 to R6) and MUXs 726-1 and 726-2 (FIG. 13). When k = 1 to 7) indicates the simultaneous toggle group STGm (here, m = 1 to 8) shown in Table 5, STGk1 [4: 0] to STGk8 [4: 0] stored in the register 34. ] Is output to the update logic 5 (FIG. 19) as data IDkSTGM1 [4: 0] to IDkSTGM8 [4: 0].

In the update logic 5-i (FIG. 18, FIG. 19; here i = 1 to 26), the ID comparison circuit 50-k (here k = 1 to 7)
(1) The data IDkSTGM1 [4: 0] to IDkSTGM8 [4: 0] input from the STG decoder 40-k coincides with the ViID set in the ID comparison circuit 50-k; and (2) the STG decoder The logical value 1 is output to the update control unit 52 when the logical value of the data ID kSTGVALID input from 40-k is 1, and the logical value 0 is output otherwise.

In the update logic 5-i, the update control unit 52 controls the selector 54 when the logical value output from any of the ID comparison circuits 50-k is 1, and is input from the register 34 and receives the ID data IDk. Is selected and output as control signal data to the latch circuit 56.
The latch circuit 56 stores the level data LVk input to the selector 54 in response to the enable signal EN input from the update control unit 52, and the ternary decoder 84 connected to the latch circuit 56 or the vertical control data Output to the binary decoder 86 (FIG. 13).
The ternary decoder 84 and the binary decoder 86 convert the vertical control data input from the update logic 5 into a ternary or binary vertical control signal and output it to the CCD image sensor 2.

[Operations related to normal group G]
Hereinafter, the operation of the control signal generator 7 for the normal group G will be described.
When the control signal generator 7 is operated so as to control the vertical control signal for each of the normal groups G1 to G23, each ID comparison circuit 50 from the register 34 is connected to each ID comparison circuit 50 of the update logic 5. Group data ViG [4: 0] indicating which of the groups G1 to G23 belongs is used.

In the update logic 5-i (FIG. 18; here, i = 1 to 26), the ID comparison circuit 50-k (here, k = 1 to 7) has the logical value of the data IDkSTGVALID input from the STG decoder 40 being 0. In the case of
From the group G indicated by the data ViG input from the register 34 and the switching signal generation unit 60 (FIG. 12), the ID comparison circuit 50-k (in this case k = 1 to 1) via the command generation unit 70 and the transfer unit 72. 7) and the group G indicated by the value (000001 to 110111) of the data VGRP [1: 6] (that is, the data VGRP [1: 6] becomes the ID data IDk [5: 0]) input to 7). Then, the update logic 5 included in any one of the groups G1 to G23 indicated by the data ViG receives the group G indicated by the value of VGRP [1: 6] (000001 to 110111) and the data VLVL <1>, Vertical control data having a value suitable for the combination with <2> is output to the ternary decoder 84 and the binary decoder 86.
The ternary decoder 84 and the binary decoder 86 generate ternary and binary vertical control signals according to the vertical control data from the update logic 5, and output them to the ternary decoder 84 and the binary decoder 86.

[Operation for individual vertical control data]
Hereinafter, the operation of the control signal generation unit 7 regarding individual vertical control signals will be described.
When controlling the vertical control data irrespective of the groups G and STG, the identifier ViID (i = 1 to 26 in this case) set in each update logic 5-i is used.

In the update logic 5-i (FIG. 18; here i = 1 to 26), the ID comparison circuit 50-k (here k = 1 to 7) receives the logical value of the data IDkSTGVALID input from the STG decoder 40-k. If is 0,
(1) ID data IDk (operand) included in the toggle instruction matches the identifier ViID set in the update logic 5; and (2) Data ViG input from the register 34 (00001 to 11010; Table 5) The update indicated by the ID data IDk of the toggle instruction when the data indicated by matches one of the values (000001 to 110111) of the seven data VGRP [1: 6] input from the transfer unit 72 The logic 5 generates vertical control data having a value of one of the data VLVL <1> and <2> corresponding to the value of the data VGRP [1: 6], and supplies the vertical control data to the ternary decoder 84 and the control signal data generator 36. Output.

In the above description, the case where one vertical control data belongs to only one of the simultaneous toggle group STG and the normal group G is described as a specific example. However, the simultaneous toggle group STG and the normal group G are used together. In addition, the same vertical control data can belong to both the simultaneous toggle group STG and the normal group G.
Thus, in order for the same vertical control data to belong to both the simultaneous toggle group STG and the normal group G, separate data is prepared in the register 34 for the simultaneous toggle group STG and the normal group G. Data may be set and the control signal generator 7 may process them appropriately.

Hereinafter, a setting example for making the same vertical control data belong to both the simultaneous toggle group STG and the normal group G is shown.
(1) The register 34 is provided with registers (5 bits × 26) for the normal group G (V1G [4: 0] to V26G [4: 0]; 5 bits × 26);
(2) Add the following 5 bits x 8 x 8 sets of registers;
STG11 [4: 0] to STG18 [4: 0];
STG21 [4: 0] to STG28 [4: 0];
・
・
STG81 [4: 0] to STG88 [4: 0];

For example, the following settings are made in the register group in the register 34 added in this way.
V1G [4: 0] = 00001 (= G1), V2G [4: 0] = 00001 (= G1);
V3G [4: 0] = 00001 (= G2), V4G [4: 0] = 00010 (= G2);
STG11 [4: 0] = 00001 (= V1), STG12 [4: 0] = 00100 (= V4);
STG21 [4: 0] = 00001 (= V2), STG22 [4: 0] = 00011 (= V3);
Switch command; Corresponding signal 100001 (= G1); V1, V2
100010 (= G2); V3, V4
111000 (= STG1); V1, V4
111001 (= STG2); V2, V3

By configuring the control signal generator 7 as described above, it is possible to provide a control signal generator for a CCD image pickup device suitable for the above-described 2-in-1 type AFE.
As long as there is no contradiction in function or the like, the control signal generator 7 shown as the second embodiment can operate in the same manner as the control signal data generator 3 shown as the first embodiment. Can be similarly modified.

  The present invention can be used to generate an image sensor control signal.

1,6 ... Digital camera,
100: optical system,
102: Image memory,
104... Image processing unit,
106... Recording device,
108... Recording medium,
110 ... UI part,
112 ... V driver,
114... Control unit,
2 CCD image sensor,
204... Vertical CCD cell,
200 ... vertical CCD,
206 ... Horizontal CCD 206,
208... Output amplifier,
3... Control signal data generator,
300 ... Program memory,
302 ... Microcontroller,
34... Register
340... Register ViG,
342... Register ViL,
344: Register STG,
4 ... Instruction code decoder,
40 ... STG decoder,
402, 500... Comparison circuit,
502 ... AND circuit,
406, 54 ... selector,
42, 84... Ternary decoder,
44, 86... Binary decoder,
5 ... Update logic,
50... ID comparison circuit,
500... Comparison circuit,
502 ... AND circuit,
404, 504... OR circuit,
52... Update control unit,
56... Latch circuit,
60... Switching signal generator,
600 ... CPU,
602: Memory,
722... Register,
604 ... H driver,
606... CG (clock generator),
70 ... command generation unit,
72 ... transfer part,
720 ... counter section,
726 ... MUX,
8: Command execution part,

Claims (15)

Image sensor control for generating control signals for the vertical and horizontal directions for a CCD image sensor controlled by a plurality of control signals for the vertical direction in charge transfer and a plurality of control signals for the horizontal direction in charge transfer A signal generator,
An instruction code creating means for creating an instruction code for specifying a group including a plurality of control signals for either the vertical direction or the horizontal direction, and a value of the control signal included in the group;
An image sensor control signal generating device, comprising: control signal generating means for simultaneously generating a control signal of a value specified in the instruction code and included in a group specified in the created instruction code. The instruction code is at least
Group designation information for designating any one of the control signal groups,
Each including value information designating a value of a control signal included in one of the groups of the control signals,
The instruction code creating means includes:
The instruction code including one group designation information and the value information designating a value of a control signal included in a group designated by the group designation information; or each of the plurality of group designation information And creating an instruction code included in association with each of the value information specifying the value of the control signal included in each of the plurality of groups specified by the group specification information,
The image sensor control signal generation device according to claim 1, wherein the control signal generation unit simultaneously generates the control signals included in a group according to the generated instruction code. The image sensor control signal generator according to claim 2, wherein the control signal takes two or three values. The control signal includes a vertical control signal that controls the vertical direction of the array of light receiving elements included in the CCD image sensor, and a horizontal control signal that controls the horizontal direction of the array of light receiving elements included in the CCD image sensor. The image sensor control signal generator according to claim 2 or 3. The image sensor control signal generation device according to claim 2, wherein each of the control signals can be included in a plurality of the groups. The instruction code further includes control signal identification information for identifying any of the group designation information and control signal designation information for designating the control signal,
Group data specifying which group each of the control signals is included is stored in a register in advance.
The group data is
First group data designating which first group each control signal is included in;
Second group data designating control signal designating information corresponding to the control signal contained in each of the second groups, in order to designate which second group each of the control signals is contained in ; Including
When the control signal identification information included in the instruction code takes one of a plurality of predetermined values, the control signal included in the second group data specified by one of the predetermined values Control signal designation information selection means for selecting designation information;
A valid signal indicating that the selected second group data is valid when any of the control signal identification information included in the instruction code takes any of the plurality of predetermined values. Effective signal generating means for generating;
The selected, all of the control signal indicated by the control signal specifying information included in the second group data indicated as the valid, the instruction code to take any of the plurality of predetermined values The image sensor control signal generation device according to claim 2, further comprising: a control signal update unit configured to update to a value indicated by the value information corresponding to the included control signal designation information. Sequentially instruction codes created in the above, accept, an instruction code which the received, at a predetermined timing with respect to the instruction code further includes an operation code output means for outputting the same time,
The image sensor control according to claim 1, wherein the control signal generation unit generates a control signal included in the group corresponding to the simultaneously output instruction code as a value specified by the simultaneously output instruction code. Signal generator. The instruction code output means includes
The image sensor control signal generator according to claim 7, further comprising: a plurality of unit storage units that each store one of the instruction codes and simultaneously output any one of the stored instruction codes at a predetermined timing. The image sensor control signal generating apparatus according to claim 8, wherein at least two of the unit storage units constitute a shift register that shifts the stored instruction code to the unit storage unit in the next stage at each timing. . The image sensor control signal generation device according to claim 7, further comprising clock signal generation means for generating a clock signal for defining the timing. Image sensor control for generating control signals for the vertical and horizontal directions for a CCD image sensor controlled by a plurality of control signals for the vertical direction in charge transfer and a plurality of control signals for the horizontal direction in charge transfer A signal generator,
An instruction code creating means for creating an instruction code for specifying a group including a plurality of control signals for either the vertical direction or the horizontal direction, and a value of the control signal included in the group;
Control signal generating means for simultaneously generating a control signal of a value specified in the instruction code included in the group specified in the generated instruction code, and
An image photographing device for photographing an image by controlling the CCD image sensing device with a control signal generated by the image sensing device control signal generating device. An image sensor for generating a control signal for the vertical direction and the horizontal direction for a CCD image sensor controlled by a plurality of control signals for the vertical direction in charge transfer and a plurality of control signals for the horizontal direction in charge transfer The control signal generator
An instruction code creating step for creating an instruction code for designating a group including a plurality of control signals for either the vertical direction or the horizontal direction, and a value of the control signal included in the group;
A control signal generation step of executing a control signal generation step of simultaneously generating a control signal having a value specified in the instruction code and included in a group specified in the created instruction code. The instruction code is at least
Group designation information for designating any one of the control signal groups,
Each including value information designating a value of a control signal included in one of the groups of the control signals,
The instruction code creating step includes:
The instruction code including one group designation information and the value information designating a value of a control signal included in a group designated by the group designation information; or each of the plurality of group designation information And creating an instruction code that is associated with each of the value information that specifies the value of the control signal included in each of the plurality of groups specified by the group specification information,
The image sensor control signal generation method according to claim 12, wherein the control signal generation step simultaneously generates the control signals included in a group in accordance with the created instruction code. A computer generates a plurality of control signals for the vertical direction in charge transfer and a control signal for the vertical direction and the horizontal direction for a CCD image sensor controlled by a plurality of control signals for the horizontal direction in the charge transfer. In the imaging device control signal generator
An instruction code creating step for creating an instruction code for designating a group including a plurality of control signals for either the vertical direction or the horizontal direction, and a value of the control signal included in the group;
An image sensor control signal generation program that causes the computer to execute a control signal generation step of simultaneously generating a control signal having a value specified in the instruction code and included in a group specified in the created instruction code. The instruction code is at least
Group designation information for designating any one of the control signal groups,
Each including value information designating a value of a control signal included in one of the groups of the control signals,
The instruction code creating step includes:
The instruction code including one group designation information and the value information designating a value of a control signal included in a group designated by the group designation information; or each of the plurality of group designation information , Causing the computer to generate an instruction code that is included in association with each of the value information that specifies the value of the control signal included in each of the plurality of groups specified by the group specification information,
The image sensor control signal generation program according to claim 14, wherein the control signal generation step causes the computer to execute simultaneous generation of the control signals included in a group according to the created instruction code.

Images