CN100384243C - A Static Image Acquisition System for Space Experiment - Google Patents

Abstract

The invention discloses an image acquisition system, in particular to a still image acquisition system for black and white full television signals used in space experiments. The system includes: video input circuit, synchronous separation circuit, A/D conversion circuit, image data memory circuit, acquisition sequence control circuit, transmission control circuit, and central control processing unit. The present invention has the advantages that: the collection process is basically completed by a pure hardware circuit, without the intervention of external signals in the collection process of each frame of image, the pixel row to be collected can be modified by the process of reloading the EEPROM chip code as required, serial number and quantity.

Description

A Static Image Acquisition System for Space Experiment

technical field

The invention relates to an image acquisition system, in particular to a still image acquisition system for black and white full television signals used in space experiments.

Background technique

At present, the most commonly used static image acquisition system in space experiments often requires a specially designed optical system, and is equipped with a suitable photosensitive device (such as CCD) and its controller, and then cooperates with the corresponding A/D conversion circuit and storage circuit. Although this method can ensure high image acquisition accuracy and resolution, the cost of space test equipment is relatively high due to the high specificity of these special optical systems and electronic devices specially used for space tests. In order to reduce costs, in some cases where the requirements for image quality and acquisition frame rate are not high, general-purpose industrial-grade cameras that output full TV signals can be considered instead of specialized imaging devices. Therefore, there is a need for an image acquisition system that can realize the image acquisition function of the space test and has the characteristics of low cost.

Contents of the invention

The purpose of the present invention is to provide a device suitable for space test detection, which converts the full TV signal output by a general black and white TV camera into a digital signal to form a static picture output, and can selectively output some specific line signals according to needs. or column signal static image acquisition system.

In order to achieve the above object, the technical scheme that the present invention takes is as follows:

A static image acquisition system for space experiments provided by the present invention, as shown in Figure 1, includes:

The video input circuit 1 is connected with an external camera (not shown in the figure), and is used to drive and isolate the black and white full TV signal and the basic working clock signal from the camera, divide the basic working clock signal into two, and output the sampling clock signal;

A synchronous separation circuit 2 connected to the video input circuit 1 is used to extract frame, field and line synchronous signals from the full television signal;

The A/D conversion circuit 3 connected with the video input circuit 1 is used to convert the analog TV signal into an 8-bit digital sequence;

The image data storage circuit 4 connected with the A/D conversion circuit 3 is used to provide digital still image data memory and its address selection circuit;

The acquisition timing control circuit 5 connected with the synchronous separation circuit 2 and the image data storage circuit 4 uses the EEPROM chip to store the main timing of static image acquisition, and is used to control the effective time of rows and columns in the process of each frame of image acquisition. The relevant control timing signal of the data transmission cycle;

The transmission control circuit 6 connected to the image data storage circuit 4 and the acquisition timing control circuit 5 is used to generate the relevant control timing signals of the data transmission cycle, and send the collected image data;

The central control processing unit 7 connected to the image data storage circuit 4, the acquisition timing control circuit 5, and the transmission control circuit 6 is used to control the switching of acquisition and transmission cycles.

Described image data storage circuit 4, as shown in Figure 2, comprises a SRAM memory, a 3-state driver, at least two counters, at least two gate circuits; The capacity of the SRAM memory is at least 256K; The two counters , one as a column address counter, the other as a row address counter; the output of the row address counter is connected to the low address of the SRAM memory, and the output of the column address counter is connected to the high address of the SRAM memory for recording row and column data in the memory The address of the two gate circuits, one is an OR gate circuit, and the other is a NOR gate circuit; the switching signal sent by the central processing unit and the acquisition column clock signal output by the acquisition timing control circuit pass the NOR gate output read signal to the SRAM memory; the switch signal sent by the central processing unit and the acquisition column clock signal output by the acquisition timing control circuit output the write signal to the SRAM memory through the OR gate; the 3-state driver is used for the data sent by the A/D conversion circuit 3 and Data port isolation of SRAM memory.

The acquisition timing control circuit 5, as shown in FIG. 3 , includes at least two counters, at least two EEPROM chips, at least two gate circuits and a multiplex 2-to-1 circuit. One of the two counters is used as a column counter, and the other is used as a row counter; the capacity of the EEPROM chip is at least 512 bytes. The column counter is connected with the first EEPROM chip; the row counter is connected with the second EEPROM; the clearing terminal of the column counter is connected with the output terminal of the first EEPROM through the first OR gate circuit to output and collect the column clock signal C_CK_V; the clearing terminal of the row counter is connected with The output terminal of the second EEPROM outputs and collects the row clock signal C_CK_H through the second OR gate circuit; the three-way signal of collecting the column clock signal C_CK_V, collecting the row clock signal C_CK_H, and the row counter clearing terminal signal SYN_F is taken as a group, and the signals from the sending control One group of circuit 6 sends control signals (including sending column clock signals, sending row clock signals, and sending frame end signals) as another group, and these two groups of signals pass through a multi-way 2-to-1 circuit, and the multi-way 2-to-1 The circuit selects the signal output according to the state of the switch signal of the central processing unit 7 .

Compared with the prior art, the present invention has the advantages of:

The acquisition process is basically completed by a pure hardware circuit, and no external signal intervention is required during the acquisition process of each frame of image. In addition, because the EEPROM chip is used in the acquisition timing control circuit to store the row and column acquisition timing of the video signal, it is beneficial to modify the serial number and quantity of the pixel row and column to be acquired through the process of reloading the EEPROM chip code as needed during the design process. .

Description of drawings

Fig. 1 is a composition diagram of the static image acquisition system for space experiment of the present invention;

Fig. 2 is the internal structural block diagram of image data storage circuit 4;

FIG. 3 is a block diagram of the internal structure of the acquisition timing control circuit 5 .

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, the system includes: video input circuit 1, synchronization separation circuit 2, A/D conversion circuit 3,

An image data storage circuit 4 , an acquisition timing control circuit 5 , a transmission control circuit 6 , and a central control processing unit 7 . Each part and its function are introduced as follows:

The video input circuit 1 accepts the full TV signal and the basic working clock signal thereof output by the camera (not shown in the figure); wherein the video signal is driven and isolated by the AD844 (not shown in the figure) of the American AD company, and the output video signal; and The basic working clock signal is divided by two through a D flip-flop, and the sampling clock signal (9.46875MHz) is output.

The core device of sync separation circuit 2 is the RS100A video sync splitter military product chip of American Third Domain Company. The function of the chip is to extract the composite synchronous signal in the full TV signal, and then generate frame synchronous pulse signal SYN_F and horizontal synchronous pulse signal SYN_H through certain logic and sequence circuit combination.

The core device of the A/D conversion circuit 3 is the AD9048 lightning video A/D conversion chip of American AD Company, which uses the clock signal as the sampling clock to convert the video signal into a series of 8-bit digital signals.

The image data storage circuit 4, as shown in Figure 2, comprises an SRAM memory, a 3-state driver, at least two counters, at least two gate circuits; the capacity of the SRAM memory is at least 256K; the two counters, one as A column address counter, and the other is used as a row address counter; the output of the row address counter is connected to the low address of the SRAM memory, and the output of the column address counter is connected to the high address of the SRAM memory for recording the address of the row and column data in the memory; The two gate circuits, one is an OR gate circuit, and the other is a NOR gate circuit; the switching signal sent by the central processing unit and the acquisition column clock signal output by the acquisition timing control circuit pass the NOR gate output read signal to the SRAM memory; The switch signal sent by the central processing unit and the acquisition column clock signal output by the acquisition timing control circuit are outputted by the OR gate to write the signal to the SRAM memory; 54HC244 chip) isolates the data sent by the A/D conversion circuit 3 from the data port of the SRAM. When performing image acquisition, the 3-state driver transmits the data sent by the A/D conversion circuit 3 to the SRAM data port; and after the acquisition cycle is completed, the output of the 3-state driver is set to a high-impedance state. The calibration of the acquisition period is realized by the switch signal output by the central control processing unit 7, and this signal is input to the output enable port of the 3-state driver. When the signal is at low level, it means that in the acquisition period, the output of the 3-state driver is enabled; and when the signal is at high level, the output of the 3-state driver is disabled and is in a high-impedance state. The address selection circuit of the memory is composed of two sets of counters: a column address counter and a row address counter, wherein the clock signal of the column address counter is CK_V, and the reset signal is CK_H; the clock signal of the row address counter is CK_H, and the reset signal is RS_F. The above three signals all come from the acquisition timing control circuit 5 .

The acquisition timing control circuit 5, as shown in FIG. 3 , includes a column counter, a row counter, two EEPROM chips, two OR gate circuits and a multi-channel 2-to-1 circuit. The capacity of the EEPROM chip is at least 512 bytes; the column counter is connected with the first EEPROM chip; the row counter is connected with the second EEPROM; the clearing terminal of the column counter and the output terminal of the first EEPROM output and collect the column clock signal through the first OR gate circuit C_CK_V; the clear terminal of the row counter and the output terminal of the second EEPROM output and collect the row clock signal C_CK_H through the second OR circuit; collect the column clock signal C_CK_V, collect the row clock signal C_CK_H, and the row counter clear terminal signal SYN_F three ways The signal is taken as one group, and one group of sending control signals (including sending column clock signal, sending row clock signal, and sending frame end signal) from sending control circuit 6 is taken as another group, and these two groups of signals pass through a multiplex 2 selection 1 circuit, the multi-way 2 select 1 circuit selects the signal output according to the state of the switch signal of the central processing unit 7 . The column counter takes the sampling clock signal output by the video input circuit 1 as the counting clock, and outputs an address signal of an EEPROM, and the state of the 0th bit ("0" or "1") of the data stored in the EEPROM chip corresponding to this address is captured A column valid is generated at the output after reading. That is to say, when a pixel point needs to be collected in a certain clock cycle, the lowest bit of the data in the EEPROM chip corresponding to the clock cycle should be "0", otherwise it should be "1". This signal and the acquisition clock signal pass through an OR gate to generate the acquisition column clock signal C_CK_V. In addition, the column counter uses the row synchronization signal SYN_H generated by the synchronization separation circuit 2 as a reset signal. The line counter takes the line synchronous signal SYN_H generated by the synchronous separation circuit 2 as the count clock, and outputs the address signal of another EEPROM chip, and the "0" or "1" state of the 0th bit of data corresponding to the address in the EEPROM chip is changed A line valid signal is generated at the output after reading. That is to say, when a certain row of television signals needs to be collected, the lowest bit of the data in the EEPROM chip corresponding to the row should be "0", otherwise it should be "1". This signal and the horizontal synchronous signal SYN_H pass through the OR gate to generate a collection horizontal clock signal C_CK_H. In addition, the line counter uses the frame synchronization signal SYN_F generated by the synchronization separation circuit 2 as a reset signal.

In addition, the acquisition timing control circuit 5 should not only finally generate the timing control during image acquisition, but also consider the timing control during image data transmission. The method is to use the three-way signal of collecting the column clock signal C_CK_V, collecting the row clock signal C_CK_H, and the row counter clearing terminal signal SYN_F as a group of inputs, and using a group of sending control signals from the sending control circuit 6 (including sending the column clock signal T_CK_V, Send the line clock signal T_CK_H, and send the frame end signal T_RS_F three-way signal) as another set of inputs, through a multiplex 2-to-1 circuit. The multi-channel 2-to-1 circuit uses the switch signal from the central control processing unit 7 as the selection signal, and when the switch signal is at low level, it outputs the timing control signal of the acquisition cycle, otherwise it outputs the timing control signal of the sending cycle. There are 3 channels of output timing control signals including column clock signal CK_V, row clock signal CK_H and frame reset signal RS_F.

The function of the sending control circuit 6 is to generate a set of sending control signals required in the digital image data sending process, including sending a column clock signal, sending a row clock signal and sending a frame end signal. Due to the different specific application conditions of various systems, no corresponding regulations are made for the specific implementation of this part of the circuit in the present invention, and the specific circuit can be designed according to actual needs. For example, the data management system of a spacecraft can read digital image data by sending a strobe signal and a serial transmission clock signal to the device designed in the present invention. When a frame of static image is collected, it is counted by the serial transmission clock to generate the sending column clock signal, sending row clock signal and frame end signal. During this period, the central control unit 7 may also send the image to this unit at an appropriate time. Packet header and packet number information of data packaging, this unit drives and transmits the packet header, packet sequence number and image data through the serial transmission clock through the parallel/serial conversion circuit; during each frame of static image acquisition, it is sent by the central control processing unit 7 The data is filled and transmitted externally by the serial transmission clock signal through this unit.

The main function of the central control processing unit 7 is to control the switching of the acquisition and transmission cycles, and in the actual application of the space test, there is also a packaging process for data transmission. In the present invention, this part of the circuit is not specially regulated, and can be designed according to actual conditions. . This part of the circuit judges whether the acquisition process is completed according to the frame synchronization signal SYN_F generated by the synchronization separation circuit 2, and sets the switch signal to low level during the acquisition process, and sets the switch signal to high level after the acquisition process ends.

According to the above, the process of image acquisition and transmission in this system can be described as follows:

As shown in Figure 1, firstly, the full TV signal and its working clock are input into the system through the video input circuit 1, and the basic working clock signal is divided by two to output the acquisition clock signal, and the video signal is driven and isolated by the AD844 of the American AD company. Output video signal. This video signal is sent to the A/D conversion circuit 3 and the sync separation circuit 2 . In the synchronization separation circuit 2, the frame and line synchronization signals (SYN_F, SYN_H) of the full TV video signal are extracted and sent to the acquisition timing control circuit 5, while the frame synchronization signal SYN_F is sent to the central control processing unit 7. The central control processing unit 7 decides to start collecting a frame of image according to the received frame synchronization signal SYN_F, then sets the switch signal to low level, and sends this signal to the collection timing control circuit 5 and the image data storage circuit 4 . At this time, the A/D conversion circuit 3 is converting the full TV signal into a series of 8-bit digital quantities with the basic working clock signal of the video camera divided by two as the sampling clock signal, and sending it to the image data storage circuit 4 . The image data storage circuit 4 stores a series of 8-bit digital quantities in the SRAM according to the row and column clock signals (CK_H, CK_V) sent by the acquisition timing control circuit 5 . When the central control processing unit 7 receives the next frame synchronization signal (SYN_F), it means that a frame of image data has been collected, so the switch signal is set to high level, and the system enters the sending cycle, and at this time the A/D conversion circuit The 8-bit digital quantity generated by 3 is isolated from the SRAM memory data port by the 3-state driver in the image data storage circuit 4, and the row and column clock signals and frame synchronization signals (CK_H, CK_V and SYN_F) generated by the acquisition timing control circuit 5 are collected. Converted to the corresponding sending control signal generated by the sending control circuit 6, which has nothing to do with the video signal. After the transmission control circuit 6 takes out all the frame image data stored in the SRAM memory in the image data storage circuit 4, the central control processing unit 7 will set the switch signal to low level again according to the transmission frame end signal, and the system will re-enter the acquisition process. cycle, and iteratively.

Claims (6)

1. static image collection system that is used for space test comprises:

Video input circuit is used to drive and isolates from the composite video signal of external camera and with groundwork clock signal two divided-frequency, the output sampled clock signal;

The A/D change-over circuit that is connected with video input circuit is used for vision signal is converted to 8 digital bit amount sequences;

The image data storage circuit that is connected with the A/D change-over circuit is used to provide digitized static image data memory and addressing circuit thereof;

Central authorities' controlled processing unit, control each several part circuit working and the control collection and the switching in the cycle of transmission;

It is characterized in that, also comprise:

The synchronizing separator circuit that is connected with video input circuit is used for extracting frame, field, line synchronizing signal from composite video signal;

The collection sequential control circuit that is connected with synchronizing separator circuit, image data storage circuit, store with the main sequential of memory the still image collection, be used for controlling each image frame grabber process row, column effective time, also transmit the relevant control timing signal of data transmitting period in addition;

With the sending controling circuit that image data storage circuit, collection sequential control circuit are connected, be used to produce the relevant control timing signal of data transmitting period, the view data that collection is finished sends.

2. the static image collection system that is used for space test according to claim 1 is characterized in that, described collection sequential control circuit comprises that at least two counters, at least two eeprom chips, at least two gate circuits and a multichannel 2 select 1 circuit; Described two counters, one as column counter, and another is as linage-counter; Capacity at least 512 bytes of described eeprom chip; Column counter is connected with first eeprom chip; Linage-counter is connected with the 2nd EEPROM; The clock control end of column counter and the output of first eeprom chip are gathered the column clock signal by the output of first OR circuit; The output of the clear terminal of column counter and the 2nd EEPROM is gathered the row clock signal by the output of second OR circuit; The column clock signal be will gather, row clock signal, linage-counter clear terminal signal three road signals gathered as one group, to transmit control signal from one group that sends control circuit and (comprise and send the column clock signal, send the row clock signal, and transmit frame end signal) as another group, these two groups of signals select 1 circuit by a multichannel 2, and this multichannel 2 selects the state of the switching signal that 1 circuit sends according to central processor unit to select signal output.

3. the static image collection system that is used for space test according to claim 1 is characterized in that, described image data storage circuit comprises a SRAM memory, one 3 attitude drivers, at least two counters, at least two gate circuits; The capacity of described SRAM memory is 256K at least; Described two counters, one as column address counter, and another is as line address counter; The output of line address counter is connected with the low address of SRAM memory, and the output of column address counter is connected with the high address of SRAM memory, is used for writing down the address of row, column data at memory; Described two gate circuits, one is OR circuit, another is an OR-NOT circuit; The collection column clock signal of switching signal that central processing unit sends and the output of collection sequential control circuit is given the SRAM memory by NOR gate output read signal; The collection column clock signal of switching signal that central processing unit sends and the output of collection sequential control circuit passes through or door is exported a write signal to the SRAM memory; Described 3 attitude drivers are used for the data port of data that the A/D change-over circuit is sent and SRAM memory and isolate.

4. the static image collection system that is used for space test according to claim 1, it is characterized in that, the groundwork clock signal that comprises video camera in the described video input circuit, frequency is 18.9375MHz, through behind the two divided-frequency as the sampled clock signal of A/D change-over circuit, the capable valid period of 52 microseconds of each in composite video signal, can gather 492 effective picture elements at most.

5. the static image collection system that is used for space test according to claim 1, it is characterized in that, described synchronizing separator circuit, RS100A sync separator military products chip with Third Domain company is a core, after this chip extracts the composite synchronizing signal in the composite video signal, from composite synchronizing signal, isolate line synchronizing signal and frame synchronizing signal.

6. the static image collection system that is used for space test according to claim 1, it is characterized in that, described A/D change-over circuit, the lightening video a/d conversion chip of AD9048 with U.S. AD company is a core, sampled clock signal is the two divided-frequency of the groundwork clock signal of video camera, and frequency is 9.46875MHz.

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