JP4659244B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device that performs a test by a scan method.
[Prior art]
In a system LSI on which a semiconductor memory device and a controller are mounted, writing of addresses and data to the semiconductor memory device is performed from a controller or the like provided in the same system LSI. Therefore, it is not necessary to input addresses and data directly from the outside of the system LSI to the semiconductor memory device in normal operation, and no external terminals for direct input are provided. However, in order to test the semiconductor memory device, it is necessary to input the address and data to the semiconductor memory device from outside the system LSI and check the output data. In order to realize this, a scanning method is used in which addresses and data are serially input from a single terminal during a test operation.
[0002]
In the scan method, it is not necessary to provide a large number of external terminals for addresses and data as system LSI external terminals, and it is only necessary to provide a single terminal for scan input, so that the number of pins can be reduced.
[0003]
FIG. 1 is a diagram showing a configuration of a conventional semiconductor memory device using a scanning method.
[0004]
The semiconductor memory device of FIG. 1 includes a semiconductor memory device body 11 such as an SRAM (Static Random Access Memory), and a flip-flop 12-0 for scan input for t input address signals IA [0] to IA [t-1]. Through 12-t-1, flip-flops 13-0 through 13-b-1, and b output data signals A [0] for the b input data signals I [0] through I [b-1]. ] To A [b-1] scan output flip-flops 14-0 to 14-b-1, a plurality of selector circuits 15, an XOR circuit 16, an NXOR circuit 17 which is an inversion of XOR, AND circuits 18 and 19, And an output buffer 20.
[0005]
During normal operation, the selection signal MST is LOW (“0”), and each selector circuit 15 receives input address signals IA [0] to IA [t−1] and input data input in parallel from the outside of the semiconductor memory device 10. The signals I [0] to I [b-1] are selected. The selected input signal is supplied to the semiconductor memory device body 11. During normal operation, the scan mode signal SM is also LOW, and the NXOR circuit 17 supplies a HIGH signal to the AND circuit 19. Accordingly, the input clock signal CK is supplied to the semiconductor memory device body 11 via the AND circuit 19. Output data of the semiconductor memory device body 11 is supplied to the outside of the semiconductor memory device 10 as output data signals A [0] to A [b-1].
[0006]
During the test operation, the scan mode signal SM instructing the scan mode is set to HIGH, and setting data is input from the test input terminal TSI in synchronization with the input clock signal CK. At this time, the selection signal MST is set to LOW. Therefore, the output of the XOR circuit 16 is HIGH, and the input clock signal CK is supplied to each flip-flop via the AND circuit 18. Each flip-flop is connected in series so that the serial output SO of the previous stage is connected to the serial input SI of the next stage, and the setting data input from the test input terminal TSI is shifted by a shift operation synchronized with the clock signal CK. Data shift is repeated, and finally predetermined data can be set in each flip-flop.
[0007]
When the predetermined data is set in each flip-flop, the selector signal 15 selects the Q output of the corresponding flip-flop and supplies it to the semiconductor memory device body 11 by setting the selection signal MST to HIGH. At this time, the scan mode signal SM remains HIGH, and the NXOR circuit 17 supplies the HIGH signal to the AND circuit 19. Accordingly, the input clock signal CK is supplied to the semiconductor memory device body 11 via the AND circuit 19. As a result, an address input (read operation) or an address and data input (write operation) to the semiconductor memory device body 11 is performed. At this time, the output of the XOR circuit 16 becomes LOW, and the input clock signal CK is not supplied to the flip-flop. Accordingly, the scan operation (shift operation) of the flip-flop is not executed at this timing.
[0008]
Output data signals A [0] to A [b-1] output from the semiconductor memory device body 11 by the read operation are stored in parallel in the scan output flip-flops 14-0 to 14-b-1. Thereafter, the data of the flip-flops 14-0 to 14-b-1 is shifted by the clock signal CK, so that the output data signals A [0] to A [b-1] are sequentially output from the output terminal TSO.
[Problems to be solved by the invention]
In the semiconductor memory device as described above, in order to set data in the test operation, it is necessary to execute the scan shift operation by the number of input flip-flops. That is, the number of scan shift operations is the number of addresses + the number of write data.
[0009]
For example, taking an SRAM of 1024 words and 72 bits as an example, the number of scan shifts required for one writing is 10 (= log ₂ 1024) 82 times with +72 bits.
[0010]
The number of scan shifts is further increased in a semiconductor memory device provided with a partial write function.
[0011]
FIG. 2 is a diagram showing a configuration of a conventional semiconductor memory device with a partial write function using a scanning method. 2, the same elements as those in FIG. 1 are referred to by the same reference numerals, and the description thereof will be omitted.
[0012]
The semiconductor memory device 10A with a partial write function in FIG. 2 includes, in addition to the elements in FIG. 1, a flip-flop 21- for scan input for b partial write enable input signals VI [0] to VI [b-1]. 0 to 21-b-1 are provided. For the partial write enable input signals VI [0] to VI [b-1], the input data signals I [0] to I [b-1] corresponding to the bits set to "0" are valid. Thus, for a bit set to “1”, the corresponding input data signals I [0] to I [b−1] are invalid. Therefore, for example, when the partial write enable input signal is set to “00001111” for an 8-bit data input, only the data of I [0] to I [3] is taken into the semiconductor memory device body 11. It has become. Such a function enables partial data input.
[0013]
In the semiconductor memory device with partial write function 10A in FIG. 2, the number of scan shift operations is the number of addresses + the number of write data + the number of partial write enable. For example, taking an SRAM of 1024 words and 72 bits as an example, the number of scan shifts required for one writing is 10 (= log ₂ 1024) It is 154 times of +72 bits + 72 bits.
[0014]
If the test is performed with a march pattern that is all “0” or all “1”, it is necessary to perform data setting by scan shift 10 × 1024 times. The semiconductor memory device 10 in FIG. 1 requires 10 × 1024 × 82 scan shifts, and the semiconductor memory device 10A with the partial write function in FIG. 2 requires 10 × 1024 × 154 scan shifts. End up. As described above, the conventional scan-type semiconductor memory device has a problem that the number of scan shift operations during the test is enormous and the test time becomes long.
[0015]
In view of the above, an object of the present invention is to provide a scan-type semiconductor memory device capable of setting data with a relatively small number of scan shifts.
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a semiconductor memory device main body that receives an n-bit address signal and an m-bit data signal larger than 2, n scan flip-flops connected in series to each other, and setting the address signal serially. Two scan flip-flops connected in series with each other to serially set the data signal And the m-bit output data read from the semiconductor memory device main body and the m-bit expected value data configured by repeating the 2-bit expected value data, the output data becomes the expected value. A comparison circuit for determining whether or not the data matches And repeating the data of the two scan flip-flops to form m-bit data and inputting it to the semiconductor memory device body.
[0016]
In the above invention, Two Since m-bit data is formed by repeating the data of the scan flip-flop, there is no need to provide m scan flip-flops and execute m scan shift operations, and the input data can be scanned less than m times. Can be set. This makes it possible to reduce the number of scan shifts required for data setting for the scan flip-flop.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0017]
FIG. 3 is a block diagram showing a first embodiment of the semiconductor memory device according to the present invention.
[0018]
The semiconductor memory device 30 of FIG. 3 includes a semiconductor memory device body 31 such as an SRAM, and flip-flops 32-0 to 32-t- for scan input for t input address signals IA [0] to IA [t-1]. , Two scan input flip-flops 33-0 and 33-1, provided for a plurality of input data signals I [0], I [1], I [2],. Flip-flops 34-0 to 34-b-1 for scan output with respect to the output data signals A [0] to A [b-1], a plurality of selector circuits 35, an XOR circuit 36, an NXOR circuit 37 that is an inversion of XOR, AND circuits 38 and 39 and an output buffer 40 are included.
[0019]
During normal operation, the selection signal MST is LOW (“0”), and each selector circuit 35 receives input address signals IA [0] to IA [t−1] and input data input in parallel from the outside of the semiconductor memory device 30. The signals I [0], I [1], I [2],. The selected input signal is supplied to the semiconductor memory device body 31. In normal operation, the scan mode signal SM is also LOW, and the NXOR circuit 37 supplies a HIGH signal to the AND circuit 39. Therefore, the input clock signal CK is supplied to the semiconductor memory device body 31 via the AND circuit 39. Output data of the semiconductor memory device body 31 is supplied to the outside of the semiconductor memory device 30 as output data signals A [0] to A [b-1].
[0020]
During the test operation, the scan mode signal SM instructing the scan mode is set to HIGH, and setting data is input from the test input terminal TSI in synchronization with the input clock signal CK. At this time, the selection signal MST is set to LOW. Therefore, the output of the XOR circuit 36 is HIGH, and the input clock signal CK is supplied to each flip-flop via the AND circuit 38. Each flip-flop is connected in series so that the serial output SO of the previous stage is connected to the serial input SI of the next stage, and the setting data input from the test input terminal TSI is shifted by a shift operation synchronized with the clock signal CK. Data shift is repeated, and finally predetermined data can be set in each flip-flop.
[0021]
Here, for the plurality of input data signals I [0], I [1], I [2],..., Two scan input flip-flops 33-0 and 33-1 are provided. ing. The data pattern actually used in the test of the semiconductor memory device is a march pattern in which all bits are “0” or all bits are “1”, or a bit pattern in which “0” and “1” are alternately repeated. There is almost no checker pattern, and there is virtually no need to use other data patterns. Therefore, if two flip-flops 33-0 and 33-1 are provided for data pattern setting, an arbitrary march pattern or checker pattern can be set by repeating the data of the two flip-flops. I can do it.
[0022]
In the semiconductor memory device 30 of FIG. 3, the Q outputs of the two flip-flops 33-0 and 33-1 are alternately supplied to the semiconductor memory device body 31. That is, the Q output of the flip-flop 33-0 is supplied to the selector circuit 35 corresponding to the even-numbered input data signals I [0], I [2], I [4],. The Q output of 1 is supplied to the selector circuit 35 corresponding to the odd-numbered input data signals I [1], I [3], I [5],.
[0023]
Accordingly, if “0” is stored in the flip-flops 33-0 and 33-1, a march pattern in which all bits are “0” can be configured, and “1” is stored in the flip-flops 33-0 and 33-1. Can store a march pattern in which all bits are “1”. Furthermore, if “0” and “1” are stored in the flip-flops 33-0 and 33-1, respectively, a checker pattern of “010101...” Can be configured, and the flip-flops 33-0 and 33- If “1” and “0” are stored in 1 respectively, a checker pattern “101010...” Can be configured.
[0024]
When the predetermined data has been set in each flip-flop, the selector signal 35 selects the Q output of the corresponding flip-flop and supplies it to the semiconductor memory device body 31 by setting the selection signal MST to HIGH. At this time, the scan mode signal SM remains HIGH, and the NXOR circuit 37 supplies the HIGH signal to the AND circuit 39. Therefore, the input clock signal CK is supplied to the semiconductor memory device body 31 via the AND circuit 39. Thus, address input (read operation) or address and data input (write operation) is performed on the semiconductor memory device body 31. At this time, the output of the XOR circuit 36 becomes LOW, and the input clock signal CK is not supplied to the flip-flop. Accordingly, the scan operation (shift operation) of the flip-flop is not executed at this timing.
[0025]
Output data signals A [0] to A [b-1] output from the semiconductor memory device body 31 by the read operation are stored in parallel in the scan output flip-flops 34-0 to 34-b-1. Thereafter, the data of the flip-flops 34-0 to 34-b-1 is shifted by the clock signal CK, so that the output data signals A [0] to A [b-1] are sequentially output from the output terminal TSO.
[0026]
As described above, in the first embodiment of the semiconductor memory device according to the present invention shown in FIG. 3, by providing only two scan flip-flops for the input data signal, data setting for the scan flip-flops is performed. It becomes possible to reduce the number of scan shifts required. That is, since the number of scan shift operations is the number of addresses + the number of write data, for example, in the case of an SRAM of 1024 words and 72 bits, the number of scan shifts required for one write is 10 (= log ₂ 1024) 12 times with +2 bits.
[0027]
FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention.
[0028]
The second embodiment relates to a semiconductor memory device with a partial write function. 4, the same elements as those of FIG. 3 are referred to by the same reference numerals, and a description thereof will be omitted.
[0029]
The semiconductor memory device 30A with a partial write function shown in FIG. 4 responds to a plurality of partial write enable input signals VI [0], VI [1], VI [2],. Two scan input flip-flops 41-0 and 41-1 are provided. The Q outputs of these two flip-flops 41-0 and 41-1 are alternately supplied to the semiconductor memory device body 31. That is, the Q output of the flip-flop 41-0 is supplied to the selector circuit 35 corresponding to the even-numbered partial write enable input signals VI [0], VI [2], VI [4],. The Q output of 41-1 is supplied to the selector circuit 35 corresponding to the odd-numbered partial write enable input signals VI [1], VI [3], VI [5],.
[0030]
Therefore, in the semiconductor memory device 30A of FIG. 4, an arbitrary march pattern or checker pattern can be set as in the semiconductor memory device 30 of FIG.
[0031]
FIG. 5 is a block diagram showing a third embodiment of the semiconductor memory device according to the present invention. In FIG. 5, the same elements as those of FIG. 3 are referred to by the same reference numerals, and a description thereof will be omitted.
[0032]
The third embodiment relates to a configuration in which the number of scan flip-flops for output data is reduced.
[0033]
In the first and second embodiments, the number of flip-flops provided for the input data and the partial write enable input is reduced to two, thereby greatly reducing the number of scan shift operations in the input setting. I can do it. However, in an actual test, after data is written, the data is read to determine whether the semiconductor memory device body operates normally. In order to read data in the scan operation, it is necessary to repeat the scan shift by the number of bits of the data output. For example, in the case of 72-bit output, 72 scan shifts are required.
[0034]
The scan read operation from the output flip-flop is executed simultaneously with the scan write operation to the input flip-flop, thereby performing efficient data reading and writing. Therefore, for example, the number of scan shifts required for writing in the semiconductor memory device 30 of FIG. 3 is 12 times (= log ₂ Even if it is 1024 + 2), when 72 scan shifts are required for output, 72 scan shifts are required when reading and writing are performed simultaneously. On the other hand, in the conventional configuration of the semiconductor memory device 10 of FIG. 1, the number of scan shifts required for writing is 82 times (= log ₂ 1024 + 72), if read / write is executed simultaneously, 82 scan shifts are required. Therefore, in the semiconductor memory device 30 of FIG. 3, the number of scan shifts can be reduced, but the actual reduction efficiency is not so high.
[0035]
The semiconductor memory device 30B of FIG. 5 is different from the semiconductor memory device 30 of FIG. 3 in the data output part, and the comparison circuit 51, the output data expected value storage flip-flops 52-0 and 52-1, and the comparison circuit 51 compare. A flip-flop 53 for outputting the determination result is included.
[0036]
As described above, the data pattern actually used in the test of the semiconductor memory device is a march pattern in which all bits are “0” or all bits are “1”, or “0” and “1” are alternately repeated. Most of the checker patterns are bit patterns, and there is virtually no need to use other data patterns. Therefore, in the semiconductor memory device of the present invention, two flip-flops are provided for the input data, and an arbitrary march pattern or checker pattern is realized by repeating this 2-bit pattern. When these march patterns or checker patterns are used, the expected value pattern of output data read from the semiconductor memory device body 31 is the same pattern as the march pattern or checker pattern used for input. That is, the expected value data pattern of the output data is a march pattern in which all bits are “0” or all bits are “1”, or a checker pattern in which “0” and “1” are alternately repeated.
[0037]
In the semiconductor memory device 30B of FIG. 5 according to the third embodiment, the two-bit expected value is obtained by the scan shift operation for the two flip-flops 52-0 and 52-1 provided for storing the output data expected value. Store the data. Then, by repeating the 2-bit pattern of these flip-flops 52-0 and 52-1, an expected value bit pattern equal to the number of output bits is created. The 2-bit expected value data may be the same as the data stored in the two scan input flip-flops 33-0 and 33-1.
[0038]
Specifically, the data of these two flip-flops 52-0 and 52-1 is supplied to the comparison circuit 51. The comparison circuit 51 includes a pattern in which 2-bit data of the flip-flops 52-0 and 52-1 are repeated, and a bit pattern of output data signals A [0] to A [b-1] read from the semiconductor memory device body 31. Are compared with each other to determine whether or not both bit patterns match. If the two match, for example, “0” is written to the D input of the flip-flop 53 and output from the output terminal TSO to the outside of the semiconductor memory device. If the bit patterns do not match, for example, “1” is written to the D input of the flip-flop 53 and output from the output terminal TSO to the outside of the semiconductor memory device.
[0039]
As described above, in the semiconductor memory device 30B according to the third embodiment of the present invention, the two flip-flops 52-0 and 52-1 are provided to store the 2-bit expected value data, and the comparison circuit 51 generates the 2-bit data. This expected value data is repeated to create an expected value bit pattern equal to the number of output bits, and this is compared with the actual output data to determine whether or not the expected value is met. Therefore, unlike the conventional configuration, it is not necessary to perform the scan shift operation equal to the number of output bits at least, and the number of scan shifts can be greatly reduced.
[0040]
That is, since the number of scan shift operations is basically the number of addresses + the number of write data + the number of expected value storage bits, for example, a 1024-word 72-bit SRAM is taken as an example, the scan shift required for one write operation Is 10 (= log ₂ 1024) +2 bits + 2 bits, 14 times. Further, since only the 1-bit determination result is read for the scan read operation, only 14 scan shifts need be executed when the read and write operations are performed simultaneously.
[0041]
Needless to say, the configuration of FIG. 5 can also be applied to the semiconductor memory device with a partial write function of FIG. In this case, since the number of scan shift operations is basically the number of addresses + the number of write data + the number of partial write enable writes + the number of expected value storage bits, for example, a 1024 word 72-bit SRAM is taken as an example. The number of scan shifts required for one writing is 10 (= log ₂ 1024) +2 bits + 2 bits + 2 bits is 16 times, and even when reading and writing operations are performed simultaneously, it is only necessary to perform 16 scan shifts.
[0042]
FIG. 6 is a circuit diagram showing the configuration of comparison circuit 51 in FIG. 5 together with the portion related to data output of the semiconductor memory device.
[0043]
The comparison circuit 51 includes AND circuits 61 to 64, OR circuits 65 to 68, XOR circuits 69 to 76, and OR circuits 77 to 83. The Q output of the flip-flop 52-0 that stores even bits of the expected value is input to the XOR circuits 71 and 72 and 75 and 76. The Q output of the flip-flop 52-1, which stores odd bits of the expected value, is input to the XOR circuits 69 and 70 and 73 and 74.
[0044]
For example, the AND circuit 64 takes an AND of the output data A [0] and A [2], so that the output becomes HIGH only when both are “1”. Further, since the OR circuit 68 takes OR of the output data A [0] and A [2], the output becomes HIGH when at least one of them is “1”.
[0045]
Regardless of whether the expected value even bit stored in the flip-flop 52-0 is "0" or "1", the output of the AND circuit 64 and the expected value even bit in the case of output data as expected The output of the XOR circuit 75 that takes the XOR of and becomes the LOW, and the output of the XOR circuit 76 that takes the XOR of the output of the OR circuit 68 and the even bit of the expected value also becomes LOW. Therefore, the output of the OR circuit 80 is LOW. The output data A [0] and A [2] are the same regardless of whether the expected value even number bit stored in the flip-flop 52-0 is "0" or "1". Is different from, the output of the XOR circuit 75 that XORs the output of the AND circuit 64 and the expected value even bit is HIGH, and further the XOR circuit 76 that XORs the output of the OR circuit 68 and the expected value even bit Output is also HIGH. Accordingly, the output of the OR circuit 80 becomes HIGH.
[0046]
If the output data A [0] and A [2] are different from each other, it is neither a march pattern nor a checker pattern, and the output is incorrect. In this case, the output of the AND circuit 64 becomes LOW, and the output of the OR circuit 68 becomes HIGH. Therefore, regardless of the value of the even bit of the expected value, one of the XOR circuits 75 and 76 becomes HIGH and the other becomes LOW. Accordingly, the output of the OR circuit 80 becomes HIGH.
[0047]
That is, when the output data A [0] and A [2] are as expected values, the output of the OR circuit 80 is LOW, and when the output data A [0] and A [2] are different from the expected values, the output of the OR circuit 80 is HIGH. Similar logic is determined for each output bit and integrated by OR circuits 81-83. As a result, the output of the OR circuit 83 is LOW when all the output data is as expected, and HIGH when it is different from the expected value.
[0048]
In this manner, the comparison circuit 51 shown in FIG. 6 can determine whether or not the output data is as expected, and can output the determination result as 1-bit data.
[0049]
FIG. 7 is a diagram showing the timing of the write operation in the semiconductor memory device according to the present invention.
[0050]
7A shows the selection signal MST, FIG. 7B shows the scan mode signal SM, FIG. 7C shows the write enable signal TWE, FIG. 7D shows the scan input data TSI, FIG. 7E shows the clock signal CK, and FIG. Signals A [n] and (g) are the output data signal TSO.
[0051]
First, the scan mode signal SM is set to HIGH, and the operation mode is set to the scan mode. Thereafter, the scan input data TSI is serially input in synchronization with the clock signal CK. Here, the scan input data TSI is serial data including at least a write address and write data. When the capture of all the scan input data TSI is completed, the selection signal MST is set to HIGH, the write enable signal TWE is enabled (LOW), and the Q output (write address and write data) of each flip-flop is set to the clock signal CK. Synchronized and supplied to the semiconductor memory device body. At this time, as described above with reference to FIG. 3, the scan mode signal SM remains HIGH, and the scan shift operation of the flip-flop is not executed. Writing data to the semiconductor memory device body without a scan shift operation in this way is called a non-scan shift write operation.
[0052]
As a result, the data write operation to the semiconductor memory device body is completed.
[0053]
FIG. 8 is a diagram showing the timing of the read operation in the semiconductor memory device according to the present invention.
[0054]
8A shows the selection signal MST, FIG. 8B shows the scan mode signal SM, FIG. 8C shows the write enable signal TWE, FIG. 8D shows the scan input data TSI, FIG. 8E shows the clock signal CK, and FIG. Signals A [n] and (g) are the output data signal TSO.
[0055]
First, the scan mode signal SM is set to HIGH, and the operation mode is set to the scan mode. Thereafter, the scan input data TSI is serially input in synchronization with the clock signal CK. Here, the scan input data TSI is serial data including at least a read address. When the capture of all the scan input data TSI is completed, the write enable signal TWE remains disabled (HIGH), the selection signal MST is set HIGH, and the Q output (read address) of each flip-flop is synchronized with the clock signal CK. Supplied to the semiconductor memory device body. At this time, the scan mode signal SM remains HIGH, and the scan shift operation of the flip-flop is not executed.
[0056]
As a result, a data read operation for the semiconductor memory device body is executed.
Reading data from the semiconductor memory device body without a scan shift operation in this way is called a non-scan shift read operation.
[0057]
Further, the scan mode signal SM is set to LOW while the selection signal MST remains HIGH, and the clock pulse of the clock signal CK is input. Thereby, the data output from the semiconductor memory device main body is stored from the D input in the flip-flops 34-0 to 34-b-1, for example, in the configuration of FIG. For example, in the configuration of FIG. 5, 1-bit data indicating whether or not the read data is as expected is stored in the flip-flop 53 from the D input.
[0058]
As a result, the data read operation from the semiconductor memory device body is completed.
[0059]
FIG. 9 is a diagram showing timings of read and write operations in the semiconductor memory device according to the present invention.
[0060]
9A shows the selection signal MST, FIG. 9B shows the scan mode signal SM, FIG. 9C shows the write enable signal TWE, FIG. 9D shows the scan input data TSI, FIG. 9E shows the clock signal CK, and FIG. Signals A [n] and (g) are the output data signal TSO.
[0061]
First, the scan mode signal SM is set to HIGH, and the operation mode is set to the scan mode. Thereafter, the scan input data TSI is serially input in synchronization with the clock signal CK. Here, the scan input data TSI is serial data including at least an address that is a target of a read operation and at the same time a target of a write operation, and write data. When the capture of all the scan input data TSI is completed, the selection signal MST is set to HIGH while the write enable signal TWE is disabled (HIGH), and the Q output (read address) of each flip-flop is synchronized with the clock signal CK. Supplied to the semiconductor memory device body. At this time, the scan mode signal SM remains HIGH, and the scan shift operation of the flip-flop is not executed.
[0062]
As a result, a data read operation for the semiconductor memory device body is executed.
[0063]
Thereafter, the write enable signal TWE is enabled (LOW), and the Q outputs (write address and write data) of each flip-flop are supplied to the semiconductor memory device body in synchronization with the clock signal CK. At this time, the scan shift operation of the flip-flop is not executed.
[0064]
Further, the scan mode signal SM is set to LOW while the selection signal MST remains HIGH, and the clock pulse of the clock signal CK is input. Thereby, the data output from the semiconductor memory device main body is stored from the D input in the flip-flops 34-0 to 34-b-1, for example, in the configuration of FIG. For example, in the configuration of FIG. 5, 1-bit data indicating whether or not the read data is as expected is stored in the flip-flop 53 from the D input.
[0065]
Thus, the operation of reading data from the designated address of the semiconductor memory device body and the operation of writing new data to the designated address are completed.
[0066]
FIG. 10 is a flowchart showing a process for testing the semiconductor memory device of the present invention using a march pattern.
[0067]
In step S1, the input address is set to address 0. In step S2, scan data is input by a scan shift operation. In step S3, a non-scan shift write operation is executed to write scan data consisting of a column “0”. In step S4, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S2. If it is the last address, the process proceeds to step S5.
[0068]
In step S5, the input address is set to address 0. In step S6, scan data is input by a scan shift operation. In step S7, a non-scan shift read operation is executed to read data consisting of the column “0” written in step S3. In step S8, a non-scan shift write operation is executed to write scan data consisting of the column “1”. In step S9, data is stored in an output flip-flop. In step S10, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S6. If it is the last address, the process proceeds to step S11.
[0069]
In step S11, the input address is set as the final address. In step S12, scan data is input by a scan shift operation. In step S13, a non-scan shift read operation is executed to read data consisting of the column “1” written in step S8. In step S14, a non-scan shift write operation is executed to write scan data consisting of a column “0”. In step S15, the data is stored in the output flip-flop. In step S16, it is determined whether or not the input address is address 0. If the address is not 0, the input address is decremented by 1 and the process returns to step S12. If the address is 0, the process proceeds to step S17.
[0070]
In step S17, the input address is set to address 0. In step S18, scan data is input by a scan shift operation. In step S19, a non-scan shift write operation is executed to write scan data consisting of the column “1”. In step S20, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S18. If it is the last address, the process proceeds to step S21.
[0071]
In step S21, the input address is set to address 0. In step S22, scan data is input by a scan shift operation. In step S23, a non-scan shift read operation is executed to read data consisting of the column “1” written in step S19. In step S24, a non-scan shift write operation is executed to write scan data consisting of a column “0”. In step S25, data is stored in the output flip-flop. In step S26, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1 and the process returns to step S22. If it is the last address, the process proceeds to step S27.
[0072]
In step S27, the input address is set as the final address. In step S28, scan data is input by a scan shift operation. In step S29, a non-scan shift read operation is executed to read data consisting of the column “0” written in step S24. In step S30, a non-scan shift write operation is executed to write scan data consisting of the column “1”. In step S31, data is stored in an output flip-flop. In step S32, it is determined whether or not the input address is address 0. If the address is not 0, the input address is decremented by 1 and the process returns to step S28. If the address is 0, the process proceeds to step S33. Finally, in step S33, scan shift is executed to output data serially from the output flip-flop.
[0073]
As described above, when a march pattern is used, the column “0” is usually written, the column “0” is read, the column “1” is written, the column “1” is read, and “ Write column “0”, write column “1”, read column “1”, write column “0”, read column “0” and write column “1” . This operation is executed for all addresses. As described above, the scan shift operation simultaneously performs the operation of setting the input scan data in the input flip-flop and the operation of reading the output data from the output flip-flop.
[0074]
After executing the test using the march pattern as described above, after writing the column of “0”, the column of “0” is read as written, and after writing the column of “1” It is checked whether or not the same “1” column is read out. Thus, the memory function of the semiconductor memory device can be tested. When testing the semiconductor memory device having the configuration shown in FIG. 5, the read data is checked only by reading the 1-bit comparison / determination result.
[0075]
FIG. 11 is a flowchart showing a process for testing the semiconductor memory device of the present invention using a checker pattern.
[0076]
In step S1, the input address is set to address 0. In step S2, scan data is input by a scan shift operation. In step S3, a non-scan shift write operation is executed to write scan data consisting of the column “0101. In step S4, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S2. If it is the last address, the process proceeds to step S5.
[0077]
In step S5, the input address is set to address 0. In step S6, scan data is input by a scan shift operation. In step S7, a non-scan shift read operation is executed to read scan data consisting of the column “0101. In step S8, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S6. If it is the final address, the process proceeds to step S9.
[0078]
In step S9, the input address is set to address 0. In step S10, scan data is input by a scan shift operation. In step S11, a non-scan shift write operation is executed to write scan data consisting of the column “1010...”. In step S12, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S10. If it is the last address, the process proceeds to step S13.
[0079]
In step S13, the input address is set to address 0. In step S14, scan data is input by a scan shift operation. In step S15, a non-scan shift read operation is executed to read scan data consisting of the column “1010...”. In step S16, it is determined whether or not the input address is the final address. If it is not the final address, the input address is incremented by 1, and the process returns to step S14. If it is the last address, the process proceeds to step S17. Finally, in step S17, scan shift is executed to output data serially from the output flip-flop.
[0080]
After performing the test using the checker pattern as described above and writing the column “0101...”, The column “0101. After writing this column, it is checked whether or not the column “1010...” As written is read out. Thus, the memory function of the semiconductor memory device can be tested. When testing the semiconductor memory device having the configuration shown in FIG. 5, the read data is checked only by reading the 1-bit comparison / determination result.
[0081]
The above embodiment shows an example of the configuration of the present invention for the purpose of explanation, and the present invention is not limited to the configuration of the above embodiment.
[0082]
For example, in the above embodiment, two scan input flip-flops are provided for a plurality of input data signals I [0], I [1], I [2],. In this way, a march pattern or a checker pattern is formed. When it is necessary to set a pattern different from the march pattern or checker pattern, two or more scan input flip-flops are provided, and a desired pattern is configured by repeating the bit pattern of these flip-flops. Is possible. For example, if there is a request in advance that it is necessary to set the pattern “11001100...”, Four scan input flip-flops are provided, the data “1100” is set, and this is repeated. What is necessary is just composition. Even in this case, it is obvious that an arbitrary march pattern and checker pattern can be formed. At this time, when an expected value storing flip-flop is provided as in the configuration of FIG. 5, four flip-flops are provided.
[0083]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
【The invention's effect】
In the present invention, Two Since the scan flip-flop is provided and the data of the number of bits is configured by repeating the data of the scan flip-flop, it is necessary to provide the same number of scan flip-flops as the number of data and execute the scan shift operation. The input data can be set by a scan shift operation with less than the number of data. This makes it possible to reduce the number of scan shifts required for data setting for the scan flip-flop.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a conventional semiconductor memory device using a scanning method.
FIG. 2 is a diagram showing a configuration of a conventional semiconductor memory device with a partial write function by a scan method.
FIG. 3 is a configuration diagram showing a first embodiment of a semiconductor memory device according to the present invention;
FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention.
FIG. 5 is a block diagram showing a third embodiment of the semiconductor memory device according to the present invention.
6 is a circuit diagram showing a configuration of the comparison circuit of FIG. 5 together with a portion related to data output of the semiconductor memory device. FIG.
FIG. 7 is a diagram showing a timing of a write operation in the semiconductor memory device according to the present invention.
FIG. 8 is a diagram showing a timing of a read operation in the semiconductor memory device according to the present invention.
FIG. 9 is a diagram showing timings of read and write operations in the semiconductor memory device according to the present invention.
FIG. 10 is a flowchart showing a process for testing the semiconductor memory device of the present invention using a march pattern.
FIG. 11 is a flowchart showing a process for testing the semiconductor memory device of the present invention using a checker pattern.
[Explanation of symbols]
30 Semiconductor memory device
31 Semiconductor memory device body
32-0,..., 32-t-1 address input flip-flop
33-0, 33-1 Flip-flop for data input
34-0, ..., 34-b-1 Data output flip-flop
35 Selector circuit
36 XOR circuit
37 NXOR circuit
38, 39 AND circuit
40 output buffers

Claims (5)

a semiconductor memory device body for receiving an n-bit address signal and an m-bit data signal larger than 2;
N scan flip-flops connected in series with each other to serially set the address signal;
Two scan flip-flops connected in series with each other to set the data signal serially ;
By comparing the m-bit output data read from the semiconductor memory device body with the m-bit expected value data configured by repeating the 2-bit expected value data, the output data is converted into the expected value data. A comparison circuit for determining whether or not they match , and repeating the data of the two scan flip-flops to form m-bit data and inputting it to the semiconductor memory device body A semiconductor memory device.   2. The semiconductor memory device according to claim 1, further comprising two scan flip-flops connected in series to each other and for setting a partial enable signal serially. The semiconductor memory device according to claim 1, further comprising a flip-flop set being connected in series with the 2-bit expected value data serially to each other. And a first selector for selecting the n-bit address signal input from the outside during the first operation and for selecting an address signal output from the n scan flip-flops during the second operation. Item 4. The semiconductor memory device according to any one of Items 1 to 3 . A second selector for selecting a data signal of m bits larger than 2 input from the outside during a first operation and for selecting a data signal output from the two scan flip-flops during the second operation; the semiconductor memory device of any one of claims 1 to 4,.

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