JP4650044B2 - Information processing apparatus, system, and information processing method - Google Patents

Description

  The present invention relates to an information processing device, a system, and an information processing method.

  Conventionally, an apparatus for optical transmission between an arithmetic module and a memory module has been proposed. This technique is introduced in Patent Document 1 and Patent Document 2. This solves problems such as increase in power consumption, cost increase, and transmission error due to skew when the conventional bus wiring is electrically connected. In order to realize optical transmission, various means are provided on the transmission side and the reception side. Specifically, photoelectric conversion means, electro-optic conversion means, parallel / serial conversion means, serial / parallel conversion means, error correction code encoding / decoding means, code encoding / decoding means for DC balance, optical transmission For example, a clock and data timing adjusting means for the above-mentioned signals can be combined, and by combining these, accurate signal transmission and reception is possible.

  When a bidirectional data bus signal such as a CPU (Central Processing Unit) bus is to be realized by an optical fiber connection, it is necessary to divide the optical signal system into two systems, a transmission side and a reception side. When data is written (write) from the CPU side to the memory or ASIC (Application Specific Integrated Circuit), the CPU side uses the optical signal transmission side, the memory or ASIC side uses the optical signal reception side, and conversely the CPU When the side goes to read data from the memory or ASIC, the optical signal receiving side is used on the CPU side, and the optical signal transmitting side is used on the side having the memory or ASIC.

  The problem here is securing the bit error rate (BER). In high-speed serial data transmission using an optical fiber, it is essential to prepare an error correction code encoding / decoding means. In reading and writing data on the CPU bus, there is no room for resending data when an error occurs, and error correction must be performed in real time. The actual BER in a state where the BER at the physical level and the error correction algorithm are combined must exceed the required specification. In order to ensure the BER at the physical level, considering the variation in light loss caused by differences in transmission line distance, coupling loss, individual differences in components, etc. In addition to setting, it is required that the data transmitted from each node is synchronized with the clock for latching it on the receiving node side.

  High-speed serial data transmission methods include a method in which a frame clock signal and a data signal are sent together, and a method in which a clock signal frequency is embedded in a data signal without sending a frame clock signal (CDR; Clock Data Recovery). A frame clock signal is required to restore a serial signal to a parallel signal at the receiving node, but it is possible to automatically generate a frame clock signal by a method combining a CDR and a PLL (Phase Locked Loop) circuit or the like.

  However, when a frame clock signal on the receiving side is generated from a PLL circuit or the like, it takes a certain time (usually on the order of milliseconds) to stabilize due to a change in the input signal. The If the system has sufficient time from when the node is switched to when data transfer is started, the above interruption is not a problem.

  However, in a system that needs to shorten the memory access time as much as possible, for example, data transfer between the CPU and the cache memory, such interruption causes a problem because the performance of the entire system is greatly reduced. Therefore, in view of the above circumstances, Patent Document 3 introduces a method aimed at providing a signal transmission system capable of performing one-to-many inter-node transmission connected by a serial transmission path at high speed.

In this technology, a timing adjustment sequence is executed prior to transmission / reception of actual data, and even serial data sent from different slave devices is synchronized in a clock latched by the receiving master device. Thus, even if a node is switched, serial data transmission is not interrupted.
Japanese Patent Laid-Open No. 11-39069 JP 11-39521 A JP 2003-244175 A

  However, depending on the elapsed time since the execution of the timing adjustment sequence, the synchronization state between each slave device and the master device can be maintained due to, for example, individual differences between devices on each slave device, environmental changes such as ambient temperature, etc. There is a problem of disappearing.

  Therefore, the present invention has been made in view of the above problems, and provides an information processing apparatus, a system, and an information processing method capable of maintaining the synchronization state of signals between both nodes on the transmission side and the reception side. Objective.

In order to solve the above-described problems, the present invention provides an information processing apparatus that transfers data to and from an external device, and is synchronized with a first frame clock signal used for synchronous transmission with respect to the external device. Transmitting means for transmitting a first data signal; receiving means for receiving a second data signal transmitted in synchronization with a second frame clock signal used by the external device for synchronous transmission; and during execution of data transfer , The first frame clock signal and the second frame clock signal based on a clock that establishes a constant phase difference relationship with the first frame clock signal and the second data signal. Determining means for determining a degree of phase difference displacement; and correcting a phase difference displacement of the second frame clock signal with respect to the first frame clock signal based on a determination result of the determining means. To order, and a control means for transmitting a command for prompting the change of the phase setting value of the second frame clock signal to the external device, the second frame clock signal, said first frame clock The second frame clock signal is generated based on the first frame clock signal and is not transmitted from the external device to the information processing device so as to establish a constant phase difference relationship with the signal. The information processing apparatus is characterized in that the second data signal transmitted in synchronization with the second data signal is restored from a serial signal to a parallel signal using the first frame clock signal .

  According to the present invention, the tendency of the phase shift can be continuously monitored even during the data transfer, and the change of the phase setting value of the second frame clock signal is urged to correct the phase shift as necessary. By sending the command, it is possible to ensure the bit error rate (BER) of the bidirectional bus system. As a result, it is possible to realize a bidirectional bus system that maintains the synchronized state of signals between both nodes on the transmission side and reception side when performing transmission between one-to-many nodes connected by a serial transmission path.

  The determination means uses a clock synchronized with the second frame clock signal, a clock whose phase is advanced from the second frame clock signal, and a clock whose phase is delayed from the second frame clock signal, The phase difference between the first frame clock signal and the second frame clock signal is determined.

  The determination unit generates a clock whose phase is advanced from the second frame clock signal and a clock whose phase is delayed from the second frame clock signal based on the adjustment step interval in the external device. The phase adjustment step interval is determined. The first frame clock signal and the second frame clock signal are generated based on the same oscillation source. At least one of the first data signal and the second data signal is transmitted through an optical transmission medium. The first frame clock signal is transmitted through an optical transmission medium.

The system of the present invention is a system including the information processing apparatus and an external apparatus that transfers data between the information processing apparatus via an optical transmission medium.
The present invention provides a transmission step of transmitting a first data signal in synchronization with a first frame clock signal used for synchronous transmission to an external device, and a second frame clock signal used by the external device for synchronous transmission. A receiving step for receiving the second data signal to be transmitted, and a determining step for determining a degree of phase difference displacement between the first frame clock signal and the second frame clock signal during execution of data transfer; An information processing method comprising: a changing step of changing a latch timing at the time of data reception in order to correct a phase difference displacement of the second frame clock signal with respect to the first frame clock signal based on a determination result of the determination step It is.

  According to the present invention, the tendency of the phase shift can be continuously monitored even during the data transfer, and the bidirectional data bus is urged to change the latch timing of the received data in order to correct the phase shift as necessary. It becomes possible to secure the bit error rate (BER) of the system. As a result, it is possible to realize a bidirectional bus system that maintains the synchronized state of signals between both nodes on the transmission side and reception side when performing transmission between one-to-many nodes connected by a serial transmission path.

The present invention provides a transmission step of transmitting a first data signal in synchronization with a first frame clock signal used for synchronous transmission to an external device, and a second frame clock signal used by the external device for synchronous transmission. Receiving the second data signal to be transmitted and the clock and the second data signal establishing a certain phase difference relationship between the first frame clock signal and the first frame clock signal during execution of the data transfer And a determination step of determining a degree of phase difference displacement between the first frame clock signal and the second frame clock signal, and the first frame clock signal with respect to the first frame clock signal based on a determination result of the determination step. In order to correct the phase difference displacement of the second frame clock signal, the phase setting value of the second frame clock signal to the external device Possess sending a command to prompt the change, wherein the second frame clock signal, so as to establish a constant phase difference relationship between the first frame clock signal, the first frame The second data signal generated based on the clock signal and not transmitted from the external device to the information processing device and transmitted in synchronization with the second frame clock signal is the first frame clock. The information processing method is characterized in that a signal is used to restore a serial signal to a parallel signal .

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus, system, and information processing method which can maintain the synchronous state of the signal between both transmitting side and receiving side nodes can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described.

  FIG. 1 is a schematic diagram showing a configuration example of a bidirectional optical transmission system according to the present invention. CPUs used for controlling mechanical operation, ASIC for image processing, and the like include a CPU bus called a CPU interface for electrically connecting and controlling the CPU and its peripheral devices. When the bidirectional data bus of the CPU bus is to be realized by optical fiber connection, as shown in FIG. 1, it is necessary to divide the optical signal system into two systems, a transmission side and a reception side.

  The signal transmission system 100 includes a master device (information processing device) 1, a main slave device 2, and a plurality of sub slave devices 3 and 4. The master device 1 performs data transfer with the slave devices 2 to 4. The master device 1 includes a CPU (processor) 11, an ASIC 12, an optical transmitter 13, and an optical receiver 14. The optical transmitter 13 includes a light emitting element 131 such as a laser diode (LD), a driving circuit 132 thereof, and an optical connector 133 for coupling with an optical fiber. The optical receiver 14 includes a light receiving element 141 such as a photodiode (PD), a receiving circuit 142, and an optical connector 143 for coupling with an optical fiber. The ASIC 12 is given a predetermined clock from the oscillator 15.

  The main slave device 2 and the sub slave devices 3 and 4 can have the same configuration. The main slave device 2 and the sub slave devices 3, 4 have memories 21, 31, 41, ASICs 22, 32, 42, optical transmitters 23, 33, 43, and optical receivers 24, 34, 44, respectively. As in the case of the master device, the optical transmitters 23, 33, and 43 have light emitting elements such as laser diodes (LD), their drive circuits, and optical connectors 233, 333, and 433 for coupling with optical fibers. Similarly, the optical receivers 24, 34, and 44 include light receiving elements such as photodiodes (PD), receiving circuits, and optical connectors 243, 343, and 443 for coupling to optical fibers.

  The master device 1 and each of the slave devices 2 to 4 are connected by a downstream optical transmission path 5 and an upstream optical transmission path 6. The downstream optical transmission path 5 includes an optical fiber 51, an optical branching device 55, and a plurality of optical fibers 52 to 54. The upstream optical transmission line 6 includes an optical fiber 61, an optical coupling device 65, and a plurality of optical fibers 62 to 64. The optical fiber 51 is connected to the optical connector 133, and the optical fibers 52 to 54 are connected to the optical connectors 243, 343, and 443. The optical fiber 61 is connected to the optical connector 143, and the optical fibers 62 to 64 are connected to the optical connectors 233, 333, and 433. Here, for example, a plastic optical fiber (POF) can be used as the optical fiber, but the optical fiber is not limited thereto. As the optical branching device 55 and the optical coupling device 65, for example, a star coupler or an optical sheet bus provided with a transmitted light diffusing unit can be used.

  FIG. 2 is a detailed block diagram of the master device 1 and the main slave device in the bidirectional optical transmission system shown in FIG. The sub-slave devices 3 and 4 are omitted because they have the same configuration as the main slave device. As shown in FIG. 2, the master device 1 includes a CPU 11, an optical transmitter 13, an optical receiver 14, an oscillator 15, a transmission PLL circuit 16, a reception PLL circuit 17, a parallel / serial converter (SERDES) 18, and a serial / parallel converter. (SERDES) 19, a timing adjustment circuit 110, and a reception timing detection block 111. The CPU 11 transmits / receives data to / from the main slave device 2 and the sub slave devices 3 and 4 through the CPU bus, transmits a timing adjustment start signal to the timing adjustment circuit 110 as necessary, and is busy from the timing adjustment circuit 110. Receive the signal.

  Frame clock signals output from the master device 1 and the slave devices 2, 3, 4 can be generated from the same oscillator 15. In this way, the master side frame clock signal and the slave side frame clock signal are generated based on the same oscillation source. This can be realized by transmitting the master side frame clock signal generated by the oscillator 15 to the slave device 2 and connecting the reception frame clock signal and the transmission frame clock signal on the slave device 2 side.

  The timing adjustment circuit 110 activates the timing adjustment sequence if the timing adjustment activation signal from the CPU 11 is valid, and connects the input / output signal with the outside to the inside as it is invalid. The transmission PLL 16 receives the reference clock signal output from the oscillator 15 and outputs a frame clock signal with a adjusted duty ratio. The parallel / serial converter 18 performs speed conversion of the parallel data signal and outputs a serial data signal. For example, 16 parallel data signals with a transmission rate of 50 Mbps are input as input signals, and a 50 MHz frame clock signal output from the transmission PLL 16 is provided. Is performed, the output signal of the parallel-serial conversion unit 18 is two serial data signals of 500 Mbps. The optical transmitter 13 transmits a master data signal (first data) to the slave device 2 in synchronization with a master side frame clock signal (first frame clock signal) used for synchronous transmission.

  The optical receiver 14 receives a slave data signal (second data) transmitted in synchronization with a slave-side frame clock signal (second frame clock signal) used by the slave device 2 for synchronous transmission. The reception PLL 17 inputs a frame clock signal from the serial bus and performs the same operation as the transmission PLL 16. The serial / parallel converter 19 performs serial / parallel conversion of the serial data signal and outputs a parallel data signal. For example, when two serial data signals each having a transmission rate of 500 Mbps are provided as input signals and a 50 MHz frame clock signal output from the reception PLL 17 is provided and 8B10B decoding is performed, the output signal of the serial / parallel converter 19 is 50 Mbps. There are 16 parallel data signals.

  The reception timing detection block 111 determines the degree of phase difference displacement between the master side frame clock signal and the slave side frame clock signal during execution of data transfer. The master side frame clock signal and the slave side frame clock signal are adjusted in advance so as to establish a certain phase difference relationship.

  In addition, the reception timing detection block 111, when receiving slave data during the period of executing data transfer, has received the center phase clock synchronized with the slave side frame clock signal and the phase advanced from the slave side frame clock signal. Prepare the shift phase clock and the shift phase clock after delaying the phase from the slave side frame clock signal, and compare the received results using each clock, so that the master side frame clock signal and the slave side frame clock signal Determine the phase difference. As a result, it can be determined whether the phase of the slave side frame clock signal is advanced, delayed, or neither relative to the master side frame clock signal.

  In addition, the reception timing detection block 111 has a pre-shift phase clock whose phase is advanced from the slave-side frame clock signal and a post-shift phase clock whose phase is delayed from the slave-side frame clock signal based on the adjustment step interval in the slave device 2. To determine the phase adjustment step interval for generating.

  The CPU 11 changes the phase setting value of the slave side frame clock signal with respect to the slave device 2 in order to correct the phase difference displacement of the slave side frame clock signal with respect to the master side frame clock signal based on the determination result of the reception timing detection block 111. A command for prompting may be transmitted. Receiving this, the slave device 2 rewrites the register storing the phase setting value of the slave side frame clock signal in accordance with the command. Here, the register is included in the timing adjustment circuit 26 of FIG. The timing adjustment circuit 26 needs to store an optimum phase set value parameter, and a register holds the parameter. Based on the phase setting value parameter in the register, the delay value of the programmable delay line 27 is set through the 8-bit signal line. By correcting the setting value of the timing adjustment circuit 26 on the slave device side 2 during the period when normal data transmission is not performed, the phase of the slave side frame clock signal is shifted, resulting in the correct timing of the slave data on the master side. So that it can be received.

  The main slave device 2 includes an optical transmitter 23, an optical receiver 24, a serial / parallel converter (SERDES) 25, a timing adjustment circuit 26, a programmable delay line 27, and a parallel / serial converter (SERDES) 28. The sub slave devices 3 and 4 have the same configuration. The optical receiver 24 receives a master data signal and a master side frame clock signal from the master device 1 as a set. The optical transmitter 23 transmits a slave data signal synchronized with the slave side frame clock signal to the master device 1.

  The timing adjustment circuit 26 activates the timing adjustment sequence if the timing adjustment activation signal is valid, but connects the input / output signal with the outside as it is when the timing adjustment circuit is invalid. The programmable delay line 27 generates a slave side frame clock signal used for synchronous transmission of a slave data signal to be transmitted to the master device 1 based on the master side frame clock signal received by the optical receiver 24. The programmable delay line 27 is a device whose delay time is variable, and outputs the serial data signal input from the serial bus in synchronization with the timing delayed according to the instruction signal from the timing adjustment circuit 26.

  FIG. 3 is a flowchart of the entire timing adjustment sequence. When the timing adjustment activation signal is detected in step S31, the busy signal is activated in step S32 and the busy state is notified to the outside. Thereby, input / output of data signals is prohibited during the timing adjustment processing. A reception adjustment sequence is executed in step S33, and a transmission adjustment sequence is executed in step S34. When these are finished, the busy state for the outside is canceled in step S35, and the whole is finished.

  FIG. 4 is a flowchart of the reception adjustment sequence. 4 to 6, thick arrows represent signal exchange between the master device 1 and the slave device 2. In the reception adjustment sequence, step SM41 executed by the master side timing adjustment circuit 110 is activated. This represents a process of transmitting the test pattern signal from the parallel-serial converter 18 to all slave devices.

This test pattern is stored in advance in storage means such as a memory in both the master side timing adjustment circuit 110 and the slave side timing adjustment circuit 26. For example, if the test pattern is a 10-bit signal, the following repetitive pattern is used.
-Bit string 1. “0001110101”
-Bit string 2. “0011010101”

The conditions necessary for the test pattern depend on the specifications of the transmission path, but for example, the following is necessary.
・ Condition 1 1. The logical value “1” occupies 40% to 60% in the bit string. It can be determined from the pattern itself which bit is the first bit. Bit strings 1 and 2 both satisfy conditions 1 and 2.

  Next, in step SM42, the master side timing adjustment circuit 110 continues to transmit the test pattern signal for a predetermined time, and then ends the process. The fixed time here represents a time sufficiently longer than the processing time of steps SS41 to SS51 of the slave side timing adjustment circuit 26 described below.

Next, processing of the slave side timing adjustment circuit 26 will be described. In step SS41, the slave side timing adjustment circuit 26 receives the test pattern signal transmitted in step SM41. At this time, the slave-side timing adjustment circuit 26 needs to set an initial value of the reception timing for the programmable delay line 27 in advance. In step SS42, the slave side timing adjustment circuit 26 collates the received test pattern with the correct answer pattern stored in advance, and stores the collation result in the memory in step SS43. Here, for example, when the bit string 1 is a correct pattern, the received test pattern is a bit string 3. Assume that it is “10000111010”. In this case, each bit is correctly received, but the position of the first bit is only shifted to the lower side by one bit. Therefore, the following two are stored as the collation results.
Results 1. Whether all individual bits are received correctly.
Result 2. If the result 1 is OK, how many bits should be shifted to get the correct answer?

  In step SS44, it is determined whether or not all the reception timing tests have been completed. If not completed, the reception timing is changed in step SS45, and the process returns to step SS41. Here, the change of the reception timing is executed by the programmable delay line 27 in accordance with an instruction from the timing adjustment circuit 26 on the slave side. When the test is completed, all matching results are read from the memory at step SS46, and the optimum reception timing is determined at step SS47.

  Table 1 below shows an example of a collation result based on eight reception timings that are continuously changed as an example. Here, among reception timings 3 to 7 in which “Result 1” is OK, intermediate reception timing 5 is determined as the optimum reception timing. As a determination method, for example, a look-up table in which 8 bits representing “result 1” are used as addresses and optimum reception timing for each address is stored in advance can be used.

In the example of Table 1, if OK is a value “1”, NG is a value “0”, “Result 1” at reception timing 8 is MSB, and “Result 1” at reception timing 1 is LSB, address “01111100”, that is, 124 addresses In addition, a value indicating the reception timing 5 is stored.

  Since all the results may be NG, in step SS49, the slave side timing adjustment circuit 26 determines whether or not a receivable result has been obtained, and if it is NG, the reception timing cannot be set. In step SS50, an error signal is output to the outside. Otherwise, in step SS48, the slave side timing adjustment circuit 26 stores the result in the memory, and sets the optimum reception timing for the programmable delay line 27 in step SS51. Thus, the processing of the slave side timing adjustment circuit 26 is completed.

  FIG. 5 is a diagram illustrating a transmission adjustment sequence in the master device 1, and FIG. 6 is a diagram illustrating a transmission adjustment sequence in the slave device 2. Both figures are connected by “A”, “B”, and “C” in each figure. In the transmission adjustment sequence, step SM81 executed by the master side timing adjustment circuit 110 is activated. This represents processing for transmitting the ID signal from the parallel-serial converter 18 to all slave devices. The ID signal is a signal having an ID number set in advance for identifying each slave node as a data signal.

  Since the transmission adjustment sequence is executed by one-to-one transmission between each slave device 2 to 4 and the master device 1, step SM81 is required to designate one slave device from the master device 1 side. In step SM82, the master side timing adjustment circuit 110 continues to transmit the ID signal for a predetermined time, and then receives the test pattern transmitted from the slave device 2 in step SM83.

  Next, processing of the slave side timing adjustment circuit 26 will be described. The processing of the slave side timing adjustment circuit 26 below is executed in all slave devices. In FIG. 6, first, in step S92, the timing adjustment circuit 26 initializes transmission timing. In step SS81, the timing adjustment circuit 26 receives the ID signal transmitted in step SM81, and determines whether it is an ID signal or an end notification signal. If an end notification signal is received, the process ends. If the ID signal is received, the ID number of each slave device is checked in step SS82, and it is determined in step SS83 whether or not the own node is designated. This determination result is held by storage means such as a register. As a result of step SS83, the slave device 2 designated by the ID signal transmits a test pattern signal to the master device 1 in step SS84. The test pattern signal is the same as step SM41 in FIG.

  In addition, the slave device not designated by the ID signal transmits a test pattern signal in which all logical values are “0” in step SS85. Steps SS84 and SS85 are executed at the same timing, and the signals are joined on the serial bus. Therefore, it is necessary to select the signal at step SS85 so that the test pattern signal at step SS84 is not affected by the merge and is correctly transmitted to the master device 1.

  Next, the processing of the master side timing adjustment circuit 110 will be described. The four steps from step SM83 to step SM86 that receive the test pattern are the same as steps SS41 to S44 in FIG. In step SM86, it is determined whether or not all transmission timing tests have been completed for the currently designated slave device, and if not completed, a timing change instruction signal is transmitted to the slave device in step SM90. Here, the timing change instruction signal is an instruction signal for changing the transmission timing from the slave device 2 and performing the test again.

  Next, in step SM95, after continuing to transmit the timing change instruction signal for a predetermined time, the process returns to step SM83, and steps SM83 to M86 are executed. The fixed time in step SM95 is a time sufficiently longer than the processing time of steps SS86 to SS87 and SS83 to SS85 by the slave side timing adjustment circuit 26 described later. On the other hand, when the test is completed, all the collation results are read from the memory at step SM87, the optimum timing is determined at step SM88, and the result is transmitted as a selection result signal to the slave device at step SM89. Steps SM87 and SM88 are the same as steps SS46 and S47 in FIG.

  Subsequently, in step SM91, it is determined whether or not the transmission timing adjustment has been completed for all slave devices. If it has not been completed yet, the ID number of the slave device is updated in step SM92, and the process returns to step SM81 to adjust the transmission timing of the next slave device. In the case of the end of adjustment, in steps SM96 and SM97, the end notification signal is continuously transmitted to the slave device for a predetermined time. Here, the fixed time indicates a time sufficiently longer than the processing time of S81 by the slave side timing adjustment circuit 26. Finally, in step SM93, the final result and status are output, and the process is terminated.

  The slave side timing adjustment circuit 26 receives the signal transmitted at step SM89 or SM90 by the master side timing adjustment circuit 110 at step SS86. If the received signal is a timing change instruction signal, the transmission timing control unit 24b is instructed to change the data transmission timing in step SS87, and the process returns to step SS83. If the received signal is a selection result signal, the result is stored in the memory in step SS88, and set in the transmission timing control unit 24b in step SS89. Furthermore, after stopping the transmission of the test pattern to the master device 1 in step SS90, the process returns to step SS81. If a signal other than the above is received in step SS86, the process returns to step SS83 and continues to transmit the test pattern signal.

  FIG. 7 is a diagram illustrating a configuration of the reception timing detection block 111. As shown in FIG. 7, the reception timing detection block 111 includes delay circuits 191 to 193, latch circuits 194 to 196, and a comparison circuit 197. Reference numeral 202 denotes a post-processing circuit for notifying the CPU 11 of a result after predetermined processing of the output result from the comparison circuit 197.

  The serial data signal input unit IS for timing monitoring of the reception timing detection block 111 exists in parallel with the original processing flow of serial data reception, serial / parallel conversion circuit 19, and parallel data output. At least one serial data signal input channel for timing monitoring of the reception timing detection block 111 is required, and the same number of channels as that of a normal serial data receiving unit may be provided. On the other hand, the clock signal input unit IC of the reception timing detection block 111 is connected to the oscillator 15 (system clock) of the master device 1. This is divided into the following three clocks.

  The delay circuit 191 generates a center phase clock by delaying the input system clock by one cycle. This center phase clock is a clock synchronized with the slave side frame clock signal. The delay circuit 192 shifts the phase forward by an integer (N) times the transmission timing adjustment minimum step interval in the slave device 2 with respect to the center phase clock, and generates a pre-shift phase clock. This shift phase clock is a clock whose phase is advanced from the slave side frame clock signal. The delay circuit 193 generates a shifted phase clock after shifting the phase backward by an integer (N) times the transmission timing adjustment minimum step interval in the slave device 2 with respect to the center phase clock. Thereafter, the shift phase clock is a clock delayed in phase from the slave side frame clock signal.

  The above-mentioned timing monitor serial data signal is divided into three systems, and each is latched at the rising edge of a clock having three different phases. Since each clock is not multiplied, assuming that the serial data is formed by 10: 1 transmission, the chance that the rising edge of each clock can latch the serial data is 1/10. That is, when 10 serial data are input to a certain channel, only one clock is latched by each clock.

  The comparison circuit 197 compares the results latched by the latch circuits 194 to 196 with the above three types of center phase clock, front shift phase clock, and rear shift phase clock, and outputs the result. That is, the comparison circuit 197 compares the received results using the above three clocks, so that the CPU 11 determines the phase difference between the master side frame clock signal and the slave side frame clock signal. As a result, it can be determined whether the phase of the slave side frame clock signal is advanced, delayed, or neither relative to the master side frame clock signal.

  FIG. 8 is a diagram for explaining a method for detecting a phase shift of the frame clock signal during data transfer. The current latch timing test target “0” and the next latch timing test target “0” are shown. Further, (a) shows a front shift phase clock, (b) shows a center phase clock, and (c) shows a rear shift phase clock. FIG. 8 shows three patterns of phase shift. In the figure, “◯” and “x” indicate the determination results of the CPU 11. The CPU 11 determines that the adjustment value of the slave synchronization signal is not changed if the latch results of the center phase clock, the previous shift phase clock, and the rear phase clock are the same. Since the CPU 11 can receive at a normal timing, it uses the stored slave timing adjustment value as it is.

  When the latch results in the center phase clock and the rear shift phase clock are the same, and only the latch results in the previous shift phase clock are different, the CPU 11 needs to modify the adjustment value of the slave synchronization signal. Judge that it is necessary to shift. The CPU 11 transmits to the slave device 2 a command for urging correction of the stored slave timing adjustment value in order to shift the center phase clock later. When the latch results in the center phase clock and the previous shift phase clock are the same and only the latch results in the rear shift phase clock are different, the CPU 11 needs to modify the adjustment value of the slave synchronization signal, It is determined that it is necessary to shift to The CPU 11 transmits a command for urging correction of the stored slave timing adjustment value to the slave device 2 in order to shift the center phase clock forward.

  FIG. 9 is a diagram for explaining a timing budget for a latch timing test. 9, (a) to (c) are the master side frame clock signals, (d) is the timing specification of the receiving side device (master device 1), and (e) is the serial data transmitted from the slave device 2, respectively. . Sampling Window is the minimum time that receiving device 1 can receive data, RSKM is the jitter margin that receiving device 1 allows for data, System SW is the setup and hold time of data that can be created by the transmission system, and System RSKM Indicates jitter generated in the transmission system. In the figure, “○” indicates that the setup time and hold time are sufficient, so that data can be latched, and “×” indicates that the setup time and hold time are insufficient, so that data cannot be latched. Indicates that it is possible.

  The value of the integer N is the relationship between the sampling window (SW: Sampling Window) interval and the transmission timing adjustment minimum step interval S shown in the timing budget shown in FIG. Determined to satisfy the relationship.

  s × N × 2 <SW <s × N × 3 (1)

  Here, N is an integer. All of these can be realized by a combination of a delay element such as a delay line and a PLL.

  FIG. 10 is an operation flowchart for correcting the phase shift. In step S91, the CPU 11 determines whether the latch results of the previous shift phase clock and the center phase clock match. If the latch results match, the process proceeds to step S95. If the latch results do not match, the process proceeds to step S92. . In step S92, the CPU 11 determines whether or not it has occurred N times during the unit time. If it has not occurred N times, the process returns to step S91. If it has occurred N times, the process proceeds to step S93. Here, N is an integer set in advance. In step S93, the CPU 11 transmits a command for urging correction of the stored slave timing adjustment value to the slave device 2, and as a result, shifts the slave data one step before the phase of the master side frame clock signal.

  In step S94, the CPU 11 determines whether the latch results of the previous shift phase clock and the center phase clock match. If the latch results do not match, the CPU 11 returns to step S93 to latch the previous shift phase clock and the center phase clock. The process loops until the results match, and if the latch results of the front shift phase clock and the rear shift phase clock match, the process proceeds to step S95. In step S95, the CPU 11 determines whether or not the latch results of the center phase clock and the post-shift phase clock match. If the latch results of the center phase clock and the post-shift phase clock match, the stored slave timing adjustment value is determined. Are used as they are, and the process proceeds to Step S99.

  In step S95, if the latch results of the center phase clock and the post-shift phase clock do not match, the CPU 11 determines in step S96 whether or not it has occurred N times during the unit time, and occurs N times during the unit time. If not, the process returns to step S95, and if it occurs N times, the process proceeds to step S97. Here, N is an integer set in advance.

  In step S97, the CPU 11 transmits a command for urging correction of the stored slave timing adjustment value to the slave device 2, and consequently shifts the slave data backward by one step with respect to the phase of the master side frame clock. In step S98, the CPU 11 determines whether or not the latch results of the center phase clock and the rear shift phase clock match, and if the latch results do not match, the CPU 11 returns to step S97 to return to the center phase clock and the rear shift phase clock. Loop until the latch results match, and if they match, the process proceeds to step S99. In step S99, the CPU 11 returns to step S91 when the data transmission is not stopped, and ends the process when the data transmission is stopped.

  It should be noted that whether the center phase clock should be shifted forward, backward, or not required at all is not determined once, but based on the cumulative count results of a plurality of times as shown in FIG. . At this time, focusing on the number of counts per unit time instead of a simple cumulative result, it is determined that a deviation has occurred only when the same tendency continues for a certain period of time. This suppresses the occurrence of false detections resulting from variations. When determination results exceeding the predetermined number of times set in advance are accumulated, the CPU 11 transmits a command for urging correction of the slave timing adjustment value to the slave device 2.

  The command transmission described above must be executed when data transmission is not performed.

  According to the above-described embodiment, the tendency of the phase shift can be continuously monitored even during the data transfer, and it is possible to change the latch timing of the received data in order to correct the phase shift as necessary. It becomes possible to ensure the bit error rate (BER) of the bus system. As a result, it is possible to realize a bidirectional bus system that maintains the synchronized state of signals between both nodes on the transmission side and reception side when performing transmission between one-to-many nodes connected by a serial transmission path. The master device 1 corresponds to the information processing device, the optical transmitter 13 corresponds to the transmission means, the optical receiver 14 corresponds to the reception means, the reception timing detection block 111 corresponds to the determination means, and the CPU 11 corresponds to the control means.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed. For example, the master device 1 has been described as an example of the information processing device, but the slave device 2 may be an information processing device.

It is the schematic which shows the structural example of the bidirectional | two-way optical transmission system which concerns on this invention. FIG. 2 is a detailed block diagram of a master device 1 and a main slave device in the bidirectional optical transmission system shown in FIG. 1. It is a flowchart of the whole timing adjustment sequence. It is a figure which shows the flowchart of a reception adjustment sequence. 4 is a transmission adjustment sequence in the master device 1; It is a transmission adjustment sequence in the slave device 2. It is a figure which shows the structure of a reception timing detection block. It is a figure explaining the phase shift detection method of the frame clock signal at the time of data transfer. It is a figure for demonstrating the timing budget of a latch timing test object. It is an operation | movement flowchart at the time of correcting a phase shift.

Explanation of symbols

100 Signal Transmission System 1 Master Device 2 Main Slave Device 3 4 Sub Slave Device 11 CPU
12 ASIC
13 Optical Transmitter 14 Optical Receiver 110 Timing Adjustment Circuit 111 Reception Timing Detection Block

Claims (8)

An information processing device that transfers data to and from an external device,
Transmitting means for transmitting a first data signal in synchronization with a first frame clock signal used for synchronous transmission to the external device;
Receiving means for receiving a second data signal transmitted in synchronization with a second frame clock signal used by the external device for synchronous transmission;
During execution of data transfer, the first frame clock signal and the second data signal are based on the clock and the second data signal that establish a certain phase difference relationship with the first frame clock signal. Determining means for determining the degree of phase difference displacement of the frame clock signal;
In order to correct the phase difference displacement of the second frame clock signal with respect to the first frame clock signal based on the determination result of the determination means, the phase setting value of the second frame clock signal is set to the external device. And a control means for transmitting a command prompting the change ,
The second frame clock signal is generated based on the first frame clock signal so as to establish a certain phase difference relationship with the first frame clock signal, and the information is received from the external device. Is not sent to the processor
The information processing apparatus, wherein the second data signal transmitted in synchronization with the second frame clock signal is restored from a serial signal to a parallel signal using the first frame clock signal .   The determination means uses a clock synchronized with the second frame clock signal, a clock whose phase is advanced from the second frame clock, and a clock whose phase is delayed from the second frame clock signal. The information processing apparatus according to claim 1, wherein a phase difference between the first frame clock signal and the second frame clock signal is determined. The determination unit generates a clock whose phase is advanced from the second frame clock signal and a clock whose phase is delayed from the second frame clock signal based on the adjustment step interval in the external device. The information processing apparatus according to claim 2 , wherein a phase adjustment step interval is determined.   The information processing apparatus according to claim 1, wherein the first frame clock signal and the second frame clock signal are generated based on the same oscillation source.   The information processing apparatus according to claim 1, wherein at least one of the first data signal and the second data signal is transmitted via an optical transmission medium.   The information processing apparatus according to claim 1, wherein the first frame clock signal is transmitted via an optical transmission medium.   A system comprising: the information processing apparatus according to any one of claims 1 to 6; and an external apparatus that transfers data to and from the information processing apparatus via an optical transmission medium. A transmission step of transmitting a first data signal in synchronization with a first frame clock signal used for synchronous transmission to an external device;
A receiving step of receiving a second data signal transmitted in synchronization with a second frame clock signal used by the external device for synchronous transmission;
During execution of data transfer, the first frame clock signal and the second data signal are based on the clock and the second data signal that establish a certain phase difference relationship with the first frame clock signal. A determination step for determining the degree of phase difference displacement of the frame clock signal;
In order to correct the phase difference displacement of the second frame clock signal with respect to the first frame clock signal based on the determination result of the determination step, the phase setting value of the second frame clock signal is set to the external device. Sending a command to prompt for change;
I have a,
The second frame clock signal is generated based on the first frame clock signal so as to establish a certain phase difference relationship with the first frame clock signal, and the information is received from the external device. Is not sent to the processor
The information processing method, wherein the second data signal transmitted in synchronization with the second frame clock signal is restored from a serial signal to a parallel signal by using the first frame clock signal .

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