JP3024528B2 - Timing transfer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing transfer circuit, and more particularly to a timing transfer circuit for performing timing transfer within a device from the timing of received data.

[0002]

2. Description of the Related Art In a data transmission system, a data transmitting side and a data receiving side operate at independent clock signal and frame signal timings, and frequency synchronization of each timing signal is established. The phase is operating under indeterminate conditions. Therefore, it is necessary to transfer the data received from the transmission path to the timing of a clock signal or a frame signal in its own device.

FIG. 5 shows an example of this type of conventional timing transfer circuit. A received data signal is sent to a memory unit (eg, a FIFO (First-In First-Out) memory) 1 and a received clock signal d. Writing at the timing of the frame signal e and reading at the timing of the in-device clock signal a and the in-device frame signal b perform timing transfer, that is, clock transfer.

In this case, a phase collision area output unit 3 and a phase collision detection unit 4 are provided because it is necessary to avoid competition between write timing and read timing for the memory 1.

The phase collision area output section 3 generates a so-called window pulse signal c having a predetermined width before and after the frame signal b in the apparatus, and the phase collision detection section 4 generates the window pulse signal c. When the received frame signal f for writing is included in the signal c, a phase collision detection signal is generated on the assumption that contention occurs in both the read and write timings.

In response to the generation of the phase collision detection signal,
By activating the phase inverting unit 2 to shift the phase of the received frame signal e by 180 degrees, a conflict between the timings of writing and reading is avoided thereafter.

FIG. 6 is a time chart showing the operation of the block shown in FIG. 5, and FIGS. 6 (a) to 6 (f) show the waveforms of the signals a to f in FIG. FIG. 6 (g),
(I) and (j) show the respective phase states of the received frame signal. FIG. 6 (h) shows the memory write frame signal f after the phase control in the received frame signal phase state of FIG. 6 (g).
3 shows the state of the phase.

At the start of the line operation, the time ranges of t1 and t2 before and after the rising of the frame signal b in the device, respectively,
The phase collision area output unit 3 outputs this as a window pulse signal c assuming that it is a phase collision area on the characteristics of the memory unit 1.

When the received frame signal e is at the position shown in FIG. 6E, it does not exist in the window pulse signal, so that the phase inverting unit 2 does not perform phase control, and the received frame signal e is The line is supplied to the memory unit 1 as f and the line is brought into a steady state.

When the received frame signal e is at the position shown in FIG. 6 (g), since it exists in the window pulse signal,
In the phase collision range, the received frame signal e is shifted by 180 degrees in the phase inverting unit 2 as shown in FIG. 6 (h), is out of the range of the window pulse signal c, and then becomes a steady state.

[0011] Jitter and fluctuation during line use (Wonder)
As a result, the phase of the write frame signal f is
(I) and (j), there is no problem if the shift is made within the period t3 or t4, since it cannot enter the range of the window pulse signal c. Is within the range of the window pulse signal c, and as a result, the phase of the write frame signal f temporarily becomes 1
As a result, the data is skipped by 80 degrees, so that the write data is lost or the data is read twice in the memory unit 1, and an error occurs during the line operation.

[0012]

In this type of conventional timing transfer method, the phase control on the write side is performed to avoid the collision of the read / write phase of the memory. Wonder)
Occurs, phase control on the writing side is performed, and there is a problem that an error may occur on the line.

It is an object of the present invention to provide a timing transfer circuit which can operate stably even when the timing phase fluctuates due to jitter or fluctuation during operation.

[0014]

SUMMARY OF THE INVENTION A timing transfer circuit according to the present invention writes received data into a memory in synchronization with a timing signal of the received data, and reads out the received data from the memory in synchronization with a timing signal in the apparatus. A timing transfer circuit for performing a timing transfer between a power-on state and a power-on state in order to detect a conflict between a timing signal of received data and a timing signal in the apparatus.
Of different lengths showing the two types of phase collision regions
And the first and the window pulse signal generating means for a second window pulse signal generating based on the device timing signal, the first and second windows in a predetermined period from when the power is turned on for the second period shown respectively A window pulse selecting means for selecting a window pulse for a long period of time from among the pulse signals, and thereafter for selecting a remaining window pulse, and when the timing signal of the received data enters within the period of the selected window pulse. Phase adjusting means for shifting the phase of the timing signal of the received data by a predetermined value.

Another timing transfer circuit according to the present invention is a serial-parallel conversion means for serial-parallel conversion of received data in synchronization with a timing signal of the received data, and a non-inverting phase of the parallel received data for the timing signal of the received data. First and second latch means for latching in synchronism with a negative-phase signal, and selection means for selecting the outputs of the first and second latch means in accordance with a selection control signal, respectively. A serial-to-serial conversion means for performing parallel-to-serial conversion in synchronization with an internal timing signal; and a predetermined different length at which there is a risk of the contention in order to detect a contention between the received data timing signal and the internal device timing signal. Window pulse signal generating means for generating first and second window pulse signals respectively indicating the first and second time periods based on the in-apparatus timing signal; Wherein between regular first and second
Window pulse selecting means for selecting a window pulse for a long period of time from among the window pulse signals, and thereafter selecting the remaining window pulse, and determining whether the reception timing signal has entered within the period of the selected window pulse. Means for detecting and generating the selection control signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. By determining the phase relationship between the reception timing and the in-device timing with a larger margin at the start of line operation, jitter and fluctuations may occur during the subsequent line operation. Even if the phase fluctuates, the timing can be changed without performing the phase control of the reception timing, and a stable operation can be performed without errors.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram for explaining the principle of the present invention, and the same parts as those in FIG. 5 are denoted by the same reference numerals.
In FIG. 1, a window pulse generator 5 generates a window pulse signal having a predetermined width before and after a frame signal in the apparatus, based on the frame signal in the apparatus. The length of the window pulse signal during the subsequent line operation is shorter than that of the conventional window pulse signal c in FIGS. It is assumed that

The power-on control output section 7 generates a control signal such as a power-on reset signal for a certain period in response to power-on of the power supply section 6. During the generation of the control signal, the window pulse generator 5 outputs a window pulse signal having a longer window length, and thereafter outputs a shorter window pulse signal.

The phase collision detecting section 4 detects whether or not a frame signal for writing to the memory section 1 exists in the window pulse signal, and supplies a detection signal to the phase adjusting section 2.

When it is detected that the write frame signal has entered the window pulse, the phase adjuster 2 shifts the phase of the received frame signal so as to shift the write frame signal out of the window of the window pulse signal. I do.

FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart thereof. 2, the same parts as those in FIG. 1 are indicated by the same reference numerals. The window pulse generator 5 generates two types of window pulse signals c and d based on the in-device frame signal b, and converts the two types of window pulse signals c and d by a power-on reset signal e. And a selection circuit 52 for selectively outputting.

The window pulse signals c and d are as shown in FIG.
As shown in (d), each has a pulse width of a certain period of time t1, t2 and t8, t9 before and after the in-device frame signal b, respectively, and (t1 + t2) <(t8 + t9).

The power-on reset circuit 7 responds to the power-on of the power supply section 6 as shown in FIG.
The low-level power-on reset signal e is generated by 7 and the selection circuit 52 selects the window pulse signal d having a long pulse width during the period t7 of the low-level power-on reset signal e. Selects a window pulse signal c having a short pulse width.

The selected window pulse signal f is input to the phase collision detector 4. The phase collision detecting section 4 detects whether or not the write frame signal i is included in the pulse of the window pulse signal f. If not, the phase selection circuit 22 selects the received frame signal h as it is and outputs the write frame signal h. i, and if it is included, the phase selection circuit 21 derives the phase of the received frame signal h as a write frame signal i via a phase inversion circuit 21 that shifts the phase by, for example, 180 degrees.

As shown in FIG. 3 (e), in response to power-on at the start of the line operation, the power-on reset circuit 7 outputs a low-level power-on reset signal e for a certain period t7.
Is output. During this time, the selection circuit 52 selects the window pulse signal d having a longer pulse width (t6) and supplies it to the phase collision detection unit 4.

The window pulse signal d has a pulse width t5 of the window pulse c, which is a phase collision detection area in an original steady state.
The position of the received frame signal h (the position of t3 shown in FIG. 3 (h)) where the phase collision is not normally detected by the phase collision detection unit 4 because the pulse width t6 is larger than the pulse width t6.
When jitter or fluctuation occurs and enters the original phase collision region (the pulse width t5 of the window pulse signal c of a short pulse), phase control is performed, and the phase of the write frame signal i jumps temporarily, causing an error. Is detected during such a power-on reset period, the state of the received frame signal h (the state shown in FIG. 3 (h)) is detected as a write frame signal i as shown in FIG. 3 (i). The phase is shifted by 180 degrees.

By doing so, the phase relationship between the subsequent write frame signal i and the in-device frame signal b is constantly maintained at the relationship between (b) and (i) in FIG. Therefore,
Even if the window pulse signal c having a short pulse width (t5) in a regular state is used thereafter, even if a phase shift of the received frame signal h occurs due to jitter or fluctuation, the write frame signal i falls within the range of the window pulse signal c. Penetration is extremely low, stable and error-free.

The phase of the received frame signal h is shifted by 180 degrees. This is because shifting by 180 degrees is the most stable. Ideally, a value close to it may be used.

FIG. 4 is a block diagram of another embodiment of the present invention, and the same parts as those in FIG. 2 are denoted by the same reference numerals. In this example, timing transfer is performed using an S / P (serial / parallel) conversion circuit 10, D-FFs 11, 13, a selector 14, and a P / S conversion circuit 15 instead of the FIFO memory unit 1 in FIG. The case of the method is shown.

The S / P conversion circuit 10 converts the received data signal into an S / P signal in synchronization with the received frame signal and the received clock signal.
After the conversion, the D-FF 11 latches the parallel output in synchronization with the inverted clock of the received clock signal by the inverter 12.

The D-FF 13 latches the latch output in synchronization with the reception clock signal. The selector 14 selects both the latch outputs of the D-FFs 11 and 13 in accordance with the detection result of the phase collision detection circuit 4, It is supplied to the P / S conversion circuit 15. The P / S conversion circuit 15 performs P / S conversion in synchronization with the internal clock signal and the internal frame signal to output data.

The configuration and operation of another circuit are described in FIG.
And the description thereof is omitted.

Also in such a configuration, the phase of the received data signal is determined by the D-FFs 10 and 11 using a window pulse signal having a margin at the time of power-on reset, so that jitter and fluctuations will occur in the subsequent steady state. And a stable and stable timing transfer can be realized.

[0035]

As described above, according to the present invention, a window pulse signal is generated from the window pulse generation circuit to indicate two types of phase collision areas at the time of power-on and at the time of steady power supply. By selectively outputting a long window pulse signal,
It is possible to determine the phase of the transmission line / device with a margin at the start of line operation, and even if the phase fluctuates due to jitter or fluctuation (wander), etc., it is possible to change the clock without error without controlling the transmission line phase. There is an effect that it can be made stable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram of a conventional timing transfer circuit.

FIG. 6 is a timing chart illustrating the operation of the block in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory part 2 Phase adjustment part 4 Phase collision detection part 5 Window pulse generation part 6 Power supply part 7 Power-on control output part (power-on reset circuit) 10 S / P conversion circuit 11, 13 D-FF 12 Inverter 14 Selector 15 P / S conversion circuit 21 180 degree phase inversion circuit 22 Phase selection circuit 51 Window pulse generation circuit 52 Selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/00 H04J 3/06

Claims (1)

(57) [Claims] 1. Serial-parallel conversion means for serially / parallel-converting received data in synchronization with a timing signal of the received data, and synchronizing the parallel received data with a positive-phase signal and a negative-phase signal of the timing signal of the received data. First and second latches respectively
Latching means, selecting means for selecting the outputs of the first and second latching means in accordance with a selection control signal, and parallel / serial converting means for performing parallel / serial conversion of the selected output in synchronization with a timing signal in the apparatus. In order to detect a conflict between the timing signal of the received data and the timing signal in the apparatus, first and second predetermined lengths of different lengths at risk of the conflict are detected.
Window pulse signal generating means for generating first and second window pulse signals respectively indicating a second period and a second period based on the in-apparatus timing signal, and the first and second window pulses during a certain period from power-on. A window pulse selecting means for selecting a window pulse for a long period of time from the signal and thereafter selecting a remaining window pulse, and detecting whether or not the reception timing signal has entered during the period of the selected window pulse. Means for generating the selection control signal.