JP4649819B2 - Manufacturing method of semiconductor integrated device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a manufacturing method of securely electrically separated plurality of the semiconductor device formed by arranging two-dimensionally or three-dimensionally integrated semiconductor device Is.
[0002]
[Prior art]
Along with the high integration and miniaturization of semiconductor devices, semiconductor integrated devices in which a plurality of semiconductor elements of the same type or a plurality of semiconductor elements of different types are integrated on a common substrate have been put into practical use.
In a semiconductor integrated device, it is necessary to electrically isolate the semiconductor devices from each other so that the semiconductor devices integrated on the common substrate function independently of each other.
[0003]
Therefore, in order to electrically isolate each semiconductor element of a semiconductor integrated element in which a plurality of semiconductor elements are integrated on a common substrate, the following element isolation structure has been conventionally employed.
As shown in FIG. 7, a conventional first element applied to a conventional semiconductor integrated element in which a first semiconductor element 14 and a second semiconductor element 16 are two-dimensionally arranged on a common GaAs substrate 12. The isolation structure 10 is provided with an element isolation region 18 in which specific ions are ion-implanted into the GaAs substrate 12 between the first semiconductor element 14 and the second semiconductor element 16 to increase resistance, and the first semiconductor element 14 and the second semiconductor element 16 are electrically separated (see US Pat. No. 6,392,256B1, FIG. 13a). FIG. 7 is a schematic cross-sectional view showing the configuration of the conventional first element isolation structure 10.
[0004]
Further, as shown in FIG. 8, the conventional second element isolation structure 20 is provided with an element isolation groove 22 between the first semiconductor element 14 and the second semiconductor element 16 to insulate the element isolation groove 22 from each other. An element isolation region 26 embedded with a film 24 is provided to electrically isolate the first semiconductor element 14 and the second semiconductor element 16. FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional second element isolation structure.
[0005]
Further, as shown in FIG. 9, the conventional third element isolation structure 30 has a reverse breakdown voltage characteristic due to a reverse pn junction between the common GaAs substrate 12 and the first semiconductor element 14 and the second semiconductor element 16, respectively. In this structure, the first and second semiconductor elements 14 and 16 are electrically separated from each other by providing a reverse pn junction isolation layer 32 utilizing the above. FIG. 9 is a schematic cross-sectional view showing a configuration of a conventional third element isolation structure.
[0006]
Further, as shown in FIG. 10, an element isolation structure in which a reverse pn junction isolation layer is provided to electrically isolate a semiconductor element is a semiconductor integrated circuit in which a second semiconductor element 42 is further provided on the first semiconductor element 14A. It can also be applied to elements. FIG. 10 is a schematic cross-sectional view showing another configuration of the conventional third element isolation structure.
That is, the element isolation structure 40 is provided in which another reverse pn junction isolation layer 44 is provided between the first semiconductor element 14A and the second semiconductor element 42. In this case, in order to form another first semiconductor element 14B, first, another reverse pn junction isolation layer is formed similarly to the stacked structure in which the second semiconductor element 42 is provided on the first semiconductor element 14A. A stacked structure in which the second semiconductor element 42 is provided on the first semiconductor element 14B is formed via 44, and then the stacked structure of the second semiconductor element 42 and another reverse pn junction isolation layer 44 are etched. By removing the first semiconductor element 14B, the first semiconductor element 14B is formed.
The first to third element isolation structures 10, 20, 30, and 40 can be applied not only to isolation of different types of semiconductor elements but also to isolation of the same type of semiconductor elements.
[0007]
[Patent Document 1]
US Pat. No. 6,392,256 B1 (FIG. 13a)
[0008]
[Problems to be solved by the invention]
However, the above-described conventional element isolation structure has the following problems although it is a relatively easy structure.
Since the first element isolation structure 10 requires a high injection voltage of several hundred kV or more at the time of ion implantation, there is a problem that the equipment cost and maintenance cost of the ion implantation apparatus increase. On top of that, since an implantation mask having a film thickness larger than a photoresist film used for normal lithography, for example, a film thickness of 4 μm or more is required, a special lithography process is necessary, and further, implantation is performed. There is a problem that the crystallinity of the region of the semiconductor substrate deteriorates. In addition, since the short circuit path of the current between the semiconductor elements is shielded by partially increasing the resistance and electrically isolated, it is impossible to completely insulate the semiconductor elements. It is also a problem that the withstand voltage is as low as 10 V or less. Therefore, in order to achieve complete electrical insulation between the semiconductor elements, some other method must be used in combination.
The second element isolation structure 20 has a high withstand voltage, but has a complicated insulating film filling process in the element isolation trench.
[0009]
Since the third element isolation structure 30 uses the reverse breakdown voltage characteristic due to the reverse pn junction, a slight current (saturation current) flows even in the reverse bias state. Therefore, in the amplification device that handles a minute current or a weak signal, Noise, crosstalk, poor grounding, etc. are major problems. Further, in element isolation using a reverse pn junction isolation layer, the withstand voltage is low, and the wiring design is restricted due to the restriction of the voltage application direction.
Further, another example 40 of the third element isolation structure has the same problem as the third element isolation structure 30, and after the first semiconductor element stacked structure is formed, the second semiconductor element stacked structure Since the semiconductor integrated device is manufactured by the procedure of forming the layer structure, the wafer is exposed to a growth temperature different in the number of types of the semiconductor device when forming the laminated structure, and there is a concern about the characteristic deterioration due to the temperature history. There will be restrictions. Furthermore, since it is necessary to stack device structures in the vertical direction, it is difficult to design the wiring structure of each semiconductor element, and it is difficult to perform lithography processing when forming each semiconductor element.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated device in which semiconductor elements are integrated in a state where the elements are isolated by an element isolation structure having good insulation characteristics.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a semiconductor integrated device according to the present invention (hereinafter referred to as a first inventive method) is to electrically separate a plurality of similar semiconductor devices from each other on a common substrate. A method of manufacturing a semiconductor integrated device that is two-dimensionally arranged on a substrate,
Forming an Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer on a common substrate;
Forming a laminated structure constituting the semiconductor element on the Al-containing layer;
The stacked structure and the Al-containing layer are etched to the common substrate, and each semiconductor element is physically separated from each other in the formation region of each semiconductor element, and the side surface of the Al-containing layer under each semiconductor element is exposed. Process,
A process of selectively steam-oxidizing the Al-containing layer to convert it into an Al-oxidized layer;
It is characterized by having .
[0016]
Further, another method for manufacturing a semiconductor integrated device according to the present invention (hereinafter referred to as a second method) arranges a plurality of types of semiconductor devices having different structures and functions on a common substrate in a two-dimensional manner. A method for manufacturing a semiconductor integrated device comprising:
Forming a first Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer on a common substrate;
Forming a first laminated structure constituting the first semiconductor element on the first Al-containing layer;
The first stacked structure and the first Al-containing layer are etched to form the first semiconductor element only in the formation region of the first semiconductor element, and the first Al-containing layer under the first semiconductor element Exposing the side surface of
A second Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer is formed on the common substrate , and then a second stacked layer that constitutes a second semiconductor element on the second Al-containing layer. Forming a structure;
The second laminated structure and the second Al-containing layer are etched to form the second semiconductor element only in the formation region of the second semiconductor element, and the second Al-containing layer under the second semiconductor element Exposing the side surface of
Hereinafter, similarly, forming the third, fourth,... Semiconductor elements on the common substrate and exposing the side surfaces of the third, fourth,.
The first, second, third, fourth,... Al-containing layers are selectively steam-oxidized and converted to an Al oxide layer.
[0019]
In the method for manufacturing a semiconductor integrated device according to the first to second inventions, an electrical separation layer can be formed by one-time treatment by water vapor oxidation, which is easy to process. Therefore, a semiconductor in which a plurality of semiconductor devices are integrated An integrated device can be easily manufactured.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail based on exemplary embodiments with reference to the accompanying drawings. It should be noted that the conductivity type, film type, film thickness, film forming method, and other dimensions shown in the following embodiments are examples for facilitating understanding of the present invention, and the present invention is limited to these examples. Is not to be done.
Embodiment 1 of Semiconductor Integrated Device
This embodiment is an example of an embodiment of a semiconductor integrated device according to the first invention, and FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor integrated device of this embodiment.
As shown in FIG. 1, a semiconductor integrated device 50 according to this embodiment includes a plurality of similar semiconductor elements 54 (in FIG. 1, two semiconductor elements 54A and 54B) on a common substrate, for example, a GaAs substrate 52. A semiconductor integrated device integrated with a display), for example, an electronic device such as HEMT or FET, or an optical device such as a surface emitting semiconductor laser device or a photodiode.
[0021]
Between the GaAs substrate 52 and the semiconductor elements 54A and 54B, 40 nm thick Al oxide layers (AlO _x ) 56 each functioning as an insulating film are individually interposed. The Al oxide layer 56 is a layer obtained by selectively steam-oxidizing Al of the AlAs layer. The Al oxide layer 56 is a complete insulating film and has a high breakdown voltage. For example, the breakdown voltage of an Al oxide layer obtained by oxidizing an AlAs film having a thickness of 40 nm is 30 V or more.
By interposing the Al oxide layer 56, the semiconductor elements 54A and 54B are electrically and reliably separated from each other as if they were semiconductor elements provided on the oxide insulating film. The Al oxide layer 56 has no directionality with respect to the applied voltage with respect to electrical insulation, and insulation is ensured regardless of which direction the voltage is applied, and the leakage current is small. Moreover, the mechanical strength of the Al oxide layer 56 is also high.
[0022]
Embodiment 1 of Manufacturing Method of Semiconductor Integrated Device
This embodiment is an example of an embodiment in which the semiconductor integrated device manufacturing method according to the first invention method is applied to the manufacture of the semiconductor integrated device of the first embodiment, and FIGS. FIG. 5 is a schematic cross-sectional view for each process in manufacturing the semiconductor integrated device of Embodiment 1 by the method of this embodiment.
First, as shown in FIG. 2A, an AlAs layer 58 having a thickness of 40 nm is epitaxially grown on a GaAs substrate 52 by MOCVD or the like, and then a laminated structure 59 constituting a semiconductor element 54 is formed on the AlAs layer 58. To do.
Next, as shown in FIG. 2B, the stacked structure 59 and the AlAs layer 58 are etched up to the GaAs substrate 52 to physically separate and form the semiconductor elements 54A and 54B on the semiconductor element formation region, and the AlAs layer. 58 side surfaces are exposed.
[0023]
Next, heat treatment is performed in a water vapor atmosphere at a temperature of 400 ° C. to perform water vapor oxidation of the AlAs layer 58, thereby selectively oxidizing the AlAs layer 58 as shown in FIG. Convert to layer 56. Although the oxidation time depends on the dimensions of the AlAs layer 58 such as the film thickness and the flat area, it is several minutes to several tens of minutes.
Thereby, the semiconductor element 50 in which the semiconductor elements 54A and 54B are electrically separated and integrated on the GaAs substrate 52 can be manufactured.
[0024]
The steam oxidation process is a relatively low temperature process at a processing temperature of 400 ° C., and the time is also a relatively short time of several minutes to several tens of minutes, and only one steam oxidation process is required. There is almost no influence of thermal history on the laminated structure.
[0025]
Embodiment 2 of a semiconductor integrated device
This embodiment is an example of an embodiment of a semiconductor integrated device according to the second invention, and FIG. 3 is a schematic cross-sectional view showing the configuration of the semiconductor integrated device of this embodiment.
As shown in FIG. 3, a semiconductor integrated device 60 according to the present embodiment includes a plurality of types of semiconductor elements such as a first semiconductor element 64 and a second semiconductor element 66 (on a GaAs substrate 62, for example. FIG. 3 shows a semiconductor integrated device in which two types of semiconductor devices are displayed.
Each of the first semiconductor element 64 and the second semiconductor element 66 is an electronic device such as a HEMT or FET, or an optical device such as a surface emitting semiconductor laser element or a photodiode.
[0026]
Between the GaAs substrate 62 and the first semiconductor element 64 and the second semiconductor element 66, 40 nm-thick Al oxide layers (AlO _x ) 68 functioning as insulating films are individually interposed. The Al oxide layer 68 is a layer obtained by steam-oxidizing the AlAs layer.
By interposing the Al oxide layer 68, the first semiconductor element 64 and the second semiconductor element 66 are mutually connected like a semiconductor element provided on the oxide insulating film, as in the first embodiment. It is securely separated electrically.
[0027]
Second Embodiment of Manufacturing Method of Semiconductor Integrated Device
This embodiment is an example of an embodiment in which the method for manufacturing a semiconductor integrated device according to the second invention is applied to the manufacture of the semiconductor integrated device of Embodiment 2, and FIGS. 4 (a) to 4 (d) FIG. 10 is a schematic cross-sectional view for each process when manufacturing the semiconductor integrated device of Embodiment 2 by the method of this embodiment.
First, as shown in FIG. 4A, a 40 nm-thickness AlAs layer 70 is epitaxially grown on a GaAs substrate 62 by MOCVD or the like, and then a first semiconductor element 64 is formed on the AlAs layer 70. The laminated structure 72 is formed.
Next, as shown in FIG. 4B, the first stacked structure 72 and the AlAs layer 70 are etched to the GaAs substrate 62 to physically place the first semiconductor element 64 in the formation region of the first semiconductor element 64. Then, the side surface of the AlAs layer 70 is exposed.
[0028]
Next, an AlAs layer 70 having a thickness of 40 nm is epitaxially grown on the GaAs substrate 62 in a region other than the region where the first semiconductor element 64 is formed by MOCVD or the like, and then a second semiconductor element 66 is formed on the AlAs layer 70. A second laminated structure 74 is formed. Subsequently, as shown in FIG. 4C, the second stacked structure 74 and the AlAs layer 70 are etched to the GaAs substrate 62, and the second semiconductor element 66 is formed on the formation region of the second semiconductor element 66. While physically separating and forming, the side surface of the AlAs layer 70 is exposed.
Next, heat treatment is performed in a steam atmosphere at a temperature of 400 ° C. to perform steam oxidation of the AlAs layer 70, thereby selectively oxidizing the AlAs layer 70 as shown in FIG. Convert to layer 68. The oxidation time depends on the dimensions of the AlAs layer 70 such as the film thickness and the flat area, but is between several minutes and several tens of minutes.
Through the above steps, the semiconductor integrated device 60 of the second embodiment can be manufactured.
[0029]
The steam oxidation treatment is performed at a relatively low processing temperature of 400 ° C. and for a relatively short time of several minutes to several tens of minutes, and the Al oxide layer 68 can be formed by one oxidation treatment. Therefore, the influence of the thermal history on the stacked structure of the first semiconductor element 64 and the second semiconductor element 66 hardly occurs.
[0030]
Embodiment 3 of Semiconductor Integrated Device
This embodiment is an example of an embodiment of a semiconductor integrated device according to the third invention, and FIG. 5 is a schematic cross-sectional view showing the configuration of the semiconductor integrated device of this embodiment.
As shown in FIG. 5, the semiconductor integrated device 80 according to the present embodiment includes a plurality of first semiconductor elements 84 (two first semiconductor elements in FIG. 1) on a common substrate, for example, a GaAs substrate 82. 84A and B), and at least one of the first semiconductor elements 84, for example, a second semiconductor element 86 formed by being stacked on the first semiconductor element 84A is integrated.
Between the GaAs substrate 82 and the first semiconductor elements 84A and 84B, an Al oxide layer (AlO _x ) 88 having a thickness of 40 nm functioning as an insulating film is individually interposed. In addition, an Al oxide layer (AlO _x ) 90 having a thickness of 40 nm that functions as an insulating film is interposed between the first semiconductor element 84A and the second semiconductor element 86. The Al oxide layer 88 and the Al oxide layer 90 are Al oxide layers obtained by selectively steam oxidizing the AlAs layer.
[0031]
By interposing the Al oxide layer 88, as in the first embodiment, the first semiconductor elements 84A and 84B are electrically and reliably connected to each other as if they were semiconductor elements provided on the oxide insulating film. It is separated. Further, by interposing the Al oxide layer 90, the first semiconductor element 84A and the second semiconductor element 86 are also electrically reliably separated from each other.
[0032]
Embodiment 3 of Manufacturing Method for Semiconductor Integrated Device
This embodiment is an example of an embodiment in which the method for manufacturing a semiconductor integrated device according to the third invention is applied to the manufacture of the semiconductor integrated device of Embodiment 3, and FIGS. 6 (a) to 6 (d) FIG. 11 is a schematic cross-sectional view for each process when manufacturing the semiconductor integrated device of Embodiment 3 by the method of this embodiment.
First, as shown in FIG. 6A, an AlAs layer 92 having a thickness of 40 nm is epitaxially grown on a GaAs substrate 82 by MOCVD or the like, and then a first semiconductor element 84 is formed on the AlAs layer 92. The laminated structure 94 is formed. Subsequently, an AlAs layer 96 having a thickness of 40 nm is epitaxially grown on the first laminated structure 94 by MOCVD or the like, and then a second laminated structure 98 constituting the second semiconductor element 86 is formed on the AlAs layer 96. .
[0033]
Next, as shown in FIG. 6B, the second stacked structure 98, the AlAs layer 96, the first stacked structure 94, and the AlAs layer 92 are etched to the GaAs substrate 82, so that the AlAs layer 92, the first The laminated structure 100 including the laminated structure 94, the AlAs layer 96, and the second laminated structure 98 is physically separated on the semiconductor element formation region of the GaAs substrate 82, and the side surfaces of the AlAs layers 92 and 96 are exposed.
Next, as shown in FIG. 6C, the second stacked structure 98 and the AlAs layer 96 are removed by etching from the stacked structure 100 on the formation region of the first semiconductor element 84B, and the first semiconductor element 84B is removed. And only the AlAs layer 92 is left.
Subsequently, heat treatment is performed in a steam atmosphere at a temperature of 400 ° C. to perform steam oxidation of the AlAs layers 92 and 96 to convert them into Al oxide layers 88 and 90, respectively, as shown in FIG. 6 (d). . The oxidation time depends on the dimensions (film thickness and plane area) of the AlAs layers 92 and 96, but is from several minutes to several tens of minutes.
Through the above steps, the semiconductor integrated device 80 of the third embodiment can be manufactured.
[0034]
In the above-described embodiment, an AlAs layer is used as the Al-containing layer. However, the present invention is not limited to the AlAs layer, and an AlGaAs layer having an Al composition of 0.9 or more can be used as the Al-containing layer.
Moreover, an InP substrate can be used as the substrate by using, as the Al-containing layer, an InAlAs layer having an Al composition that is lattice-matched to InP and having an Al composition of 0.8 or more.
[0035]
【The invention's effect】
According to the first and second invention methods , the Al-containing layer interposed between the substrate and the semiconductor element and between the semiconductor element and the semiconductor element is converted into an Al oxide layer by one water vapor oxidation treatment, and is electrically separated. A layer can be formed. As a result, a semiconductor integrated device in which a plurality of semiconductor devices of the same type or different types are integrated two-dimensionally or three-dimensionally in a state of being electrically separated reliably can be easily manufactured.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor integrated device according to Embodiment 1;
FIGS. 2A to 2C are schematic cross-sectional views for each process in manufacturing the semiconductor integrated device of Example 1 by the method of Example 1. FIG.
3 is a schematic cross-sectional view showing a configuration of a semiconductor integrated device according to Embodiment 2. FIG.
FIGS. 4A to 4D are schematic cross-sectional views for each process when manufacturing the semiconductor integrated device of Example 2 by the method of Example 2. FIG.
5 is a schematic cross-sectional view showing a configuration of a semiconductor integrated device according to Embodiment 3. FIG.
FIGS. 6A to 6D are schematic cross-sectional views for each process in manufacturing the semiconductor integrated device of Example 3 by the method of Example 3. FIG.
7 is a schematic cross-sectional view showing a configuration of a conventional first element isolation structure 10. FIG.
FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional second element isolation structure.
FIG. 9 is a schematic cross-sectional view showing a configuration of a conventional third element isolation structure.
FIG. 10 is a schematic cross-sectional view showing another configuration of the conventional third element isolation structure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 12 ... GaAs substrate, 14 ... 1st semiconductor element, 16 ... 2nd semiconductor element, 18 ... Element isolation region, 20 ... Conventional 2nd element isolation structure, 22 ... Element isolation groove, 24 …… Insulating film, 26 …… Element isolation region, 30 …… Conventional third element isolation structure, 32 …… Reverse pn junction isolation layer, 40 …… Another example of the conventional third element isolation structure, 42... Second semiconductor element 44. Another reverse pn junction isolation layer 50. Semiconductor integrated element according to Embodiment 1 52... GaAs substrate 54... Semiconductor element 56. , 58... AlAs layer, 59... Laminated structure, 60... Semiconductor integrated device of Embodiment 2 64... First semiconductor element 66... Second semiconductor element 68. 70... AlAs layer, 72... First laminated structure, 74... Second laminated structure, 80 ... Semiconductor integrated device according to the third embodiment, 82 ... GaAs substrate, 84 ... first semiconductor device, 86 ... second semiconductor device, 88, 90 ... Al oxide layer, 92 ... AlAs layer, 94 ... First laminated structure, 96... AlAs layer, 98... Second laminated structure, 100.

Claims (2)

A method for manufacturing a semiconductor integrated device, wherein a plurality of semiconductor devices of the same type are electrically separated from each other and two-dimensionally arranged on a common substrate,
Forming an Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer on a common substrate;
Forming a laminated structure constituting the semiconductor element on the Al-containing layer;
The stacked structure and the Al-containing layer are etched to the common substrate, and each semiconductor element is physically separated from each other in the formation region of each semiconductor element, and the side surface of the Al-containing layer under each semiconductor element is exposed. Process,
And a step of selectively steam-oxidizing the Al-containing layer to convert it into an Al oxide layer. A method of manufacturing a semiconductor integrated device in which a plurality of types of semiconductor devices having different configurations and functions are arranged two-dimensionally on a common substrate,
Forming a first Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer on a common substrate;
Forming a first laminated structure constituting the first semiconductor element on the first Al-containing layer;
The first stacked structure and the first Al-containing layer are etched to form the first semiconductor element only in the formation region of the first semiconductor element, and the first Al-containing layer under the first semiconductor element Exposing the side surface of
A second Al-containing layer of any one of an AlAs layer, an AlGaAs layer, and an InAlAs layer is formed on the common substrate, and then a second stack that constitutes the second semiconductor element on the second Al-containing layer. Forming a structure;
The second stacked structure and the second Al-containing layer are etched to form the second semiconductor element only in the formation region of the second semiconductor element, and the second Al-containing layer under the second semiconductor element Exposing the side surface of
Hereinafter, similarly, forming the third, fourth,... Semiconductor elements on the common substrate and exposing the side surfaces of the third, fourth,.
A method of selectively oxidizing the Al-containing layer of the first, second, third, fourth,... By steam to convert it into an Al oxide layer.

Images