JP4645047B2 - Shift register circuit, drive control method thereof, and drive control apparatus - Google Patents

Description

  The present invention relates to a shift register circuit, a drive control method thereof, and a drive control device, and more particularly to a shift register circuit, a drive control method thereof, and a drive control device which are suitable for application to a display device or an image reading device.

  In recent years, information devices such as computers, mobile phones, and portable information terminals, and imaging devices such as digital video cameras, digital still cameras, and scanners have been widely used. In such a device, display means such as a liquid crystal display (LCD), image reading means such as a photo sensor array, or imaging means are frequently used.

  For example, in an active matrix liquid crystal display device, display pixels (liquid crystal pixels) each having a pixel transistor made of a thin film transistor are arranged in a matrix, and the display pixels are connected in the column direction and the scanning lines connecting the display pixels in the row direction. For a display panel having a data line to be selected, each scanning line is sequentially selected by a scanning driver, and a predetermined signal voltage is applied to each data line by the data driver, so that a display pixel in the selected state is applied. By applying a signal voltage corresponding to the image information, the alignment state of the liquid crystal in each display pixel is controlled to display desired image information. Here, the scan driver is provided with a shift register circuit as a configuration for generating and outputting a scan signal for sequentially setting each scan line to a selected state.

  In addition, even in an image reading apparatus including a photosensor array configured by arranging photosensors (reading pixels) in a matrix, the photosensors in each row are sequentially driven when the photosensor is reset or read. A scan driver for setting the state is provided, and a shift register circuit for generating and outputting a drive signal is provided as in the case of the liquid crystal display device.

FIG. 12 is a circuit configuration diagram showing a schematic configuration of a shift register circuit in the prior art, and FIG. 13 is a timing chart showing a drive control operation of the shift register circuit in the prior art.
In the conventional shift register circuit, for example, as shown in FIG. 12, a plurality of stages of circuit blocks SB1, SB2, SB3,... (Hereinafter referred to as “circuit blocks SBs”; s is a positive integer) are connected in series. The shift signals SF1, SB2, SF3,... (Hereinafter referred to as “shift signal SFs”) from the circuit blocks SBs at each stage are sequentially input to the circuit block SB (s + 1) at the next stage. The external output signal OUT (s + 1) in the next stage circuit block SB (s + 1) is input as a signal, and the reset signals RS1, RS2, RS3,. It is configured to be input as a reset signal RSs ”.

  Here, as shown in FIG. 12, each circuit block SBs (for convenience, the circuit block SB1 will be described) includes, for example, a start pulse VST (or a previous stage circuit block SB (s-1) at the gate terminal. A shift signal SF (s-1)) is applied, and a field effect transistor T11P in which a power supply voltage VDD and a contact N11 are connected to a source terminal and a drain terminal, respectively, and a contact N11 is connected to a gate terminal. A field effect transistor T12P having a drain terminal connected to the supply line of the drive pulse V1 and a contact N12, and an external output signal OUT (s + 1) of the next stage circuit block SB (s + 1) to the gate terminal. A field-effect transistor T13P that is applied and has a source terminal and a drain terminal connected to a contact N11 and a ground voltage VSS, respectively, and a gate terminal to the next stage. A field effect transistor T14P to which the external output signal OUT (s + 1) of the circuit block SB (s + 1) is applied and the contact N12 and the ground voltage VSS are connected to the source terminal and the drain terminal, respectively, and the contact N11 And a capacitor C11 connected between the contact N12.

In such a circuit block SBs (SB1), the transistor T11P functions as a bootstrap capacitive charging transistor, the transistor T12P functions as an output transistor, and the transistors T13P and T14P function as discharge transistors. The contact N11 is connected to the gate terminal of the bootstrap capacitive charging transistor (transistor T21P) in the circuit block SB (s + 1) at the next stage, and the potential is applied as the shift signal SFs (SF1). Is output to the outside of the shift register circuit as an external output signal OUTs (OUT1).

Then, as shown in FIG. 13, the control operation of the shift register circuit SB1 having such a circuit configuration is as follows. First, at timing <t0>, a high level (for example, 5V) start pulse VST is applied to the first stage circuit block SB1. Is input, the transistor T11P is turned on, and the power supply voltage VDD is applied to the contact N11. As a result, the power supply voltage VDD is charged in the bootstrap capacitor C11, and when the charged voltage becomes equal to or higher than the threshold voltage (for example, 3 V) of the transistor T12P, the transistor T12P is turned on. At this time, since the drive pulse V1 is set to the low level, the potential VN12 of the contact N12 is maintained at the low level, and the external output signal OUT1 is not output from the circuit block SB1 (the low-level external output signal OUT1 is output). )

  Next, at the timing <t1>, when the drive pulse V1 is set to a high level and applied to the drain terminal of the transistor T12P, the gate voltage of the transistor T12P (the potential VN11 of the contact N11) is increased by the bootstrap phenomenon. Since the voltage charged to the capacitor C11 at the timing <t0> is boosted to a voltage obtained by adding the voltage of the high-level drive pulse V1, the transistor T12P is turned on in a substantially saturated state, whereby the contact N12 Since a voltage equivalent to the high-level drive pulse V1 is applied to the circuit block SB1, the high-level external output signal OUT1 is output from the circuit block SB1.

  At this time, the potential VN11 of the contact N11 boosted by the bootstrap phenomenon is input to the next-stage (second-stage) circuit block SB2 as the high-level shift signal SF1, so that the first-stage circuit block described above Similar to the operation in SB1, the bootstrap capacitance charging transistor (transistor T21P) is turned on, the power supply voltage VDD is charged in the bootstrap capacitance C21, and the charging voltage is the threshold of the output transistor (transistor T22P). When the value voltage (for example, 3 V) or more is reached, the transistor T22P is turned on.

  At timing <t1>, when the drive pulse V1 is set to low level after the high-level external output signal OUT1 is output from the circuit block SB1, the transistor T12P maintains the on state, but the contact N12 The potential is set to a low level and the output of the external output signal OUT1 is shut off (a low-level external output signal OUT1 is output).

  Next, at timing <t2>, when the drive pulse V2 is set to a high level, the gate voltage of the transistor T22P of the circuit block SB2 (the potential VN21 of the contact N21) is boosted by the bootstrap phenomenon, so A voltage equivalent to the level driving pulse V2 is applied, the high output signal OUT2 is output from the circuit block SB2, and the potential VN21 of the contact N21 is the next as the high level shift signal SF2. It is input to the stage (third stage) circuit block SB3.

  At this time, the potential VN22 (high-level external output signal OUT2) of the contact N22 is input to the previous stage (first stage) circuit block SB1 as the high-level reset signal RS1, so that the transistors T13P and T14P are turned on. Since the operation is performed, the contact N11 and the contact N12 are connected to the ground voltage VSS, the potentials VN11 and VN12 become equal to each other, and the charge accumulated in the capacitor C11 is initialized (reset).

  At timing <t2>, when the drive pulse V2 is set to low level after the high-level external output signal OUT2 is output from the circuit block SB2, the transistor T22P is kept on, but the contact N22 The potential is set to the low level, and the output of the external output signal OUT2 is cut off (the low-level external output signal OUT2 is output). As a result, the low-level reset signal RS1 is input to the previous (first) circuit block SB1, so that the transistors T13P and T14P are turned off, and the potentials VN11 and VN12 of the contact N11 and the contact N12 are low. Is kept in the floating state (floating state).

  Hereinafter, as shown in FIG. 13, by repeating the same operation for each circuit block SBs in the next stage (third stage) and thereafter, the external output signal OUTs is sequentially sent from each circuit block SBs at a predetermined timing. In addition to the output, the shift signal SFs is output to the block SB (s + 1) at the next stage of the circuit block SBs, and the shift signal SF (s-1) is output to the block SB (s-1) at the previous stage. .

By applying such a shift register circuit to a scanning driver of a display device or an image reading device, for example, display pixels arranged in a display panel or photosensors arranged in a photosensor array In accordance with an external output signal (corresponding to a scanning signal or a selection signal) output from the circuit block, a line-sequential selection operation is performed in which a selection state is sequentially set for each row and a display operation or an image reading operation is executed. .
The shift register circuit and the drive control method thereof as shown in FIGS. 12 and 13 are described in detail in, for example, Patent Document 1 and the like.

JP 2003-101406 A (pages 5 to 6, FIGS. 1 and 3)

However, the shift register circuit as described above has the following problems.
FIG. 14 is a timing chart for explaining a problem of the shift register circuit in the prior art. Here, a description will be given while appropriately comparing with the above-described conventional shift register circuit drive control method (FIG. 13).

  In the shift register circuit as shown in FIG. 12, as shown in FIG. 13, in a specific circuit block SBs (for example, SB2), a predetermined timing <t (s-1)> (s is a positive integer) ), The high level shift signal SF (s-1) is input from the preceding circuit block SB (s-1), so that the bootstrap capacitor charging transistor (transistor T21P) is turned on, and the capacitor (C21). Then, the predetermined charge is accumulated, and then the drive pulse V2 is set to the high level at timing <ts>, so that the high level external output signal OUTs (OUT2) is only once by the bootstrap phenomenon during the scanning period. Is output. At this time, the reset signal RS (s-1) (RS1) is output to the previous circuit block SB (s-1) (SB1), and the next circuit block SB (s + 1) (SB3). Shift signal SFs (SF2) is output.

  Here, as described above, the initialization operation of the potentials VN11 and VN12 of the contacts N11 and N12 in the previous circuit block SB (s-1) (for example, SB1) is performed by the reset signal RS (s− from the circuit block SBs. 1) is executed only during the input period, and in the subsequent operation period, the potentials VN11 and VN12 of the contacts N11 and N12 are always held in the low-level floating state.

  Therefore, as shown in FIG. 14, every time the drive pulse V1 supplied to the odd-numbered circuit blocks SB3, SB5... Is set to the high level (that is, timing <t3>, <t5>,... ) Due to the gate-drain capacitance of the transistor T12P in the first stage circuit block SB1 that has previously output the external output signal OUTs, the gate voltage of the transistor T12P (the potential VN11 of the contact N11) fluctuates to the high level side. The transistor T12P is turned on slightly, the potential VN12 of the contact N12 is changed, and the external output signal OUT1 having a signal level slightly higher than the original low level state is output.

As shown in FIG. 14, such a fluctuation in the signal level of the external output signal OUTs occurs every time the drive pulse V2 is set to a high level (that is, timing <t4>,<t6>,.
Therefore, when the shift register circuit as described above is applied to a scan driver for driving a display panel or a photosensor array, there is a problem that display image quality may be deteriorated or an image reading operation may malfunction. Had.

  In view of the above problems, the present invention provides a shift register circuit having a plurality of stages of circuit blocks that perform a shift operation and a signal output operation using a change in the level of a drive pulse. Shift register circuit capable of sequentially outputting an external output signal having a stable signal level for each circuit block of each stage without being affected by the level change of the drive pulse applied to define the signal level of An object of the present invention is to provide a drive control method including the shift register circuit.

The invention according to claim 1 includes a plurality of stages of signal holding means connected in series, and outputs an output signal from each of the signal holding means based on an input signal sequentially input to the signal holding means of each stage. In the shift register circuit that sequentially outputs, each of the signal holding means includes at least an input control unit that captures the input signal at a first operation timing, and a signal of the input signal that is captured at the first operation timing. An output control unit that outputs the output signal having the first signal level at a second operation timing based on the level; and the output signal control unit that determines the second signal level from the output control unit at a third operation timing. and a signal level determination unit for outputting an output signal, respectively, the signal period of the pulse signal are the same, and, as the pulse signal each other do not overlap in time The first to third operation timings are defined by a plurality of types of control clocks selected from a plurality of set drive pulse groups, and the output control unit is at least on the one end side of the current path. The control clock for defining the operation timing is supplied, the first switch means having the output signal output contact connected to the other end side, and a predetermined power supply voltage is applied to one end side of the current path A second switch means connected to the output contact on the other end side, and the signal level determination unit is configured to apply a first control voltage applied to a control terminal of the first switch means, and The second control voltage applied to the control terminal of the second switch means is periodically determined at signal levels having opposite polarities, and the signal level determination unit is at least on one end side of the current path. The control clock for defining the third operation timing is supplied, the third switch means having the control terminal of the first switch means connected to the other end side, and the predetermined switch on one end side of the current path And the fourth switch means connected to the control terminal of the second switch means on the other end side, and the control terminals of the third and fourth switch means include The control clock defining the third operation timing is commonly applied.

In the first aspect of the present invention , the output control unit is supplied with at least the control clock for defining the second operation timing on one end side of the current path, and the output contact of the output signal on the other end side. And a second switch means to which a predetermined power supply voltage is applied to one end side of the current path and the output contact is connected to the other end side. The level determination unit is configured so that the first control voltage applied to the control terminal of the first switch means and the second control voltage applied to the control terminal of the second switch means have opposite polarities. It is characterized in that the signal level is periodically determined.

According to the first aspect of the present invention , the signal level determining unit is supplied with at least the control clock for defining the third operation timing on one end side of the current path, and the first switch on the other end side. A third switch means to which the control terminal of the means is connected; and a predetermined power supply voltage is applied to one end side of the current path and a control terminal of the second switch means is connected to the other end side. 4, and the control clock defining the third operation timing is commonly applied to the control terminals of the third and fourth switch means.

According to a second aspect of the present invention , in addition to the third and fourth switch means, the signal level determining unit is further supplied with the control clock defining the first operation timing on one end side of the current path. And the fifth switch means having the control terminal of the second switch means connected to the other end side, the predetermined power supply voltage is applied to one end side of the current path, and the And a sixth switch means connected to a control terminal of the second switch means, and the control clock defining the first operation timing is commonly applied to the control terminals of the fifth switch means. It is characterized by.

According to a third aspect of the present invention , the input control unit has at least one input contact of the input signal connected to one end of the current path and the control terminal of the first switch means connected to the other end. The control device further includes seventh switch means for supplying the control clock for defining the first operation timing to the control terminal.

According to a fourth aspect of the present invention , the signal level determining unit sets the second control voltage to the first control so as to hold the second switch means in a non-conductive state at the second operation timing. Voltage control means for determining a signal level having a polarity opposite to that of the voltage is provided.
According to a fifth aspect of the present invention , the voltage control means is a capacitive element connected between a control terminal of the second switch means and a predetermined power supply voltage.

According to a sixth aspect of the present invention , the voltage control means has a control terminal of the second switch means connected to one end side of the current path and the predetermined power supply voltage connected to the other end side. It is the 8th switch means to which the said output contact was connected.
The invention according to claim 7 is characterized in that at least the first to eighth switch means are n-channel field effect transistors.

The invention according to claim 8 is characterized in that at least the first to eighth switch means are thin film transistors using an amorphous silicon semiconductor.
According to a ninth aspect of the present invention , the plurality of stages of signal holding means extract the output signal from the signal holding means of each stage based on the signal level of the input signal input to the signal holding means of the first stage. At the same time, the output signal is sequentially output to the signal holding means in the next stage as a shift signal.

The invention according to claim 10 includes a plurality of stages of signal holding means connected in series, and outputs an output signal from each of the signal holding means based on an input signal sequentially input to the signal holding means of each stage. In the drive control method of the shift register circuit that sequentially outputs , each of the signal holding means includes at least an input control unit that captures the input signal at the first operation timing, and the above-described capture that is captured at the first operation timing. Based on the signal level of the input signal, an output control unit that outputs the output signal having the first signal level at the second operation timing, and from the output control unit to the second signal level at the third operation timing. A signal level determination unit that outputs the determined output signal, and each of the pulse signals has the same signal period, and the pulse signals overlap each other in time. The first to third operation timings are defined by a plurality of types of control clocks selected from a plurality of drive pulse groups set so as not to occur, and the output control unit is at least one end side of the current path The control clock defining the second operation timing is supplied to the first switch means having the output signal output contact connected to the other end, and a predetermined power supply voltage to the one end of the current path And a second switch means connected to the output contact on the other end side, and the signal level determination unit is applied to a control terminal of the first switch means. The control voltage and the second control voltage applied to the control terminal of the second switch means are periodically determined at signal levels having opposite polarities, and the signal level determination unit includes at least: A third switching means having the control clock defining the third operation timing supplied to one end of the flow path and having a control terminal of the first switching means connected to the other end; a current path; And a fourth switch means to which the predetermined power supply voltage is applied to one end side and a control terminal of the second switch means is connected to the other end side, and the third and fourth switches The control clock defining the third operation timing is commonly applied to the control terminals of the means, and the step of taking in the input signal at the first operation timing and the input at the first operation timing based on the signal level of the input signal, and outputting the output signal having the first signal level at the second operation timing, the in the third operation timing the And periodically outputting the output signal determined at a signal level of 2 .

The invention according to claim 11 is characterized in that the second control voltage is determined at a signal level having a polarity opposite to that of the first control voltage at the second operation timing.

According to a twelfth aspect of the present invention, there is provided a drive control device including a shift register circuit that sequentially outputs a scanning signal for driving pixels in each row with respect to a pixel array in which a plurality of pixels are two-dimensionally arranged. The register circuit includes a plurality of stages of signal holding means connected in series,
Each of the signal holding means has a second operation timing based on at least an input control unit that captures an input signal at a first operation timing, and a signal level of the input signal that is captured at the first operation timing. An output control unit that outputs an output signal having a first signal level, and a signal level determination unit that outputs the output signal determined from the output control unit to the second signal level at a third operation timing; And a plurality of types of control clocks selected from a plurality of drive pulse groups , each of which has the same signal period of the pulse signals and is set so that the pulse signals do not overlap in time. The first to third operation timings are defined, and the output control unit defines the second operation timing at least on one end side of the current path. A first switch means having an output contact of the output signal connected to the other end side, a predetermined power supply voltage is applied to one end side of the current path, and the other end side And a second switch means to which an output contact is connected, wherein the signal level determining unit is a first control voltage applied to a control terminal of the first switch means, and the second switch means. The second control voltage applied to the control terminal is periodically determined to be signal levels having opposite polarities, and the signal level determination unit is configured to provide the third operation timing at least on one end side of the current path. Is supplied with the control clock, the third switch means having the control terminal of the first switch means connected to the other end, and the predetermined power supply voltage applied to one end of the current path. And the other end And a fourth switch means to which a control terminal of the second switch means is connected, and the control clock defining the third operation timing is provided at the control terminals of the third and fourth switch means. There is applied to the common, the input signal input to the first stage of the signal holding unit while shifting sequentially the following stages of the signal holding unit, based on the output signal output from each of said signal holding means The scanning signal is generated.

13. The drive control device according to claim 12 , wherein each of the drive control devices has a plurality of drives set so that pulse signals have the same signal period and the pulse signals do not overlap with each other in time. the plurality of types of control clock selected from group of pulses, the first to third operation timing of that are specified.
13. The drive control device according to claim 12 , wherein the output control unit is supplied with at least the control clock that defines the second operation timing on one end side of a current path and the output signal on the other end side. A first switch means connected to the output contact; and a second switch means to which a predetermined power supply voltage is applied to one end of the current path and the output contact is connected to the other end. The signal level determining unit is configured to obtain a first control voltage applied to a control terminal of the first switch means and a second control voltage applied to a control terminal of the second switch means. The signal levels having opposite polarities are periodically determined at the timing of 3 .

13. The drive control device according to claim 12 , wherein the signal level determination unit sets the second control voltage to the first so as to hold the second switch means in a non-conductive state at the second operation timing. The signal level may be determined to have a polarity opposite to the control voltage.
Further, in the drive control device, each of the pixels two-dimensionally arranged in the pixel array includes pixel selection means for holding the pixel in a selected state based on the scanning signal, the pixel selection means, The first and second switch means provided in the signal holding means may be constituted by field effect thin film transistors having the same channel polarity.

13. The drive control device according to claim 12 , wherein the pixels two-dimensionally arranged in the pixel array are display pixels, and the drive control device is based on the output signals output from each of the signal holding means. The scanning signal generated in this manner may be output for each row of the pixel array so that the display pixels for each row are set to a selected state for writing predetermined display data.

13. The drive control device according to claim 12 , wherein the pixels two-dimensionally arranged in the pixel array are read pixels, and the drive control device is based on the output signals output from the signal holding means. The scanning signal generated in this manner may be output for each row of the pixel array, so that the read pixels for each row are set to a selected state for reading a predetermined subject image.

  The shift register circuit and the drive control method thereof according to the present invention can be applied to a scanning driver (drive control device) of a display device or an image reading device, and each input signal is sequentially shifted to the next stage while each stage is shifted. In the shift register circuit having a plurality of stages of signal holding blocks (signal holding means) for sequentially outputting output signals to each other, the signal holding blocks of each stage have the same signal period of the pulse signals and the pulse signals mutually. Are supplied with a plurality of types of control clocks (first to third control clocks) selected from a plurality of drive pulse groups set so that they do not overlap in time, and the input control unit performs the first control. The input signal is taken in at the first operation timing specified by the clock, and is high level by the output control unit at the second operation timing specified by the second control clock. The first signal level output signal is output, and the output signal determined at the low level (second signal level) by the signal level determination unit at the third operation timing defined by the third control clock is output. It is configured to output periodically.

  Here, the input control unit, the output control unit, and the signal level determination unit are all configured by field effect thin film transistors (first to seventh switch means) having the same channel polarity. And first and second switch means connected in series between at least a second control clock supply contact and a low potential power supply (ground voltage; predetermined power supply voltage). The output signal is taken out from the connection contact of the two switch means, and the first and second control voltages applied to the respective control terminals of the first and second switch means are mutually signaled at the third timing. The signal level is periodically inverted and determined while maintaining a relationship in which the levels have opposite polarities.

  This shortens the period during which the first and second control voltages are in the floating state at the third timing (the output signal non-output state) other than the second timing at which the high-level output signal is output. Thus, by alternately and deterministically turning on the first and second switch means, the signal level of the output signal can be periodically determined to the low level side, so the first caused by the floating state. In addition, it is possible to prevent malfunction of the second switch means and output an external output signal (output signal) having a stable signal level.

  In addition, it is possible to avoid a state in which the same potential (signal level of the same polarity) is continuously applied to the gate terminals (control terminals) of the thin film transistors constituting the first and second switch means. Even when the means is constituted by, for example, a thin film transistor using an amorphous silicon semiconductor, deterioration of the threshold voltage characteristic of the thin film transistor due to carriers trapped in the semiconductor layer can be suppressed. It is possible to output an external output signal (output signal) having a stable signal level by suppressing a decrease in drive capability of the switch means due to voltage shift (fluctuation).

  The signal level determining unit for setting the first and second control voltages for controlling the operating states of the first and second switch means constituting the output control unit includes, for example, at least the third control clock. A third switch means connected between the supply contact and the control terminal of the first switch means, and a fourth switch connected between the low potential power supply (ground voltage) and the control terminal of the second switch means. And the third and fourth switch means can be applied to the control terminals of the third and fourth switch means in common. In addition, fifth and sixth switch means connected in series between the supply contact of the first control clock and the low potential power supply (ground voltage), the fifth and sixth switch means The output signal is extracted from the connection contact of , The control terminal of the second switch means is connected to the control terminal of the fifth and sixth switch means, it is possible to first control clock applies a commonly applied configuration.

  As a result, at the third timing (including the first timing) other than the second timing at which the high-level output signal is output from the output control unit, the voltage is applied to each control terminal of the first and second switch means. The first and second control voltages can be controlled such that the signal levels are periodically inverted and determined while maintaining a relationship in which the signal levels are opposite to each other.

  In addition, the signal level determination unit has, for example, one end side of the control terminal of the second switch means so as to definitely turn off the second switch means at the second operation timing when the high level output signal is output. In addition, it may have a configuration provided with voltage control means including a capacitive element and a thin film transistor (eighth switch means) whose other end side is connected to a low potential power supply (ground voltage).

  According to this, even when the potential of the connection contact of the first and second switch means rises due to the output of the high level output signal at the second operation timing, the second switch means. The second control voltage applied to the control terminal can be determined at a predetermined signal level to suppress fluctuations, so that the second switch means can be definitely turned off, and the output signal Signal level degradation can be suppressed.

The drive control device according to the present invention is a scanning driver for a display device such as a liquid crystal display device or an organic EL display, or an image reading device such as a fingerprint reader, and includes the above-described shift register circuit. Have.
According to this, the input control unit constituting the signal holding block of each stage of the shift register circuit captures the input signal at the first operation timing, and the output control unit outputs the high level output signal at the second operation timing. In addition, since the output signal determined at the low level at the third operation timing other than the second timing by the signal level determination unit can be periodically output, the output signal non-output period (third timing) The signal level of the output signal can be periodically determined to the low level side, and a scanning signal (output signal) having a stable signal level can be output. Therefore, it is possible to stabilize the selection state of the display pixel and the reading pixel, execute a good image display operation and an image reading operation, and improve the display image quality and suppress the reading malfunction.

  In addition, each pixel constituting the pixel array includes, for example, a liquid crystal display pixel including a pixel transistor as a pixel selection unit, a self-luminous pixel including a pixel driving circuit, and a reading pixel including a photosensor having a double gate transistor structure. The switch means constituting these pixel selection means and the switch means constituting each signal holding block of the shift register circuit are constituted by field effect thin film transistors having the same channel polarity, A conductive layer (electrode layer), an insulating layer, or a semiconductor layer formed by the same manufacturing process can be applied to an insulating substrate such as the same glass substrate.

Hereinafter, a shift register circuit, a drive control method thereof, and a drive control apparatus according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
First, an overall configuration of a shift register circuit according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram showing a first embodiment of a shift register circuit according to the present invention. Here, for convenience of explanation, among the signal holding blocks (signal holding means) of a plurality of stages (n stages; n is an integer of 4 or more) constituting the shift register circuit, for convenience, the <k> stage to <k + 3 Only the four stages of> stage (1 ≦ k, k + 3 ≦ n) are shown and described.

  As shown in FIG. 1, the shift register circuit according to the present embodiment includes a plurality of stages of signal holding blocks RSA (k) to RSA (k + 3) having a signal holding function equivalent to that of a flip-flop circuit. Each of the holding blocks RSA (k) to RSA (k + 3) has a configuration in which an input terminal IN and an output terminal (output contact) OUT are sequentially connected in series, and each stage of the signal holding blocks RSA (k) to RSA (k + 3) Output signal (the signal level of the output terminal OUT) is taken out as the external output signals GS (k) to GS (k + 3) of the shift register circuit, and also to the signal holding blocks RSA (k + 1) to RSA (k + 4) in the next stage. It is configured to be supplied as a shift signal.

  Each of the signal holding blocks RSA (k) to RSA (k + 3) has three types of control clocks CKA, CKB, and CKC (each having a different phase) according to the stage number of the signal holding block (which stage is). The clock terminals TA, TB, and TC are individually supplied with a combination of any of the four types of drive pulses CK1 to CK4. Each of the signal holding blocks RSA (k) to RSA (k + 3) includes a power supply terminal VL to which a low-potential-side power supply voltage (ground voltage) Vss is commonly supplied.

Next, a specific circuit configuration of each signal holding block applied to the shift register circuit according to the present embodiment will be described with reference to the drawings.
FIG. 2 is a circuit configuration diagram showing a specific example of a signal holding block applied to the shift register circuit according to the present embodiment. Here, in order to correspond to the configuration of the shift register circuit shown in FIG. 1, the circuit configuration of the signal holding block at the <k> stage will be described.

As shown in FIG. 2, the signal holding block RSA (k) has seven field effect thin film transistors Tr11 to Tr17 as a basic configuration.
Specifically, the external output signal GS (k−1) from the signal holding block RSA (k−1) at the previous stage (in the case of the signal holding block RSA (1) at the first stage, the start signal ST; And a source terminal and a drain terminal are connected between the input terminal IN and the contact Na, and a control clock CKC (first control clock) is supplied. A source terminal and a drain terminal are connected between the thin film transistor Tr11 (seventh switching means) whose gate terminal is connected to the clock terminal (supply contact) TC and the clock terminal TC and the contact Nb, and the gate is connected to the clock terminal TC. A thin film transistor Tr16 (fifth switch means) to which the terminal is connected is connected between the power supply terminal VL to which the ground voltage Vss is supplied and the contact Nb. A thin film transistor Tr17 (sixth switch means) having a terminal and a drain terminal connected, and a gate terminal connected to the input terminal IN, and a clock terminal (supply contact) TB to which a control clock CKB (third control clock) is supplied The source terminal and the drain terminal are connected between the contact Na and the thin film transistor Tr14 (third switch means) whose gate terminal is connected to the clock terminal TB, and the source terminal and the power supply terminal VL are connected between the contact Nb and the power supply terminal VL. A thin film transistor Tr15 (fourth switch means) having a drain terminal connected and a gate terminal connected to the clock terminal TB, a clock terminal (supply contact) TA to which a control clock CKA (second control clock) is supplied, and an output A source terminal and a drain terminal are connected between the terminal OUT, and a gate terminal is connected to the contact Na. The connected thin film transistor Tr12 (first switch means), the thin film transistor Tr13 (second switch) having the source terminal and the drain terminal connected between the output terminal OUT and the power supply terminal VL and the gate terminal connected to the contact Nb. Means) and a capacitor CA connected between the contact Na and the output terminal OUT.

Here, the thin film transistor Tr11 constitutes an input control unit according to the present invention, the thin film transistors Tr12 and Tr13 constitute an output control unit according to the present invention, and the thin film transistors Tr14 to Tr17 serve as signal level determination units according to the present invention. It is composed.
Note that the thin film transistors Tr11 to Tr17 constituting the signal holding block RSA (k) described above are all the same type (here, n-channel type) thin film transistors (here, n-channel type) using an amorphous silicon semiconductor formed on an insulating substrate. It is comprised by TFT; Thin Film Transistor. Further, the capacitor CA is appropriately set according to the gate-source capacitance of the thin film transistor Tr12. If the gate-source capacitance has an appropriate capacitance value, the capacitor CA is not provided. Also good.

  In the signal holding block RSA (k), the control clocks CKA, CKB, CKC individually supplied to the clock terminals TA, TB, TC are, for example, the signal holding block RSA (k) 1, 5, 9, (K = 4 × u + 1: u = 0, 1, 2, 3,...) In the case of the signal holding block in the stage, the driving pulse CK1 is supplied to the clock terminal TA as the control clock CKA. Then, the drive pulse CK2 is supplied as the control clock CKB to the clock terminal TB, and the drive pulse CK4 is supplied as the control clock CKC to the clock terminal TC.

  Further, when the signal holding block RSA (k) is a signal holding block in the second, sixth, tenth,... (K = 4 × u + 2) stage, a driving pulse as a control clock CKA is supplied to the clock terminal TA. CK2 is supplied, the drive pulse CK3 is supplied as the control clock CKB to the clock terminal TB, and the drive pulse CK1 is supplied as the control clock CKC to the clock terminal TC.

  Further, when the signal holding block RSA (k) is a signal holding block at the third, seventh, eleventh,... (K = 4 × u + 3) stage, a driving pulse as a control clock CKA is supplied to the clock terminal TA. CK3 is supplied, the drive pulse CK4 is supplied as the control clock CKB to the clock terminal TB, and the drive pulse CK2 is supplied as the control clock CKC to the clock terminal TC.

  Further, the signal holding block RSA (k) is a signal holding block in the 4, 8, 12,... (K = 4 × (u + 1): s = 0, 1, 2, 3,...) Stage. In some cases, the drive pulse CK4 is supplied to the clock terminal TA as the control clock CKA, the drive pulse CK1 is supplied to the clock terminal TB as the control clock CKB, and the drive pulse CK3 is supplied to the clock terminal TC as the control clock CKC. Supplied.

That is, when the remainder x obtained by dividing the stage number <k> of the signal holding block by 4 is 1 to 3 at the clock terminal TA, the number of the remainder x (x = 1, 2, 3) is determined. Drive pulses CKx (= CK1, CK2, CK3) are supplied, respectively. When the remainder x is 0, the drive pulse CK4 is supplied. Further, when the remainder y obtained by dividing the number obtained by adding 1 to the stage number <k> of the signal holding block by 4 is 1 to 3 at the clock terminal CKB, the number of the remainder y (y = 1, 2). 3), the drive pulse CKy (= CK1, CK2, CK3) is supplied, and when the remainder y is 0, the drive pulse CK4 is supplied. Furthermore, when the remainder z obtained by dividing the number obtained by adding 3 to the stage number <k> of the signal holding block by 4 is 1 to 3 at the clock terminal CKC, the number of the remainder z (z = 1, 2). 3), the drive pulse CKz (= CK1, CK2, CK3) is supplied, and when the remainder z is 0, the drive pulse CK4 is supplied.
Here, the drive pulses CK1 to CK4 are pulse signals that are sequentially set to a high level in a predetermined cycle without overlapping each other in time, as will be described in detail in a drive control operation (see FIG. 3) described later. is there.

Next, the operation of each thin film transistor constituting the signal holding block as described above and the change in potential at each terminal and contact will be described. Here, description will be made with reference to the signal holding block RSA (k) shown in FIG.
In the signal holding block RSA (k) having the above-described configuration, the thin film transistor Tr11 is turned on when the high-level (“H”) control clock CKC is supplied to the clock terminal TC. In synchronization with the supply timing, a high-level or low-level input signal (start signal ST or external output signal GS (k−1) of the signal holding block RSA (k−1) in the previous stage) is input to the input terminal IN. By supplying, the potential (first control voltage) VNa of the contact Na is set based on the signal level.

  Similarly to the thin film transistor Tr11, the thin film transistor Tr16 is turned on when the high level control clock CKC is supplied. On the other hand, the thin film transistor Tr17 has a high level input signal (external output signal GS ( k-1)) is turned on when supplied, so that the potential (second control voltage) VNb of the contact Nb is the ground voltage Vss supplied to the power supply terminal VL when the input signal is at a high level. Is set to a low level based on.

The thin film transistor Tr12 is turned on when the potential VNa of the contact Na is at a high level, while the thin film transistor Tr13 is turned on when the potential VNb of the contact Nb is at a high level. When the potential VNb of the contact Nb is high level, the low level (second signal level) based on the ground voltage Vss is set regardless of the potential VNa of the contact Na, and the potential VNb of the contact Nb is low level. In addition, the high level (first signal level) based on the signal level of the control clock CKA is set only when the high level control clock CKA is supplied during the period when the potential VNa of the contact Na is at the high level. Is done.
Further, since the thin film transistors Tr14 and Tr15 are turned on when the high-level control clock CKB is supplied, when the control clock CKB is at the high level, the potential VNa of the contact Na becomes the signal level of the control clock CKB. The potential VNb of the contact Nb is set to a low level based on the ground voltage Vss.

  Here, the drive pulses CK1 to CK4 individually supplied as the control clocks CKA to CKC to the clock terminals TA to TC are sequentially set to a high level without overlapping each other as shown in FIG. Since the pulse signal is set, first, only the control clock CKB supplied to the clock terminal TB is set to the high level, and the control clocks CKA and CKC supplied to the other clock terminals TA and TC are set to the low level. Accordingly, the thin film transistors Tr14 and Tr15 are turned on, the potential VNa of the contact Na is set to a high level based on the high level control clock CKB, and the potential VNb of the contact Nb is set to a low level based on the ground voltage Vss. As a result, the thin film transistor Tr12 is turned on and the thin film transistor Tr13 is turned off, so that the low level external output signal GS (k) based on the low level control clock CKA is output from the output terminal OUT.

  Next, only the control clock CKC supplied to the clock terminal TC is set to the high level, the control clocks CKA and CKB supplied to the other clock terminals TA and TB are set to the low level, and the high level is synchronized with this timing. By supplying a level input signal (external output signal GS (k−1)), the thin film transistors Tr11, Tr16 and Tr17 are turned on, and the potential VNa of the contact Na is set to a high level based on the high level input signal. Since the potential VNb of the contact Nb is held at a low level based on the ground voltage Vss, the thin film transistor Tr12 is turned on, the thin film transistor Tr13 is turned off, and the low level control is performed from the output terminal OUT. A low-level external output signal GS (k) based on the clock CKA is output. That. Here, the potential difference between the potential VNa (high level) of the contact Na and the potential (low level) of the output terminal OUT (that is, the gate-source potential of the thin film transistor Tr12) is the capacitor CA and the gate-source of the thin film transistor Tr12. It is held as a voltage component by the inter-capacitance.

  Next, only the control clock supplied to the clock terminal TA is set to CKA at a high level, and the control clocks CKB and CKC supplied to the other clock terminals TB and TC are set to a low level. Since the thin film transistor Tr12 is kept on by the voltage component held in the gate-source capacitance, the high level based on the control clock CKA is applied to the output terminal OUT, and the high level based on the high level control clock CKA is applied. A level external output signal GS (k) is output.

  Here, when a potential based on the high-level control clock CKA is applied to the output terminal OUT via the thin film transistor Tr12, the voltage component held in the capacitor CA and the gate-source capacitance of the thin film transistor Tr12 causes the contact Na to The bootstrap phenomenon occurs in which the potential VNa is boosted to a potential higher than the high level based on the input signal (external output signal GS (k−1)). Thereby, when the potential VNa (gate voltage) of the contact Na reaches the saturation voltage of the thin film transistor Tr12, the source-drain current is saturated and the potential of the output terminal OUT (signal level of the external output signal GS (k)). Is set to a signal level substantially equivalent to the high level of the control clock CKA.

  Thereafter, only the control clock CKB supplied to the clock terminal TB is set to the high level again, and the control clocks CKA and CKC supplied to the other clock terminals TA and TC are set to the low level, so that the thin film transistors Tr14 and Tr15 are turned on again. The ON operation is performed, the potential VNa of the contact Na is set to a high level based on the high level control clock CKB, and the potential VNb of the contact Nb is set to a low level based on the ground voltage Vss. The thin film transistor Tr13 is turned off, and a low level external output signal GS (k) based on the low level control clock CKA is output from the output terminal OUT.

  Then, only the control clock CKC supplied to the clock terminal TC is set to the high level again, the control clocks CKA and CKB supplied to the other clock terminals TA and TB are set to the low level, and the low-level input signal is supplied. As a result, the thin film transistors Tr11, Tr16, and Tr17 are turned on again, and the potential VNa of the contact Na is set to a low level based on the low level input signal (external output signal GS (k−1)). Since the potential VNb is held at a high level based on the high level control clock CKC, the thin film transistor Tr12 is turned off, the thin film transistor Tr13 is turned on, and the low level external output signal based on the ground voltage Vss is output from the output terminal OUT. GS (k) is output.

Next, a drive control method for the shift register circuit to which the above-described signal holding block is applied will be described with reference to the drawings.
FIG. 3 is a timing chart showing the operation of the shift register circuit according to the present embodiment. Here, the shift register circuit and the k-th signal holding block RSA (k) will be described with appropriate reference.

  First, four types of drive pulses CK1 to CK4 supplied as control clocks CKA to CKC to the shift register circuit shown in FIG. 2 are not overlapped in time with each other as shown in FIG. It is set to switch to the high level in the order of CK2, CK3, and CK4. Further, the input terminal IN of the first stage (first stage) signal holding block RSA (1) (not shown) is synchronized with the timing when the control clock CKC supplied to the signal holding block RSA (1) becomes high level. Then, control is performed so that the high-level start signal ST is supplied.

  As shown in FIG. 3, first, at timing <S0>, for example, only the driving pulse CK2 among the driving pulses CK1 to CK4 is set to the high level, and the first stage (first stage) signal holding block RSA (1) (Or the signal holding block RSA (k) at the k-th stage) is supplied as the control clock CKB, the potentials VNa of the contacts Na and Nb that are electrically floating in the signal holding block RSA (1), VNb is determined at a high level based on the high-level control clock CKB (drive pulse CK2) and a low level based on the ground voltage Vss.

  Next, at timing <S1>, in the state where only the driving pulse CK3 is set to the high level and the driving pulses CK1, CK2, and CK4 are set to the low level, all the controls supplied to the signal holding block RSA (1). Since the clocks CKA to CKC are at a low level, the potential VNa of the contact Na is in a floating state on the high level side, and the potential VNb of the contact Nb is in a floating state on the low level side.

  Next, at timing <S2> (first operation timing), only the driving pulse CK4 is set to the high level and supplied as the control clock CKC. When the high level start signal ST is supplied in synchronization with this timing, The potentials VNa and VNb of the contacts Na and Nb that are in the electrically floating state are respectively high level based on the high-level start signal ST and low level based on the divided voltage by the conduction resistances of the thin film transistors Tr16 and Tr17. Confirmed.

  At this time, the thin film transistor Tr12 is turned on when the potential VNa of the contact Na becomes high level. However, since the drive pulse CK1 supplied as the control clock CKA to the clock terminal TA is set to low level, the output terminal OUT Is at a low level, and the high-level shift signal and the high-level external output signal GS (1) are not output to the signal holding block RSA (2) at the next stage (second stage). At this time, the potential difference generated between the contact Na and the output terminal OUT is held as a voltage component in the capacitor CA.

  Next, at timing <S3> (second operation timing), when only the driving pulse CK1 is set to the high level and supplied as the control clock CKA, the potential VNa of the contact Na becomes higher than the high level due to the bootstrap phenomenon. By further rising, the thin film transistor Tr12 is turned on in a saturated state, and the potential of the output terminal OUT (external output signal GS (1)) is fixed to a signal level equivalent to the high level control clock CKA (drive pulse CK1). Is done. As a result, a high-level external output signal GS (1) is output as a shift signal to the signal holding block (2) at the next stage (second stage) via the output terminal OUT, and the first row of the display panel. As a scanning signal (selection signal) for driving the display pixels or the reading pixels in the first row of the sensor array.

  Next, as shown in FIG. 3, when only the control clock CKB (driving pulse CK2) is again set to the high level and supplied at the timing <S4>, the potentials VNa and VNb of the contacts Na and Nb are respectively The high level based on the high level control clock CKB (drive pulse CK2) and the low level based on the ground voltage Vss are determined, and then at timing <S5>, the control clocks CKA to CKC (drive pulses CK1, CK2, CK4). ) Are all set to a low level, the potential VNa of the contact Na is in a floating state on the high level side, and the potential VNb of the contact Nb is in a floating state on the low level side.

  Next, at timing <S6>, when only the control clock CKC (drive pulse CK4) is set to the high level and the low level start signal ST is supplied, the contacts Na and Nb that are in the electrically floating state are supplied. The potentials VNa and VNb are determined at a low level based on the low level start signal ST and a high level based on the high level control clock CKC (drive pulse CK4). As a result, the potential of the output terminal OUT is fixed to a low level based on the ground voltage Vss via the thin film transistor Tr13, so that a high level shift signal to the signal holding block RSA (2) at the next stage (second stage). In addition, the high-level external output signal GS (1) is not output.

  Hereinafter, as shown in FIG. 3, at the timings <S8>, <S12>,... At which the high-level control clock CKB (drive pulse CK2) is supplied, the potential VNa of the contact Na is fixed to the high level. At the same time, the potential VNb of the contact Nb is fixed at the low level, and at the timing <S10>, <S14>,... At which the high level control clock CKC (drive pulse CK4) is supplied, the potential VNa of the contact Na. Is determined at the low level, and the control operation for determining the potential VNb of the contact Nb at the high level is repeated. Here, the timings <S0>, <S2>, <S4>, <S6>,... (Even-numbered timing) correspond to the third operation timing according to the present invention.

That is, in the shift register circuit and the drive control method thereof according to the present embodiment, the output stage transistor circuit (the thin film transistors Tr12 and Tr13 in series) that determines the potential of the output terminal (signal level of the external output signal GS (k)). Circuit) supplies a high-level control clock CKA for determining the signal level only at the timing of outputting the high-level external output signal GS (k), and other timing (that is, the external output signal GS). At the time of (k) non-output), drive control is performed so as to set the signal level of the external output signal GS (k) based on the low level control clock CKA or the ground voltage Vss.
In the non-output state of the output signal GS (k), the potentials VNa and VNb of the contact Na and the contact Nb are alternately switched to a high level or a low level at a predetermined cycle while maintaining the opposite polarities. To drive control.

  Therefore, according to the shift register circuit and the drive control method thereof according to the present embodiment, as a means for determining the signal level (low level) of the external output signal in each signal holding block, it is set to a high level or a low level at a predetermined cycle. Switch means (thin film transistor Tr12) for supplying a drive pulse to be set to the output terminal, and switch means (thin film transistor Tr13) for supplying a low level based on the ground voltage Vss to the output terminal, in a non-output state of the external output signal By alternately (complementarily) turning on these switch means, the signal level of the external output signal can be periodically determined to the low level side.

  Further, since the same potential is not continuously applied to the gate terminal (contact Nb) of the switch means for supplying the low level due to the ground voltage to the output terminal, the shift register circuit (signal holding block) is Even in the case of a thin film transistor using amorphous silicon, the threshold voltage characteristic of the thin film transistor is less likely to deteriorate due to carriers trapped in the semiconductor layer made of amorphous silicon, and the threshold voltage is specified. It is possible to suppress a decrease in driving capability due to a shift (fluctuation) in the voltage direction.

  Thereby, the signal level of the drive pulse is switched at a predetermined cycle for driving the signal holding block of the other stage, and the gate voltage (potential VNa of the contact Na) of one switch means (thin film transistor Tr12) is the gate-drain capacitance. Even if it is affected by the above, since the other switch means (thin film transistor Tr13) has a sufficient drive capability, fluctuations in the signal level of the external output signal can be suppressed.

  Therefore, even when the shift register circuit according to this embodiment is applied to a scanning driver of a display device or an image reading device, the signal level of a selection signal (external output signal) for driving the display panel or sensor array for each row Therefore, it is possible to stabilize the selection state of the display pixels and the photosensors and execute a good image display operation and image reading operation.

  Further, according to the shift register circuit and the drive control method thereof according to the present embodiment, as shown in FIG. 3, the gate voltage (contact point) applied to the transistor circuit in the output stage (series circuit composed of the thin film transistors Tr12 and Tr13). The switch means (thin film transistor) for supplying the drive pulse to the output terminal by holding the potential VNa of the Na and the potential VNb of the contact Nb) by alternately switching the signal level at a predetermined cycle while maintaining the opposite polarities. DC voltage component (potential VNa of the contact Na) applied to the gate terminal of Tr12) and DC voltage component applied to the gate terminal of the switching means (thin film transistor Tr13) for supplying the low level by the ground voltage Vss to the output terminal. The potential VNb) of the contact Nb can be held substantially evenly, so that each switch means The shift of the threshold voltage characteristics of the thin film transistor to be formed can be made substantially equal. As a result, the ratio of the relative drive capabilities of the switch means constituting the transistor circuit in the output stage can be maintained substantially constant, and an external output signal having a good signal level can be output over a long period of time.

  Furthermore, the shift register circuit (signal holding block) according to the present embodiment can be configured using only n-channel field effect transistors (thin film transistors) as shown in FIG. It can be formed by applying amorphous silicon whose manufacturing technology has already been established, and a shift register circuit with excellent operating characteristics can be realized at a relatively low cost.

By the way, it is known that a thin film transistor using amorphous silicon generally has a defect that characteristic deterioration with time is remarkable. Specifically, a thin film transistor using amorphous silicon has a characteristic that carriers are easily trapped in a semiconductor layer made of amorphous silicon.
Therefore, in the present embodiment, the gate voltage applied to the transistor circuit in the output stage (the series circuit including the thin film transistors Tr12 and Tr13) is synchronized with the change of the control clock (drive pulse) while maintaining the opposite polarities. Therefore, by periodically changing (switching) the signal level and confirming it, it is possible to suppress the trapping of the carrier and suppress the deterioration of the operating characteristics (threshold voltage characteristics) of the thin film transistor. The operation of the shift register circuit can be favorably maintained over a long period.

<Second Embodiment>
Next, a second embodiment of the shift register circuit according to the present invention will be described.
FIG. 4 is a schematic configuration diagram illustrating a signal holding block applied to the shift register circuit according to the second embodiment. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted. FIG. 5 is a timing chart for explaining the effectiveness of the shift register circuit according to this embodiment. FIG. 6 is a timing chart for explaining the drive control operation of the shift register circuit according to this embodiment. It is. The operation of the shift register circuit according to this embodiment will be described with reference to the timing chart (FIG. 3) shown in the first embodiment as appropriate.

  As shown in FIG. 4, the signal holding block RSB (k) applied to the shift register circuit according to this embodiment is the signal holding block RSA (k) shown in the first embodiment described above (see FIG. 2). In addition to the gate-source capacitance of the transistor Tr13, between the gate-source of the thin film transistor Tr13 constituting the transistor circuit of the output stage (between the contact Nb and the ground voltage Vss), a capacitor for stabilizing the output level (voltage control) Means, capacitor element) CB is additionally connected.

  In the shift register circuit (signal holding block) having such a circuit configuration, when a drive control operation similar to that shown in the first embodiment is performed, the high-level external output signal GS is used. When (k) is output, deterioration of the signal level of the external output signal GS (k) is suppressed, and the external output signal GS (k) having an appropriate signal level is output. This will be specifically described below.

  That is, in the signal holding block according to the first embodiment (see FIG. 2), when the drive control operation as shown in FIG. 3 is executed, a high level input signal (start signal ST) is supplied at timing <S2>. After the capture, the control clock CKA (drive pulse CK1) is set to the high level at the timing <S3>, whereby a bootstrap phenomenon occurs in the thin film transistor Tr12 in the output stage, and the high-level external output signal GS (k) At this time, as shown in FIG. 3, the gate voltage (potential of the contact Na) that defines the operating state of the thin film transistor Tr12 and the gate voltage (the potential of the contact Nb) that defines the operating state of the thin film transistor Tr13 are displayed. Although the potential is set on the high level side and the low level side, the signal level Le is in floating state that is not finalized.

  Here, in particular, when the parasitic capacitance formed between the gate and drain terminals of the thin film transistor Tr13 (between the output contact OUT and the contact Nb) is large, the high level external output signal GS (k) is output, whereby the thin film transistor The gate voltage of the transistor Tr13 (the potential of the contact Nb) slightly increases from the original low signal level, and the thin film transistor Tr13 is not completely turned off (becomes semiconductive). For example, as shown in FIG. In addition, the signal level output as the external output signal GS (k) decreases from the original high level over time (the signal level surrounded by an ellipse in the figure), etc. Degradation could occur.

Therefore, in the present embodiment, the capacitor CB is connected between the gate and source of the transistor Tr13 (between the contact Nb and the ground voltage Vss), thereby suppressing the fluctuation of the gate voltage (potential VNb of the contact Nb) of the transistor Tr13. Thus, a stabilized circuit configuration is applied.
That is, in the shift register circuit (signal holding block) according to the present embodiment, as shown in FIG. 6, in a specific signal holding block RSB (k), a high-level input signal (start signal ST) at timing <S2>. ), The control clock CKA is set to a high level at timing <S3>, whereby a bootstrap phenomenon occurs in the output thin film transistor Tr12, and a high-level external output signal GS (k) is output. (The potential of the output terminal OUT becomes high level) At this time, even if the gate-drain capacitance of the thin film transistor Tr13 is large, the capacitor CB is connected between the gate and the source, so that the thin film transistor The gate voltage of Tr13 (potential VNb of contact Nb) It can be relatively held at a predetermined potential with reference to the ground voltage Vss (in other words, it can be determined at a predetermined low level instead of a floating state; in the figure, a signal level surrounded by an ellipse) Therefore, the fluctuation of the potential VNb of the contact Nb accompanying the change in the signal level of the external output signal GS (k) can be suppressed, and the thin film transistor Tr13 can be favorably held in the off state (non-conducting state). Degradation of the signal level of GS (k) can be suppressed.

  Therefore, even when the shift register circuit according to this embodiment is applied to a scanning driver of a display device or an image reading device, the signal level of a selection signal (external output signal) for driving the display panel or sensor array for each row Therefore, the selection state of the display pixel and the photosensor can be stabilized, and a good image display operation and image reading operation can be executed.

  Note that, as described above, the shift register circuit (signal holding block) according to the present embodiment determinates the operating state of the thin film transistor in the output stage that defines the signal level of the external output signal, and the signal level of the external output signal. In order to suppress the fluctuation, a configuration is shown in which a capacitor is connected between the gate and source terminals of the thin film transistor; however, the present invention is not limited to this. In short, in this embodiment, any capacitor may be connected so that the gate voltage of the thin film transistor is stabilized. For example, one end of the capacitor is connected to the gate terminal of the thin film transistor, and the other end is connected to the other end. It may have a circuit configuration connected to a contact to which a stable potential, for example, a power supply voltage (not shown) is supplied.

<Third Embodiment>
Next, a third embodiment of the shift register circuit according to the present invention will be described.
FIG. 7 is a schematic configuration diagram illustrating a signal holding block applied to the shift register circuit according to the third embodiment. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted. The drive control operation of the shift register circuit according to the present embodiment will be described with reference to the timing chart (FIG. 6) shown in the second embodiment.

  In the signal holding block RSB (k) according to the second embodiment described above, the thin film transistor Tr13 in the output stage is definitely held in the OFF state at the timing of outputting the high-level external output signal GS (k). In addition, a circuit configuration in which the capacitor CB is connected between the gate and source terminals of the thin film transistor Tr13 (between the contact point Nb and the ground voltage Vss) is applied. In this embodiment, the signal level of the external output signal GS (k) is used. Thus, it has a circuit configuration that definitely holds the operation state of the thin film transistor Tr13 in the output stage.

  As shown in FIG. 7, the signal holding block RSC (k) applied to the shift register circuit according to this embodiment is the signal holding block RSA (k) shown in the first embodiment described above (see FIG. 2). , The source-drain terminal is connected between the gate and source of the thin film transistor Tr13 constituting the output stage transistor circuit (between the contact Nb and the ground voltage Vss), and the potential of the output terminal OUT (signal of the external output signal GS (k)) It has a configuration including a thin film transistor (voltage control means, eighth switch means) Tr18 whose level is applied to the gate terminal.

  In the shift register circuit (signal holding block) having such a circuit configuration, when a high-level external output signal GS (k) is output at timing <S3>, for example, as shown in FIG. The level (high level) is applied to the gate terminal of the thin film transistor Tr18 provided between the gate and source of the thin film transistor Tr13 in the output stage, and the thin film transistor Tr18 is turned on. As a result, the contact Nb (the gate terminal of the thin film transistor Tr13) is connected to the ground voltage Vss, and the potential VNb is definitely set to the low level (in other words, not the floating state but the predetermined low level). Therefore, the variation of the potential VNb of the contact Nb accompanying the change in the signal level of the external output signal GS (k) is suppressed, and the thin film transistor Tr13 is improved. Can be held in an off state (non-conducting state), and similarly to the second embodiment described above, the signal level deterioration of the external output signal GS (k) is suppressed and a stable high level state is maintained. be able to.

Next, configuration examples of a display device and an image reading device to which the shift register circuit according to the present invention can be applied will be briefly described with reference to the drawings.
(First application example)
FIG. 8 is a schematic configuration diagram showing a display device in which the shift register circuit according to the present invention is applied to a scan driver (drive control device). Note that here, a structure including an active matrix display panel as a display device will be described.

As shown in FIG. 8, the display device 100 according to this application example is roughly divided into a display panel (pixel array) 110, a scan driver (gate driver) 120, a data driver (source driver) 130, and a system controller 140. And a display signal generation circuit 150.
Here, the display panel 110 is, for example, a well-known transmissive or reflective liquid crystal display panel, or a self-luminous light emitting element (such as an organic electroluminescent element (organic EL element) or a light emitting diode (LED)). As shown in FIG. 8, the display panel is arranged in the vicinity of each intersection of a scanning line SL arranged in the row direction and a data line DL arranged in the column direction. The display pixels according to the form are arranged two-dimensionally.

  Further, as shown in FIG. 8, the scan driver 120 roughly includes a plurality of stages of signal holding blocks having a circuit configuration equivalent to that of each of the above-described embodiments, corresponding to the scan lines SL of each row of the display panel 110. A shift register circuit 121, and a buffer circuit 122 that amplifies an external output signal output from the signal holding block at each stage to a predetermined signal level and supplies the amplified signal to the scanning line SL of each row as a scanning signal. Yes. Then, in the signal holding block at each stage of the shift register circuit 121, a scanning control signal (scanning start signal (corresponding to the above-mentioned start signal ST), scanning clock signal (supplied) is supplied from a system controller (LCD controller) 140 described later. Etc.) corresponding to the drive pulses CK1 to CK4 described above) and the like, while sequentially outputting (transmitting) the shift signal corresponding to the upper side to the lower side of the display panel 110, the shift signal is taken out as an external output signal, It is applied as a scanning signal to each scanning line SL via the buffer circuit 122, and the display pixel EM group for each row is controlled to be sequentially set to a selected state.

  Based on the data control signal supplied from the system controller 140, the data driver 130 captures and holds the display data for each row of the display panel 110 supplied from the display signal generation circuit 150, and stores the display data in the display data. A corresponding gradation signal (gradation voltage or gradation current) is generated and supplied in parallel to each display pixel EM set in the selected state by the scan driver 120 via each data line DL. The gradation signal (pixel information corresponding to the display data) is controlled to be written in each display pixel EM.

For example, the display signal generation circuit 150 extracts a luminance gradation signal component and a timing signal component from a video signal supplied from the outside of the display device 100, and the luminance gradation signal component for each row of the display panel 110. Is supplied to the data driver 130 as display data, and the timing signal component is supplied to the system controller 140.
Based on the timing signal supplied from the display signal generation circuit 150, the system controller 140 generates the above-described scan control signal and data control signal for at least the scan driver 120 and the data driver 130, respectively. By outputting, each driver is operated at a predetermined timing, the scanning signal and the gradation signal are output to the display panel 110, the light emission driving operation in the display pixel EM is continuously performed, and a predetermined signal based on the video signal is output. The image information is displayed on the display panel 110.

  As described above, the shift register circuit according to the present invention is applied to the scan driver 120 of the display device 100, and the drive pulses CK1 to CK4 that have a predetermined cycle and do not overlap with each other from the system controller 140, and By supplying the scanning start signal ST as a scanning control signal, the individual scanning signals are output based on the external output signals that are sequentially output from the signal holding blocks shown in the above-described embodiments and in which the fluctuation of the signal level is suppressed. Can be applied to the scanning line SL, the selection state of the display pixels can be stabilized, a good image display operation can be executed, and the display image quality can be improved.

In addition, the display pixel EM according to this configuration example and at least the shift register circuit (the signal holding block shown in each of the embodiments described above) applied to the scan driver are formed in a batch by the same manufacturing process. It can be manufactured by applying a conductive layer or an insulating layer. That is, a pixel transistor (selection transistor; pixel selection unit) provided in a liquid crystal display panel or the like, a thin film transistor provided in a pixel drive circuit (light emission drive circuit; pixel selection unit) applied to an organic EL panel or the like, and a shift register circuit ( Each thin film transistor constituting a signal holding block) includes a conductive layer (electrode layer), an insulating layer, and a semiconductor layer made of amorphous silicon formed on the same insulating substrate such as a glass substrate by the same manufacturing process. Can be manufactured by application.
Therefore, it is possible to form the display panel and the scan driver (shift register circuit) simultaneously and integrally using the same manufacturing process by applying amorphous silicon, whose manufacturing technology has already been established. In addition, a display device with excellent operating characteristics can be realized.

(Second application example)
FIG. 9 is a schematic configuration diagram showing an image reading apparatus in which the shift register circuit according to the present invention is applied to a gate driver (corresponding to a scanning driver; drive control apparatus). FIG. 10 is a schematic cross-sectional view showing the element structure of a photosensor applicable to the image reading apparatus according to this configuration example.
As shown in FIG. 9, the image reading apparatus according to this application example is roughly divided into a photosensor array (pixel array) 210, a top gate driver 220, a bottom gate driver 230, a drain driver 240, and a system controller 250. And is configured.

  As shown in FIG. 9, the photo sensor array 210 is arranged in the column direction, for example, with a top gate line (reset line) TL and a bottom gate line (read line) BL arranged in parallel in the row direction. Photosensors (double-gate photosensors) PS having a double-gate thin film transistor structure, which will be described later, are two-dimensionally arranged (for example, i rows × j columns; i and j are each) in each intersection region of drain lines (data lines) DL Arbitrary natural numbers) are arranged. Here, the source terminal S of each photosensor PS is connected to a predetermined low potential voltage (for example, ground potential) Vss.

  The top gate driver 220 is connected to each top gate line TL commonly connected to the top gate terminal TG of the photosensor PS in each row, and based on the top gate control signal supplied from the system controller 250, the top gate signal ( By generating φTi (corresponding to the scanning signal) and outputting it to the top gate line TL of each row, the reset operation and the carrier accumulation operation in each photosensor PS are selectively controlled.

  The bottom gate driver 230 is connected to each bottom gate line BL commonly connected to the bottom gate terminals BG of the photosensors PS in each row, and based on the bottom gate control signal supplied from the system controller 250, the bottom gate signal ( By generating φBi (corresponding to the scanning signal) and outputting it to the bottom gate line BL of each row, execution control of the reading operation in each photosensor PS is performed.

  The drain driver 240 is connected to each drain line DL commonly connected to the drain terminals D of the photosensors PS in each column, and is connected to each drain line DL based on a drain control signal supplied from the system controller 250. A precharge operation for applying a predetermined precharge voltage to each photosensor PS is executed and controlled, and by applying the bottom gate signal φBi, the amount of carriers accumulated in each photosensor PS is passed through each drain line DL. The operation of reading out the signal voltage (drain voltage) is controlled.

The system controller 250 supplies each of the top gate driver 220, the bottom gate driver 230, and the drain driver 240 with a top gate control signal, a bottom gate control signal, and a drain control signal, thereby configuring each photosensor array 210. In the photosensor PS, a control for executing a series of image reading operations (reset, carrier accumulation, precharge, and read operations) described later is performed.
Further, the system controller 250 performs predetermined image processing on the image data generated based on the signal voltage read by the drain driver 230, and performs writing and reading to a storage unit (not shown). In addition, it also has a function as an interface to the external function unit 300 that executes predetermined function processing such as image data collation and processing.

Here, for example, as shown in FIG. 10, the photosensor PS applicable to this configuration example is roughly amorphous silicon or the like in which an electron-hole pair is generated by incidence of excitation light (here, visible light). The semiconductor layer 111 is formed on both ends of the semiconductor layer 111 through impurity layers (ohmic contact layers) 117 and 118 made of n ⁺ silicon, and is selected from chromium, chromium alloy, aluminum, aluminum alloy, etc. Source electrode 112 (source terminal S shown in FIG. 9) and drain electrode 113 (drain terminal D shown in FIG. 9) made of a conductive material and opaque to visible light, and above semiconductor layer 111 (upper drawing) And a transparent electrode such as a tin oxide film or an ITO film (indium-tin oxide film) formed through a block insulating film (stopper film) 114 and an upper gate insulating film 115. A top gate electrode TGx (top gate terminal TG shown in FIG. 9) that is made of layers and is transmissive to visible light, and is formed below the semiconductor layer 111 (downward in the drawing) via a lower gate insulating film 116. And a bottom gate electrode BGx (bottom gate terminal BG shown in FIG. 9) made of a conductive material selected from chromium, chromium alloy, aluminum, aluminum alloy, etc., and opaque to visible light. Has been. The double-gate photosensor PS having such a configuration is formed on an insulating substrate SUB such as a glass substrate as shown in FIG.

  In FIG. 10, the top gate insulating film 115, the block insulating film 114, the insulating film constituting the bottom gate insulating film 116, and the protective insulating film 119 provided over the top gate electrode TGx all include the semiconductor layer 111. Irradiates at least a subject (not shown) placed on the upper surface of the protective insulating film 119 by being made of a material having high transmittance for exciting visible light, such as silicon nitride or silicon oxide. Thus, it has a structure that detects only light reflected and incident on the photosensor PS (specifically, the semiconductor layer 111) from above.

Next, a drive control method for the above-described image reading apparatus will be briefly described with reference to the drawings.
FIG. 11 is a timing chart showing a basic drive control method in the image reading apparatus provided with the photosensor array including the double gate type photosensor described above.
As shown in FIG. 11, the driving control method of the image reading apparatus according to this application example includes a reset period Trst, a charge accumulation period Tacc, a precharge period Tprch in a predetermined processing operation period (one processing cycle). This is realized by setting a reading period Tread.

  First, in the reset period Trst, a high-level reset pulse (for example, +15 V) as a top gate signal φTi is applied to the top gate terminal TG of each photosensor PS in the i-th row by the top gate driver 220 via the top gate line TL. Is applied, and a reset operation (initialization operation) for releasing carriers (here, holes) accumulated in the semiconductor layer 111 is executed.

Next, in the charge accumulation period Tacc, the top gate driver 220 applies a low level bias voltage (for example, −15 V) as the top gate signal φTi to the top gate terminal TG of each photosensor PS in the i-th row. The reset operation is finished, and the charge accumulation operation (carrier accumulation operation) is started.
Here, in the charge accumulation period Tacc, the light irradiated and reflected on the subject placed above the photosensor PS shown in FIG. 10 passes through the top gate electrode TGx made of a transparent electrode layer. By entering the semiconductor layer 111, electron-hole pairs are generated in the carrier generation region of the semiconductor layer 111 in accordance with the amount of incident light (reflected light), and the interface between the semiconductor layer 111 and the block insulating film 114. Holes are accumulated in the vicinity (around the channel region).

  In the precharge period Tprch, in parallel with the charge accumulation period Tacc, the drain driver 240 passes the drain line DL to the drain terminal D of each photosensor PS in the jth row as a drain signal φDj. By applying a precharge pulse having the charge voltage Vpg, a precharge operation for holding the charge in the drain electrode 113 is executed.

  Next, after the precharge period Tprch has elapsed, in the read period Tread, the bottom gate driver 230 passes the bottom gate line BL to the bottom gate terminal BG of each i-th photosensor PS as a bottom gate signal φBi. A drain voltage VDj corresponding to carriers (holes) accumulated in the channel region during the charge accumulation period Tacc is applied via the drain line DL by the drain driver 240 by applying a high level read pulse (for example, +10 V). The read operation is executed.

  Here, the change tendency of the drain voltage VDj shows a tendency that the drain voltage VDj sharply decreases when there are many carriers accumulated in the charge accumulation period Tacc (bright state), while there are few accumulated carriers. In such a case (dark state), since it tends to gradually decrease, for example, the photosensor PS is detected by detecting the drain voltage VDj (= Vrd) at the end of a predetermined read period Tread (after a certain time has elapsed). Can be detected, that is, brightness data corresponding to the light / dark pattern of the subject.

  Then, a series of lightness data detection operations for such a specific row (i-th row) is set as one processing cycle, and the same processing procedure is sequentially repeated for all the rows constituting the photosensor array 210 described above. Thus, a two-dimensional image of the subject can be read as brightness data, and the image data of the subject can be acquired by the system controller 250. The image data is used for predetermined function processing such as collation and processing in the external function unit 300, for example. As described above, when the double gate type photosensor is applied as the reading pixel constituting the photosensor array, both the pixel selection function (corresponding to the pixel selection means) and the lightness data reading function are a single photosensor. It is realized with.

  In the image reading apparatus 200 as described above, the top gate driver 220 and the bottom gate driver 230 correspond to the top gate line TL or the bottom gate line BL of each row as in the scan driver shown in the first application example. A configuration including a shift register circuit including a plurality of stages of signal holding blocks can be applied. Here, the external output signal output from the signal holding block at each stage of the shift register circuit is amplified to a predetermined signal level via the buffer circuit, and the top gate of each row as the top gate signal φTi and the bottom gate signal φBi. It is supplied to the line TL or the bottom gate line BL.

  As a result, the drive pulses CK1 to CK4 and the start signal ST, which have a predetermined cycle and whose signal timings do not overlap each other, are individually supplied from the system controller 250 as a top gate control signal and a bottom gate control signal. Thus, the top gate line TL is generated by generating the top gate signal φTi and the bottom gate signal φBi based on the external output signal that is sequentially output from the signal holding block shown in each of the above-described embodiments and whose signal level fluctuation is suppressed. In addition, since it can be individually applied to the bottom gate line BL, the operation state of the reading pixel (photo sensor) can be stabilized, a good image reading operation can be executed, and the occurrence of malfunctions can be suppressed. it can.

  In addition, the photosensor PS according to this configuration example and the shift register circuit (the signal holding block shown in each embodiment described above) applied to at least the top gate driver and the bottom gate driver are collectively processed by the same manufacturing process. Thus, it can be manufactured by applying a conductive layer or an insulating layer. That is, the double gate thin film transistor structure constituting the photosensor PS and each thin film transistor constituting the shift register circuit (signal holding block) are formed on the same insulating substrate SUB such as the same glass substrate. It can be manufactured by applying a conductive layer, an insulating layer, or a semiconductor layer made of amorphous silicon.

Therefore, it is possible to form the photosensor array and the top gate driver and the bottom gate driver (shift register circuit) simultaneously and integrally using the same manufacturing process by applying amorphous silicon whose manufacturing technology has already been established. Therefore, it is possible to realize an image reading apparatus having excellent operating characteristics at a relatively low cost.
In the above embodiment, the transistors constituting each stage are n-channel, but may be all p-channel transistors. At this time, the drive pulses CK1 to CK4 and the start signals ST and GS (k) are signals obtained by inverting the high level and the low level, and the ground voltage Vss may be set to a voltage higher than 0 (V).

1 is a schematic configuration diagram showing a first embodiment of a shift register circuit according to the present invention. It is a circuit block diagram which shows the specific example of the signal holding block applied to the shift register circuit which concerns on this embodiment. 6 is a timing chart illustrating an operation of the shift register circuit according to the present embodiment. It is a schematic block diagram which shows the signal holding block applied to the shift register circuit which concerns on 2nd Embodiment. 4 is a timing chart for explaining the effectiveness of the shift register circuit according to the present embodiment. 6 is a timing chart for explaining a drive control operation of the shift register circuit according to the embodiment. It is a schematic block diagram which shows the signal holding block applied to the shift register circuit which concerns on 3rd Embodiment. 1 is a schematic configuration diagram showing a display device in which a shift register circuit according to the present invention is applied to a scan driver (drive control device). 1 is a schematic configuration diagram illustrating an image reading apparatus in which a shift register circuit according to the present invention is applied to a scan driver (drive control device). It is a schematic sectional drawing which shows the element structure of the photosensor applicable to the image reading apparatus which concerns on this structural example. 6 is a timing chart illustrating a basic drive control method in the image reading apparatus according to the present configuration example. It is a circuit block diagram which shows schematic structure of the shift register circuit in a prior art. 6 is a timing chart showing a drive control operation of a shift register circuit in the prior art. 6 is a timing chart for explaining problems of the shift register circuit in the prior art.

Explanation of symbols

RSA, RSB, RSC Signal holding block CK1-CK4 Drive pulse CKA, CKB, CKC Control clock GS External output signal ST Start signal 100 Display device 200 Image reading device

Claims (12)

In a shift register circuit comprising a plurality of stages of signal holding means connected in series and sequentially outputting an output signal from each of the signal holding means based on an input signal sequentially inputted to the signal holding means of each stage ,
Each of the signal holding means is at least
An input control unit that captures the input signal at a first operation timing;
An output control unit that outputs the output signal having the first signal level at the second operation timing based on the signal level of the input signal captured at the first operation timing;
A signal level determining unit that outputs the output signal determined to be the second signal level from the output control unit at a third operation timing;
Equipped with a,
Each of the first signals is generated by a plurality of types of control clocks selected from a plurality of drive pulse groups set so that the pulse signals have the same signal period and the pulse signals do not overlap in time. Thru third operation timings are defined,
The output control unit includes at least a first switch in which the control clock defining the second operation timing is supplied to one end side of a current path, and an output contact of the output signal is connected to the other end side And a second switch means to which a predetermined power supply voltage is applied to one end side of the current path and the output contact is connected to the other end side,
The signal level determination unit mutually transmits a first control voltage applied to a control terminal of the first switch means and a second control voltage applied to a control terminal of the second switch means. Periodically fix the signal level to the opposite polarity,
The signal level determining unit is supplied with at least the control clock defining the third operation timing on one end side of the current path, and connected with the control terminal of the first switch means on the other end side. A third switch means; and a fourth switch means to which the predetermined power supply voltage is applied to one end side of the current path and to which the control terminal of the second switch means is connected to the other end side. The shift register circuit is characterized in that the control clock defining the third operation timing is commonly applied to the control terminals of the third and fourth switch means . In addition to the third and fourth switch means, the signal level determination unit is further supplied with the control clock defining the first operation timing on one end side of the current path and on the other end side with the control clock. The predetermined power supply voltage is applied to one end side of the current path, and the control terminal of the second switch means is connected to the other end side of the fifth switch means to which the control terminal of the second switch means is connected. And a sixth switch means connected thereto, wherein the control clock for defining the first operation timing is commonly applied to control terminals of the fifth switch means. Item 4. A shift register circuit according to Item 1 . The input control unit includes at least an input contact of the input signal connected to one end side of the current path, a control terminal of the first switch means connected to the other end side, and the first terminal connected to the control terminal. the shift register circuit according to claim 1 or 2, wherein the control clock for regulating the operation timing is characterized in that it comprises a seventh switching means which is supplied. The signal level determining unit sets the second control voltage to a polarity opposite to that of the first control voltage so as to hold the second switch means in a non-conductive state at the second operation timing. the shift register circuit according to any one of claims 1 to 3, characterized in that it comprises a voltage control means for determining the. 5. The shift register circuit according to claim 4 , wherein the voltage control means is a capacitive element connected between a control terminal of the second switch means and a predetermined power supply voltage. The voltage control means has a control terminal of the second switch means connected to one end side of the current path, the predetermined power supply voltage connected to the other end side, and the output contact connected to the control terminal. 5. The shift register circuit according to claim 4 , wherein the shift register circuit is an eighth switch means. At least, the switching unit of the first to eighth shift register circuit according to any one of claims 1 to 6, characterized in that a field-effect transistor of the n-channel type. 8. The shift register circuit according to claim 7 , wherein at least the first to eighth switch means are thin film transistors using an amorphous silicon semiconductor. The plurality of stages of signal holding means extract the output signal from the signal holding means of each stage based on the signal level of the input signal input to the signal holding means of the first stage, and shift the output signal to the shift signal as the shift register circuit according to any one of claims 1 to 8, characterized in that sequentially outputting the next stage of the signal holding unit. A shift register circuit comprising a plurality of stages of signal holding means connected in series and sequentially outputting an output signal from each of the signal holding means based on input signals sequentially inputted to the signal holding means of each stage. In the drive control method,
Each of the signal holding means is at least
An input control unit that captures the input signal at a first operation timing;
An output control unit that outputs the output signal having the first signal level at the second operation timing based on the signal level of the input signal captured at the first operation timing;
A signal level determining unit that outputs the output signal determined to be the second signal level from the output control unit at a third operation timing;
With
Each of the first signals is generated by a plurality of types of control clocks selected from a plurality of drive pulse groups set so that the pulse signals have the same signal period and the pulse signals do not overlap in time. Thru third operation timings are defined,
The output control unit includes at least a first switch in which the control clock defining the second operation timing is supplied to one end side of a current path, and an output contact of the output signal is connected to the other end side And a second switch means to which a predetermined power supply voltage is applied to one end side of the current path and the output contact is connected to the other end side,
The signal level determination unit mutually transmits a first control voltage applied to a control terminal of the first switch means and a second control voltage applied to a control terminal of the second switch means. Periodically fix the signal level to the opposite polarity,
The signal level determining unit is supplied with at least the control clock defining the third operation timing on one end side of the current path, and connected with the control terminal of the first switch means on the other end side. A third switch means; and a fourth switch means to which the predetermined power supply voltage is applied to one end side of the current path and to which the control terminal of the second switch means is connected to the other end side. The control clock defining the third operation timing is commonly applied to the control terminals of the third and fourth switch means,
A step of capturing the input signal in the first operation timing,
A step of based on the signal level of the input signal taken by the first operation timing, and outputs the output signal having the first signal level at the second operation timing,
And outputting the third said output signal determined in said second signal level at the operation timing of the periodically,
A drive control method for a shift register circuit, comprising: 11. The drive control method for a circuit of a shift register according to claim 10 , wherein the second control voltage is determined at a signal level having a polarity opposite to that of the first control voltage at the second operation timing. . In a drive control device including a shift register circuit that sequentially outputs a scanning signal for driving pixels in each row with respect to a pixel array in which a plurality of pixels are two-dimensionally arranged.
The shift register circuit includes a plurality of stages of signal holding means connected in series,
Each of the signal holding means is at least
An input control unit that captures an input signal at a first operation timing;
An output control unit that outputs an output signal having a first signal level at a second operation timing based on the signal level of the input signal captured at the first operation timing;
A signal level determining unit that outputs the output signal determined to be the second signal level from the output control unit at a third operation timing;
Comprising
Each of the first signals is generated by a plurality of types of control clocks selected from a plurality of drive pulse groups set so that the pulse signals have the same signal period and the pulse signals do not overlap in time. Thru third operation timings are defined,
The output control unit includes at least a first switch in which the control clock defining the second operation timing is supplied to one end side of a current path, and an output contact of the output signal is connected to the other end side And a second switch means to which a predetermined power supply voltage is applied to one end side of the current path and the output contact is connected to the other end side,
The signal level determination unit mutually transmits a first control voltage applied to a control terminal of the first switch means and a second control voltage applied to a control terminal of the second switch means. Periodically fix the signal level to the opposite polarity,
The signal level determining unit is supplied with at least the control clock defining the third operation timing on one end side of the current path, and connected with the control terminal of the first switch means on the other end side. A third switch means; and a fourth switch means to which the predetermined power supply voltage is applied to one end side of the current path and to which the control terminal of the second switch means is connected to the other end side. The control clock defining the third operation timing is commonly applied to the control terminals of the third and fourth switch means,
Based on the output signals output from each of the signal holding means, the input signal input to the signal holding means of the first stage is sequentially shifted to the signal holding means of the subsequent stage, and the scanning signal is changed. A drive control device that generates the drive control device.

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