JP2001282169A - Shift register and electronic device - Google Patents

Abstract

(57) [Summary] To stabilize the level of an output signal output from each stage of a shift register. SOLUTION: A wiring A surrounded by a source of a TFT 21, a gate of a TFT 22, and a drain of a TFT 23 is connected to a wiring for supplying a reference voltage Vss.
The capacitor C1 is inserted for each stage. If no charge is accumulated in the wiring A and the TFT 21 is off, the wiring A
Is in a floating state. At this time, a high-level clock signal CK1 or CK
When 2 is supplied, the potential of the wiring A increases due to the parasitic capacitance of the TFT 22. However, this increase in the potential can be mitigated by the capacitor C1, and it is possible to prevent the gate voltage of the TFT 22 from exceeding the threshold voltage and leaking the clock signal CK1 or CK2 as the output signals OUT1, OUT2,.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a shift register,
And an electronic device such as a display device or an imaging device using the shift register as a driver.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device such as a TFT liquid crystal display device, display pixels arranged in a matrix are selected line by line, and display data is written into a pixel capacitance of the selected pixel to thereby obtain a desired display pixel. Getting the display. As a driver for selecting this line, a shift register that sequentially shifts an output signal in accordance with an external control signal is generally used.

FIG. 18 shows a configuration of a conventional shift register. This shift register includes a plurality of stages RS
(1), RS (2),..., Each stage has four TFTs (Thin Film Transistors) 21 to 24
It is constituted by. In this shift register, when a high-level start signal Pst is supplied from the outside, the TFT 21 of the first stage RS (1) is turned on, so that the TFTs 21 and 2 of the first stage RS (1) are turned on.
Electric charges are accumulated in the wiring between 2 and 23, and the TFT 22 is turned on. When the clock signal CK1 changes to a high level in this state, the clock signal CK1 is substantially kept as it is via the TFT 22 which is turned on.
This is output as the output signal OUT1 of (1).

[0004] The output signal OUT1 turns on the TFT 21 of the second stage RS (2).
The charge from the output signal OUT1 is accumulated in the wiring between the TFTs 21, 22, and 23 of the second stage RS (1),
The FT 22 turns on. When the clock signal CK2 changes to a high level in this state, the clock signal CK2 is output as it is as the output signal OUT2 of the second stage RS (2) via the TFT 22 which is turned on.
Also, the output signal OUT2 causes the first stage RS
The charge accumulated in the wiring between the TFTs 21, 22, and 23 of (1) is released.

Further, each stage RS (1), RS (2),.
When the period during which a high-level output signal is to be output ends, a high-level control signal φR
Is supplied, the TFT 24 is turned on. As a result, the electric charges accumulated in the wiring for outputting the output signals OUT1, OUT2,... Are forcibly released, and the signal levels thereof are reset to the low level. By repeating the above operations, the output signals OUT1, OUT2,... Which become high level are sequentially shifted.

Japanese Patent Laid-Open Publication No. 2000-35772 shows another example of such a shift register.
FIG. 19 shows a configuration of a shift register described in Japanese Patent Application Laid-Open No. 2000-35772.

This shift register also has a plurality of stages RS
(1), RS (2),..., And each stage is composed of five TFTs 21 ′, 22, 25-27. In this shift register, when the control signal φ1 goes to a high level, T (T) of the first stage RS (1)
FT21 'turns on. At this time, when the high-level start signal Pst is supplied from the outside, the ON T
TFT2 of the first stage RS (1) via FT21 '
Electric charges are accumulated in the wiring between 1 ', 22, and 26, and the TFT
22 and 26 are turned on.

Thus, the source of the TFT 25 and the TFT
The electric charge accumulated in the wiring between the drain of the TFT 26 and the TFT
The TFT 27 is turned off when the gate voltage becomes low level. In this state, the clock signal C
When K1 changes to a high level, this clock signal CK
The potential of 1 is output as it is as the output signal OUT1 of the first stage RS (1) via the TFT 22 which is turned on substantially as it is.

While the output signal OUT1 is at a high level, the control signal φ2 is at a high level and the TFT
By turning on 21 ′, the TFTs 22 and 26 of the second stage RS (2) are turned on and the TFT 27 is turned on in the same manner.
Turns off. When the clock signal CK2 changes to the high level in this state, the potential of this clock signal CK2 is output as it is as the output signal OUT2 of the second stage RS (2) via the TFT 22 which is turned on.

Next, when the control signal φ1 goes high while the output signal OUT2 is high, the TFT 21 'of the third stage RS (3) is turned on, and the TFT 22' , 26 are turned on and the TFT 27 is turned off. Further, when the control signal φ1 becomes high level, the TFT 21 ′ of the first stage RS (1) is also turned on, and the electric charge accumulated in the above-described wiring is released. By repeating the above operations, the output signals OUT1, OUT2,... Which become high level are sequentially shifted.

However, in these shift registers, the wiring between the TFTs 21, 22, and 23 or the TFT 2
The wiring between 1 ', 22, and 26 is in a floating state unless the output signal of the stage or the previous stage is at a high level. In such a state, when the clock signal CK1 or CK2 supplied to the drain of the TFT 22 becomes high level, the potential of these wirings increases due to the parasitic capacitance of the TFT 22. As a result, the conductance of the TFT 22 changes, and the clock signal CK1 or CK
2 leak to the output signals OUT1, OUT2,. That is, in these shift registers, the levels (especially low levels) of the output signals OUT1, OUT2,... Become unstable.

When these shift registers are used, for example, as a gate driver of a liquid crystal display device, the voltage on the gate line of the liquid crystal display element becomes undesirably high, and the voltage applied to each pixel electrode of the liquid crystal display element is increased. It may exceed the threshold voltage of the connected TFT. If the TFT is turned on outside the selection period of each line in this manner, the image data to be written to the pixel capacitor is different from the original one, and the image quality of the displayed image is degraded.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a shift register in which the level of an output signal from each stage is stabilized. Aim.

Another object of the present invention is to provide an electronic device which can enhance the quality of a displayed or photographed image by applying the shift register as a driver.

[0015]

In order to achieve the above object, a shift register according to a first aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register is adjacent. A first transistor that is turned on by a signal of a predetermined level supplied from one of the stages to a control terminal, and outputs the signal of the predetermined level from one end to the other end of the current path; It is turned on by the electric charge accumulated in the wiring formed between the other end of the current path and the first or second signal externally supplied to one end of the current path and output from the other end of the current path as an output signal. A second transistor and an output signal of the other stage adjacent to the control terminal are supplied, and the third transistor is turned on by the output signal of the other stage to release charges accumulated in the wiring. Characterized in that it comprises a static and a capacitor having one end connected to the wiring.

To achieve the above object, a shift register according to a second aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register is supplied to a control terminal from outside. A first signal which is turned on by the third or fourth signal and outputs a signal of a predetermined level supplied from one of the adjacent stages to one end of the current path to the other end of the current path;
And the first or second transistor supplied to the one end of the current path from the outside by the electric charge accumulated in the wiring formed between the transistor and the control terminal and the other end of the current path of the first transistor. A second transistor that outputs the signal from the other end of the current path as an output signal, and an output signal of the other stage adjacent to the control terminal. The second transistor is turned on by the output signal of the other stage. And a third transistor for discharging the electric charge accumulated in the first transistor, and a capacitor having one end connected to the wiring.

In the shift register according to the first and second aspects, a predetermined control signal which rises after the first or second signal falls is supplied to a control terminal, and is turned on by the predetermined control signal. With this, it is possible to further include a fourth transistor for discharging charges accumulated in a signal line for outputting an output signal from the other end of the current path of the second transistor.

In the shift register according to the first and second aspects, the first or second signal supplied to one end of the current path of the second transistor in an adjacent stage is supplied to a control terminal. A transistor further provided with a fourth transistor that, when turned on by the first or second signal, releases electric charges accumulated in a signal line for outputting an output signal from the other end of the current path of the second transistor It can also be.

In order to achieve the above object, a shift register according to a third aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register has a control terminal from one adjacent stage. A first transistor that is turned on by a signal of a predetermined level supplied to the first transistor and outputs the signal of the predetermined level from one end of the current path to the other end, and a control terminal and the other end of the current path of the first transistor. A second transistor that is turned on by the electric charge accumulated in the wiring formed therebetween and emits a signal supplied to one end of the current path via the load from the other end of the current path, a control terminal, and the first transistor; The other end of the current path is turned on by the electric charge accumulated in the wiring formed between the other end of the current path and the first or second signal externally supplied to one end of the current path as an output signal. Out of A third transistor to be turned on by a signal supplied to a control terminal via a load when the second transistor is off, and a signal supplied from the outside to one end of the current path as an output signal. A fourth transistor output from the other end of the path and an output signal of the other stage adjacent to the control terminal are supplied, and when turned on by the output signal of the other stage, charges accumulated in the wiring are released. A fifth transistor to be driven and a capacitor having one end connected to the wiring.

To achieve the above object, a shift register according to a fourth aspect of the present invention is a shift register having a plurality of stages, wherein each stage of the shift register is supplied to a control terminal from outside. A first signal which is turned on by the third or fourth signal and outputs a signal of a predetermined level supplied from one of the adjacent stages to one end of the current path to the other end of the current path;
, And turned on by the electric charge accumulated in the wiring formed between the control terminal and the other end of the current path of the first transistor. A second transistor that is discharged from the other end of the current path; and a charge that is accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor. A third transistor that outputs the first or second signal supplied from the other end of the current path as an output signal, and a third transistor that is supplied to a control terminal via a load when the second transistor is off. A fourth transistor which is turned on by a signal supplied from the other end and is output from the other end of the current path as a signal supplied from the outside to one end of the current path, and a capacitor having one end connected to the wiring. To.

In the shift register according to the first to fourth aspects, a signal is output to the other end of the current path of the first transistor, and the second transistor (the one according to the third and fourth aspects) is output. Then, the wiring is in a floating state except when the electric charge is accumulated in the wiring between the wiring and the third transistor). At this time, the level of the signal supplied to one end of the current path of the second transistor (the one according to the first or second aspect) or the fourth transistor (the one according to the third or fourth aspect) changes. Then, the potential of the wiring changes due to the parasitic capacitance. However, this potential change is absorbed by the capacitor, and the second transistor (the one according to the first and second aspects) or the fourth transistor (the one according to the third and fourth aspects)
The voltage applied to the control terminal becomes stable. Thereby, the second
Without unintended output signal leakage from the other end of the current path of the transistor (the first or second aspect) or the fourth transistor (the third or fourth aspect), The level of the output signal becomes stable.

In the shift register according to the first to fourth aspects, even if the capacitor includes one having the other end connected to a negative power supply line, the other end is connected to a positive power supply line. It may include one that is grounded, or one that has the other end grounded.

In the shift register according to the first to fourth aspects, a signal of a predetermined level supplied to the first transistor is supplied from the outside at a first stage on the side where an output signal becomes active first. It is a start signal supplied at the timing, and may be an output signal of one adjacent stage in other stages.

In the shift register according to the first to fourth aspects, the first signal and the second signal may be different in phase from each other by 180 °.

In the shift register according to the first to fourth aspects, it is preferable that each transistor constituting each of the plurality of stages is a field effect transistor of the same channel type.

To achieve the above object, an electronic device according to a fifth aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element configured by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver has a predetermined level supplied to a control terminal from one adjacent stage. A first transistor that is turned on by a signal and outputs the signal of the predetermined level from one end of the current path to the other end, and a wiring formed between a control terminal and the other end of the current path of the first transistor. A second transistor which is turned on by the accumulated charge and outputs a first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path; An output signal of the other stage adjacent to the third stage is supplied, and when turned on by the output signal of the other stage, a third transistor that releases charges accumulated in the wiring is connected to one end of the third transistor. And a capacitor.

To achieve the above object, an electronic device according to a sixth aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element constituted by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver has a third or fourth signal supplied to a control terminal from outside A first transistor that is turned on by the first stage and outputs a signal of a predetermined level supplied from one of the adjacent stages to one end of the current path to the other end of the current path; and a control terminal and the other of the current path of the first transistor. The first or second signal supplied from the outside to one end of the current path is output from the other end of the current path as an output signal by being turned on by the charge accumulated in the wiring formed between the current path and the other end. And a third transistor that is supplied with an output signal of the other stage adjacent to the control terminal and that is turned on by the output signal of the other stage to release the charge accumulated in the wiring, And a capacitor connected to the wiring.

To achieve the above object, an electronic device according to a seventh aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element configured by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver has a predetermined level supplied to a control terminal from one adjacent stage. A first transistor that is turned on by a signal and outputs the signal of the predetermined level from one end of the current path to the other end, and a wiring formed between a control terminal and the other end of the current path of the first transistor. A second transistor that is turned on by the accumulated charge and emits a signal supplied to one end of the current path via a load from the other end of the current path; a control terminal; and the first transistor It is turned on by the electric charge accumulated in the wiring formed between the other end of the current path, and the first or second signal supplied from the outside to one end of the current path is output from the other end of the current path as an output signal. A third transistor,
The second transistor is turned on by a signal supplied to a control terminal via a load when the second transistor is off, and a signal supplied from the outside to one end of the current path is output from the other end of the current path as an output signal. A fourth transistor, a fifth transistor which is supplied with an output signal of the other stage adjacent to the control terminal, and which is turned on by the output signal of the other stage to release charges accumulated in the wiring; A capacitor connected at one end to the wiring.

In order to achieve the above object, an electronic device according to an eighth aspect of the present invention includes a driver including a plurality of stages, and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal; A driving element constituted by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver has a third or fourth signal supplied to a control terminal from outside A first transistor that is turned on by the first stage and outputs a signal of a predetermined level supplied from one of the adjacent stages to one end of the current path to the other end of the current path; and a control terminal and the other of the current path of the first transistor. A second transistor which is turned on by the electric charge accumulated in the wiring formed between the first and second terminals and emits a signal supplied to one end of the current path via the load from the other end of the current path; And the first or second signal supplied from the outside to one end of the current path as an output signal by being turned on by the electric charge accumulated in the wiring formed between the first transistor and the other end of the current path of the first transistor. A third transistor which is output from the other end of the current path, and which is turned on by a signal supplied to a control terminal via a load when the second transistor is off, and is supplied to one end of the current path from outside Output from the other end of the current path as an output signal.
And a capacitor having one end connected to the wiring.

The electronic devices according to the fifth to eighth aspects have the same configuration as the shift register according to the first to fourth aspects, respectively, as drivers for driving the driving elements. Therefore, the level of the output signal from the driver is stable, and the driving state of the driving element is stable. For this reason, as described below, an image to be displayed has a high image quality when the driving element is a display element, and an image to be captured when the driving element is an imaging element.

In the electronic device according to the fifth to eighth aspects, the driving element may be a display element.

In this case, the display element includes a sixth transistor to which a control terminal is supplied with an output signal of any one of the stages of the driver, and one end of a current path to which image data is supplied from outside, with a pixel. It can be provided for each.

In the electronic device according to the fifth to eighth aspects, the driving element may be an image pickup element.

In this case, the image pickup device includes a semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode connected to both ends of the semiconductor layer, and the semiconductor layer via a first gate insulating film. A first gate electrode provided on one side of the layer and a second gate electrode provided on the other side of the semiconductor layer via a second gate insulating film can be provided for each pixel. The driver includes a first driver that outputs an output signal to the first gate electrode, and a second driver that outputs an output signal to the second gate electrode.

In the electronic device according to the fifth to eighth aspects, the driver may be formed on the same substrate as the drive element.

[0036]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to this embodiment. As shown
This liquid crystal display device includes a liquid crystal display element 1, a gate driver 2, and a drain driver 3. The gate driver 2 has a control signal group Gcnt, and the drain driver 3 has a control signal group Dcnt and display data. data
Are supplied from the controller.

The liquid crystal display element 1 has a structure in which liquid crystal is sealed in a pair of substrates.
The active driving TFTs 11 using i as a semiconductor layer are formed in a matrix. The gate electrode of each TFT 11 is connected to the gate line GL, the drain electrode is connected to the drain line DL, and the source electrode is connected to pixel electrodes similarly formed in a matrix. A common electrode to which a predetermined voltage is applied is formed on the other substrate, and a pixel capacitor 12 is formed by the common electrode, each pixel electrode, and liquid crystal therebetween. Then, the liquid crystal display element 1 displays an image by controlling the amount of transmitted light by changing the alignment state of the liquid crystal by the electric charge accumulated in the pixel capacitor 12.

The gate driver 2 is constituted by a shift register which operates according to a control signal group Gcnt from the controller. The gate driver 2 controls the gate line GL according to a control signal group Gcnt from the controller.
Are sequentially selected to output a predetermined voltage. The shift register constituting the gate driver 2 will be described later in detail.

The drain driver 3 sequentially takes in image data data from the controller according to a control signal group Dcnt from the controller. When the image data data for one line is accumulated, the drain driver 3 outputs this to the drain line DL according to the control signal group Dcnt from the controller, and the TFT 11 connected to the gate line GL selected by the gate driver 2.
(ON state), and is accumulated in the pixel capacitor 12.

FIG. 2 is a diagram showing a circuit configuration of a shift register constituting the gate driver 2 of FIG. Assuming that the number of rows of TFTs 11 (the number of gate lines GL) arranged in the liquid crystal display element 1 is n, this shift register is composed of n stages. FIG. 2 shows the first three stages RS (1) to RS (3).

When applied as the gate driver 2,
In this shift register, the control signal group Gcnt from the controller is supplied to the drain of the odd-numbered TFT 22, the clock signal CK1 serving as the output signal OUT, and the output signal OU is supplied to the drain of the even-numbered TFT 22.
A clock signal CK2 serving as T, a start signal Pst, and a reference voltage Vss are supplied. The start signal Pst is supplied to the first stage RS (1), and the other signals are supplied to all the stages RS (2), RS (3),.

Since the configuration of each stage is substantially the same, the first stage RS (1) will be described as an example.
(1) is the same as the TFT 11 in the same a-
It has four TFTs 21 to 24 made of a semiconductor layer of Si and a capacitor C1. A high-level (reference voltage Vdd) start signal Pst is supplied to the gate and the drain of the TFT 21. The source of the TFT 21 is T
It is connected to the gate of FT22 and the drain of TFT23. A high-level clock signal CK1 is supplied to the drain of the TFT 22, and an output from the drain is output to the first gate line GL as an output signal OUT1 of this stage RS (1).

The gate of the TFT 23 is connected to the source of the TFT 22 of the next stage RS (2), and the TFT 23 turns on when the output signal OUT2 of the next stage RS (2) becomes high. A reset signal φR from the controller is supplied to the gate of the TFT 24, and the potential of the wiring of the output signal OUT1 of this stage RS (1) is reset. TFT2
3 and the source of the TFT 24 are connected to the reference voltage Vss.
(Constant voltage) is supplied. The reference voltage Vss may be a negative value here, but may be a ground level (0
(V)).

The capacitor C1 is a source of the TFT 21,
It is composed of a wiring A connected and surrounded by the gate of the TFT 22 and the drain of the TFT 23, a wiring of the reference voltage Vss, and gate insulating films of the TFTs 21 to 24 disposed therebetween, and one end thereof is a wiring A, and the reference voltage Vss is constantly supplied to the other end. The capacitor C1 has a function of stabilizing the potential on the wiring A in a floating state.

In the case of a structure without the capacitor C1 (same as the conventional example shown in FIG. 18), when the wiring A is floating, that is, when the start signal Pst or the output signal OUT of the preceding stage is at a low level and the control signal φR Is low level (= reference voltage Vss) and the wiring A is in a floating state.
The amplitude of the voltage of the wiring A, which fluctuates because the clock signal CK1 or CK2 rises from a low level to a high level, is a value represented by the following equation 1. However, the clock signal C
The low-level voltage and the high-level voltage of K1 and CK2 are the reference voltages Vss and Vdd, respectively.

[0047]

## EQU1 ## (CA × Vdd + CB × Vss) / (CA + C
B) −Vss = CA × (Vdd−Vss) / (CA + C)
B)

However, the capacitance CA is equal to the clock line (wiring for the clock signal CK1 or wiring for the clock signal CK2).
Parasitic capacitance between the TFT 22 and the wiring A
And the parasitic capacitance between The capacitance CB is Vss
The parasitic capacitance between the power supply line (the wiring of the reference voltage Vss) and the wiring A and the output line B (the output signal OUTk (k: 1
To n)) and the parasitic capacitance between the wiring A and the TFT 2
1, 23 and the parasitic capacitance between the wiring A.

On the other hand, when the capacitor C1 is inserted as in the present embodiment, the capacitance on the reference voltage Vss side of the parasitic capacitance between the wiring A and (CB) is changed from (CB) to (CB).
+ C1), and the amplitude of the voltage of the wiring A becomes
It becomes the value shown by. As can be seen from Equation 2, by inserting the capacitor C1, the amplitude of the voltage of the wiring A decreases, and the maximum level of the voltage of the wiring A decreases.

[0050]

[Equation 2] {CA × Vdd + (CB + C1) × Vss)}
/ (CA + CB + C1) −Vss = CA × (Vdd−V
ss) / (CA + CB + C1)

The odd-numbered stages RS (2k +
1) (k: an integer of 1 to n / 2, where n is the number of gate lines GL) is such that the output signal OUT (2k) of the previous stage RS (2k) is supplied to the gate and drain of the TFT 21. Otherwise, it is the same as the first stage RS (1). The configuration of the even-numbered stage RS (2k) is such that the output signal OU of the previous stage RS (2k-1) is connected to the gate and the drain of the TFT 21.
It is the same as the first stage RS (1) except that T (2k-1) is supplied and the clock signal CK2 is supplied to the drain of the TFT 22.

The shift register constituting the gate driver 2 is constituted by a combination of TFTs 21 to 24. The TFTs 21 to 24 have substantially the same structure as the TFT 11 included in the liquid crystal display element 1. Therefore, the gate driver 2 operates at the T
It can be formed on the substrate on the FT 11 side by the same process at once.

Hereinafter, the operation of the liquid crystal display device according to this embodiment will be described. Here, first, an operation performed by the gate driver 2 to sequentially select display pixels of the liquid crystal display element 1 line by line will be described.
The operation of the entire liquid crystal display device will be described.

FIG. 3 is a timing chart showing the operation of the bootstrap type shift register constituting the gate driver 2 of FIG. In this figure, the period of 1T is one line period (the selection period of each gate line GL is one line period).
T), and the period of 1F is one frame period.

When the start signal Pst goes high during the timing T0 to T1, the TFT 21 of the first stage RS (1) is turned on, and this signal is output from the drain of the TFT 21 to the source. Thereby, the first stage RS
The potential of the wiring A (1) in (1) becomes high level. Since the gate voltage of the TFT 22 becomes high level in this way, the TFT 22 turns on, but the level of the output signal OUT1 remains low because the clock signal CK1 supplied to the drain is low level.

Next, when the clock signal CK1 changes to the high level at the timing T1, this changes to the TFT2.
2 is output from the drain to the source, and the output signal OUT
The level of 1 changes to a high level. At this time, since the potential of the wiring A rises to a high voltage due to the bootstrap effect, it reaches the saturation gate voltage of the TFT 22, and the output signal OUT1 becomes almost equal in potential to the high level of the clock signal CK1. Thereafter, immediately before the timing T2, when the clock signal CK1 falls and the control signal φR rises, the charge on the output line B (1) is released from the signal line of the reference voltage Vss, so that the gate line The output signal OUT1 output to the GL forcibly changes to a low level.

In the period between timings T1 and T2,
High level output signal O of the first stage RS (1)
The TFT 21 of the second stage RS (2) is turned on by the UT1, the potential of the wiring A (2) becomes high level, and
The TFT 22 in the second stage RS (2) turns on.

Next, when the clock signal CK2 changes to the high level at the timing T2, the clock signal CK2 is output from the drain to the source of the TFT 22, and the level of the output signal OUT2 changes to the high level. At this time, since the potential of the wiring A rises to a high voltage due to the bootstrap effect, the output signal OUT2 becomes almost equal to the high level of the clock signal CK2. Then, immediately before timing T3, the clock signal CK
When 2 falls and the control signal φR rises,
When the charge on the output line B (2) is released from the signal line of the reference voltage Vss, the output signal OUT2 output to the gate line GL changes to a low level.

During the period between timings T2 and T3, the output signal OU of the second stage RS (2) attained the high level.
By T2, the TFT 23 of the first stage RS (1) is turned on, and the charges accumulated in the wiring A (1) are discharged to the ground. Thereby, the TFT2 of the first stage RS (1)
2 is turned off, and the TFT 22 does not turn on until the next time the start signal Pst is supplied and the electric charge is accumulated in the wiring A (1). Further, the TFT 21 of the third stage RS (3) is turned on by the output signal OUT2 of the second stage RS (2) which has become high level, and the potential of the wiring A (3) becomes high level. T of the third stage RS (3)
The FT 22 turns on.

Next, when the clock signal CK1 changes to the high level at the timing T3, the output signal OUT3 of the third stage RS (3) similarly changes to the high level. In addition, the output signal OU at the high level
By T3, the TFT 23 of the second stage RS (2) is turned on, and the charge accumulated in the wiring A (2) is discharged to the ground. Hereinafter, similarly, until the timing Tn,
The output signal of each stage becomes high level for each predetermined period within one line period, and the gate lines GL of the liquid crystal display element 1 are sequentially selected. Thus, the output signals OUT1 to OUT1
Since the high-level potential of n does not decrease gradually even if it is shifted to the next stage, malfunction is unlikely to occur.

For example, after the timing T2, 1
The charge is released from the wiring A of the first stage RS (1) to TF
T21 also remains in the OFF state and enters the floating state. When the clock signal CK1 goes high in this state, the potential of the wiring A increases due to the parasitic capacitance of the TFT 22. However, since the increase in the potential is suppressed by the capacitor C1, the rise is not as large as that in the configuration without the capacitor C1. Also, the TF of the final stage RS (n)
Only the gate of T23, TFT of the first stage RS (1)
21 together with the gate and drain of the start signal Pst
Is supplied, and when the start signal Pst is at a high level, the potential of the wiring A (n) of the final stage RS (n) is discharged.

Next, the operation of the whole liquid crystal display device will be described. While the gate driver 2 sequentially outputs high-level signals to each gate line GL as described above, the drain driver 3 fetches image data data from the controller one line at a time in accordance with the control signal group Dcnt. The capture of one line of image data is performed within one line period, and ends before the corresponding gate line GL is selected.

When the gate driver 2 selects any one of the gate lines GL and outputs a high-level signal, all the TFTs 11 for one line connected thereto are turned on.
The drain driver 3 reads the 1
A voltage corresponding to the image data data for the line is output to each drain line DL. Thereby, the image data da
The voltage corresponding to ta is stored in the pixel capacitor 12. Accordingly, the alignment state of the liquid crystal between the electrodes of the pixel capacitor 12 changes, and the light transmittance of the pixel changes.

Since the voltage stored in the pixel capacitor 12 is held until the corresponding gate line GL is selected in the next frame period, the light transmittance of each pixel is substantially 1
The frame period is maintained. By sequentially repeating such operations, an image is displayed on the liquid crystal display element 1.

As described above, in the liquid crystal display device according to this embodiment, the shift register applied to the gate driver 2 includes the stages RS (1), RS (2),
, A capacitor C1 is inserted. When the wiring A is in a floating state and the clock signal CK1 or CK2 supplied from the controller is at a high level, the capacitor C1 is connected to the TFT 2 in the off state.
2 reduces the rise in potential due to the influence of the parasitic capacitance.

As a result, the gate voltage of the TFT 22 exceeds the threshold voltage, and the clock signal CK1 or CK2
Can be prevented from leaking as output signals OUT1, OUT2,.
The levels of 2,..., Especially during the non-selection period of the line, can be stabilized.

Since such a shift register is used as the gate driver 2, the TFT 11 of the liquid crystal display element 1, which should not be selected, does not turn on. Therefore, there is no possibility that unintended data is written to each pixel capacitor 12. For this reason,
A high quality image can be displayed on the liquid crystal display element 1.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

The structure of the shift register applied as the gate driver 2 shown in the above embodiment can be changed as appropriate. Hereinafter, other shift registers applicable as the gate driver 2 will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 4 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 2 of FIG. In this shift register, each stage RS (1), RS
(2),... Have one end connected to the wiring A and the other end connected to the power supply voltage Vdd instead of the capacitor C1 shown in FIG.
Has the capacitor C2 connected to the wiring of FIG. this is,
Of the parasitic capacitance between the power supply voltage Vdd and the wiring A,
The capacitance C2 increases on the side of the clock signal CK1 while the wiring A is floating under the same conditions as in FIG.
Alternatively, the amplitude of the voltage on the wiring A, which is displaced when CK2 rises from the low level to the high level, is expressed by the following equation (3).
, And can be made smaller than when there is no capacitor C2.

[0071]

[Equation 3] {CA × Vdd + (CB + C2) × Vss} /
(CA + CB + C2) −Vss = CA × (Vdd−Vs)
s) / (CA + CB + C2)

FIG. 5 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. In this shift register, each stage RS (1), R
S (2),... Have a capacitor C3 having one end connected to the wiring A and the other end grounded, instead of the capacitor C1 shown in FIG. This is the addition of a new capacitor that did not exist originally. Here, the amplitude of the voltage on the wiring A, which is displaced when the clock signal CK1 or CK2 rises from a low level to a high level under the same conditions as in FIG.
Can be smaller than without.

[0073]

[Equation 4] {CA × Vdd + (CB + C3) × Vss} /
(CA + CB + C3) −Vss = CA × (Vdd−Vs)
s) / (CA + CB + C3)

FIG. 6 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. In this shift register, each stage RS (1), R
S (2),... Represent the capacitor C1 shown in FIG. 2, the capacitor C2 shown in FIG. 4, and the capacitor C shown in FIG.
It has all three. Here, the amplitude of the voltage on the wiring A that is displaced when the clock signal CK1 or CK2 rises from a low level to a high level under the same conditions as in FIG.
The size can be further reduced as compared with the case where only one of C2 and C3 is provided. Note that each stage is a capacitor C
It is also possible to use a combination of only one of C1, C2, and C3, or a combination of only two.

[0075]

｛CA × Vdd + (CB + C1 + C2 + C3)
× Vss｝ / (CA + CB + C1 + C2 + C3) −Vs
s = CA × (Vdd−Vss) / (CA + CB + C1 +
C2 + C3)

FIG. 7 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register includes RS (1), RS (
(2),... Have a TFT 24 ′ in place of the TFT 24 and are different from the shift register shown in FIG. 6 in that there is no input of the control signal φR. In this case, it is possible to set CK2 = ¬CK1 (¬: logical negation).

The TFT 24 ′ has its gate receiving the clock signal CK 2 (in the case of the odd-numbered stage) or the clock signal C
K1 (for the even-numbered stage) is supplied. TFT2
The drain of 4 ′ is a TFT similar to the TFT 24 described above.
22 is connected to the source of the TFT 24 '.
The reference voltage Vss is supplied.

Next, the function of the TFT 24 'will be described by taking the first stage RS (1) as an example. At the timing when the control signal φR rises in the timing chart of FIG. 3, the electric charge accumulated in the wiring capacitance Cb (1) is released only through the TFT 22 which is still on. However, when the clock signal CK2 rises at timing T2, which is the selection period of the second line, the TFT 24 '
Turns on. As a result, the charge remaining on the wiring capacitance Cb is immediately discharged via the TFT 24 ', and the timing T
The first gate line GL that is not selected from 2
Becomes low level.

FIG. 8 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register includes RS (1), RS (
(2),... Do not have the TFT 24 and three TFTs 2
The difference from the shift register shown in FIG. The driving operation is substantially the same as that shown in the timing chart of FIG. 3, except that there is no input of the control signal φR. In this case, the amplitude of the voltage on the wiring A is substantially the same as in Expression 5. In addition,
Any one of the capacitors C1, C2, C3, or 2
It is also possible to combine them.

The TFT 24 shown in FIG. 2 discharges the electric charge accumulated in the wiring B to the ground, and the gate line GL
This is for stabilizing the potential of the wiring B including at a low level. However, when the clock signal CK1 or CK2 changes from the high level to the low level, the charge accumulated in the wiring B can be released through the TFT 22 which is still in the ON state.

Then, in the next line period, TFT2
The TFT 24 is not necessarily required as long as the charge accumulated in the wiring B can be released until the potential of the gate line GL can be made lower than the threshold voltage of the TFT 11 of the liquid crystal display element 1 until the switch 2 is turned off. Therefore, a shift register having a configuration as shown in FIG.
It is also possible to apply as.

FIG. 9 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register includes RS (1), RS (
(2),... Have a TFT 21 ′ instead of the TFT 21, and a signal φ as a control signal group Gcnt.
The difference from the shift register shown in FIG. 6 is that 1, and φ2 are further supplied from the controller. Note that a combination of any one or two of the capacitors C1, C2, and C3 is also possible. The signals φ1 and φ2 are both set to the same potential as the high level Vdd and the low level Vss.

The TFT 21 'has a signal φ1 at its gate.
(Odd-numbered stage) or signal φ2 (even-numbered stage) is supplied. The signal is turned on when the signal φ1 or φ2 becomes high level, and the start signal supplied to the drain or the output signal of the previous stage Is output from the source and accumulated in the wiring A.

Next, the operation of the shift register shown in FIG. 5 when applied as the gate driver 2 will be described with reference to the timing chart of FIG.
Here, only the operation of the shift register shown in FIG. 4, that is, the portion different from the operation shown in the timing chart of FIG. 3 will be described.

In a predetermined period from timing T0 to T1, signal φ1 changes to high level. This allows
The TFT 21 of the first stage RS (1) is turned on. At this time, the start signal Pst supplied to the drain of the TFT 21 is output from the source, and the first stage RS (1)
The electric charge is accumulated in the wiring A (1), and the wiring capacitance Ca (1)
Becomes high level.

In the period between timings T1 and T2,
When the signal φ2 changes to the high level for a predetermined period, the level of the wiring A (2) of the second stage RS (2) similarly becomes the high level. During the period from the timing T2 to the timing T3, the signal A1 changes to the high level, so that the wiring A (3) of the third stage RS (3) similarly becomes the high level. Hereinafter, similarly, when the signal φ1 or φ2 changes to the high level, the wiring A of each stage sequentially changes to the high level.

FIG. 11 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Are replaced with TFT24 ′ instead of TFT24.
And the shift register shown in FIG. 9 is different from the shift register shown in FIG. The function of the TFT 24 'is shown in FIG.
Is the same as that shown in FIG. Note that each stage is a capacitor C
It is also possible to use only one of C1, C2 and C3, or a combination of only two.

FIG. 12 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Do not have a TFT 24 and three TFTs
The shift register shown in FIG. 9 is different from the shift register shown in FIG. Each stage RS (1), RS
The reason why (2),... Can be constituted by only three TFTs is the same as that shown in FIG. Note that a combination of any one or two of the capacitors C1, C2, and C3 is also possible.

FIG. 13 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Are six TFTs 21 to 23, 25 to 25
2 and FIGS. 4 to 9 and FIG.
The driving operation is different from that of the shift register shown in FIGS. However, the control signal group Gc
The signal supplied as nt has the same type and timing as those shown in the timing chart of FIG. 3 except that it does not include the control signal φR.

In this shift register, each stage RS
(1), RS (2),... Are the source of the TFT 21,
Gate of TFT22, Gate of TFT26 and TFT2
3, a wiring A similar to that of the shift register shown in FIGS. 2, 4 to 9, 11, and 12 is formed. Each stage RS (1), RS (2), ...
The capacitors C1, C2, and C3 of FIG.
As in the case of the shift register shown in FIGS. 4 to 9, 11 and 12, it has a function of stabilizing the potential on the wiring A in a floating state.

In the structure without the capacitors C1, C2 and C3 from the shift register shown in FIG. 13, when the wiring A is floating, that is, when the start signal Pst or the output signal OUT of the preceding stage is at a low level and the control signal φR is low. When the wiring A is at a low level (= reference voltage Vss) and the wiring A is in a floating state, the amplitude of the voltage of the wiring A that fluctuates because the clock signal CK1 or CK2 rises from the low level to the high level is a value represented by the following equation 6. Becomes

[0092]

## EQU6 ## (CX × Vdd + CY × Vss) / (CX + C
Y) −Vss = CX × (Vdd−Vss) / (CX + C
Y)

Here, CX is the sum of the parasitic capacitance between the clock line (the wiring of the clock signals CK1 and CK2) and the wiring A, and the parasitic capacitance between the TFT 22 and the wiring A. CY is a parasitic capacitance between the Vss power supply line (wiring for the reference voltage Vss) and the wiring A, a parasitic capacitance between the output line (wiring for the output signals OUTk (k: 1 to n)) and the wiring A, and Each of the TFTs 21, 23, 26 and the wiring A
Is the sum of the parasitic capacitances between

On the other hand, when the capacitors C1, C2, and C3 are inserted as shown in FIG. 13, the voltage amplitude of the wiring A becomes a value represented by the following equation (7). As can be seen from Expression 7, by inserting the capacitors C1, C2, and C3, the amplitude of the voltage of the wiring A decreases, and the maximum level of the voltage of the wiring A decreases.

[0095]

７CX × Vdd + (CY + C1 + C2 + C3)
× Vss｝ / (CX + CY + C1 + C2 + C3) −Vs
s = CX × (Vdd−Vss) / (CX + CY + C1 +
C2 + C3)

In this shift register, each stage RS (1), RS (2),.
A configuration having only one of C1, C2, and C3, or only two of them is also possible. In the missing portion of the capacitor, C
By substituting 0 for 1, C2, and C3, the amplitude of the voltage on the wiring A can be obtained. In any case, the amplitude of the voltage on the wiring A can be reduced as compared with the case where no capacitor is provided. Further, the TFT 25 may be replaced with another resistance element.

Next, the timing chart shown in FIG.
13 (excluding R), the operation of the shift register shown in FIG. 13 will be described by taking the first stage RS (1) as an example.

When the start signal Pst goes high during the timing T0 to T1, the TFT 21 of the first stage RS (1) is turned on and output to the source side, so that the first stage RS (1) is output. The potential of the wiring A (1) of 1) becomes a high level. Thus, the TFTs 22 and 26 are turned on.
When the TFT 26 is turned on, the TFT 25 and the TF
The charge accumulated in the wiring between T26 is released,
The TFT 27 that has been on until that time is turned off.

Next, when the clock signal CK1 changes to the high level at the timing T1, the TFT 22 is turned on and the TFT 27 is turned off, so that this signal is substantially output as the output signal OUT1. TFT21,
Since 23 is in the off state, the potential of the wiring A increases due to the parasitic capacitance of the TFT 22. Immediately before the timing T2, when the clock signal CK1 falls, the output signal OUT1 changes to a low level. In the period from timing T1 to timing T2, the first stage RS
By the output signal OUT1 of (1), the second stage RS
The wiring A (2) of (2) becomes high level, the TFTs 22 and 26 of the second stage RS (2) are turned on, and the TFT 27 is turned off.

Next, at timing T2, when the clock signal CK2 changes to the high level,
This is output as the output signal OUT2 of the second stage RS (2). By this output signal OUT2, the first stage RS
The TFT 23 of (1) is turned on, and the charge accumulated in the wiring A (1) of the first stage RS (1) is released. As a result, the TFT 22 of the first stage RS (1) is turned off,
26 is turned off, the TFT 27 is turned on, and even if the clock signal CK1 subsequently changes to the high level, the output signal OUT1
Does not go to high level.

If the clock signal CK2 falls just before the timing T3, the output signal OUT2 changes to low level. Further, timing T2 to timing T3
In the period up to the second stage RS
By the output signal OUT2 of (2), the third stage RS
The wiring A (3) of (3) becomes high level, and the TFTs 22 and 26 of the third stage RS (3) are turned on and the TFT 27 is turned off.

Next, when the clock signal CK1 changes to the high level at the timing T3, the output signal OUT3 of the third stage RS (3) similarly changes to the high level. By this output signal OUT3, the second stage R
The charges accumulated in the wiring A (2) of S (2) are released. High-level CK1 is continuously input to the TFT 22 of the first stage RS (1), but the capacitors C1, C2, C
3, the amplitude of the wiring A (1) is suppressed. Less than,
Similarly, until the timing Tn, the output signal of each stage becomes high level for each predetermined period of one line period.

FIG. 14 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Are replaced with TFT21 ′ instead of TFT21.
13. The shift register shown in FIG. 13 is different from the shift register shown in FIG. 13 in that the TFTs 23 are not provided, and the signals φ1 and φ2 are further supplied from the controller as the control signal group Gcnt. The function of the TFT 21 'is the same as that shown in FIG. In addition, it is also possible to use a combination of only one of the capacitors C1, C2, and C3, or a combination of only two of them.

In this shift register, for example, when the control signal φ1 rises between timings T2 and T3, the TFT 21 of the first stage RS (1) turns on.
Accordingly, the charge stored in the wiring A (1) is released through the signal line of the start signal Pst. Also,
When the control signal φ2 rises between the timings T3 and T4, the TFT 21 of the second stage RS (2) turns on. As a result, the electric charge stored in the wiring A (2) is released via the TFT 27 (in the ON state) of the previous stage RS (1). Therefore, the shift register shown in FIG. 14 does not need to have the TFT 23 included in the shift register having each configuration described above.

FIG. 15 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Interpose the TFT 28 between the source of the TFT 21 and the wiring A. The TFT 28 has a wiring A
Is TFT2 due to voltage rise due to bootstrap effect
In this case, a remarkable difference in voltage between the source and the drain of the TFT 21 is buffered, thereby preventing the TFT 21 from being destroyed. Regarding the driving method, the waveform chart of each signal is the same as in FIG. Note that each stage is a capacitor C
It is also possible to use only one of C1, C2 and C3 or a combination of only two.

FIG. 16 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 2 of FIG. This shift register is composed of RS (1), R
S (2),... Interpose the TFT 28 between the source of the TFT 21 and the wiring A. The TFT 28 has a wiring A
Is TFT2 due to voltage rise due to bootstrap effect
1 is for buffering a remarkable difference in voltage between the source and the drain, thereby preventing the TFT 21 from being destroyed. Each stage is composed of capacitors C1, C2, C
It is also possible to use a combination of only one of the three or only two.

In the above embodiment, the present invention has been described by taking as an example a liquid crystal display device in which the shift register having the above configuration is applied as the gate driver 2. However, the present invention relates to an inorganic EL display device, an organic EL display device,
The present invention can be applied to other types of display devices such as an FED and a plasma display device. Also in this case, the shift register having the above configuration can be applied as a driver for sequentially selecting display pixels arranged in a matrix for each line.

Further, the present invention can be applied not only to a display device but also to an image pickup device in which an image pickup device in which photo sensors (image pickup pixels) are arranged in a matrix is driven by the shift register having the above configuration. Such an imaging device will be described as an example in which a so-called double gate transistor is applied as a photosensor.

FIG. 17 is a block diagram showing the configuration of an imaging apparatus applicable to fingerprint authentication according to this modification.
As shown in the figure, the imaging apparatus includes an imaging device 5 for capturing an image, and a top gate driver 6, a bottom gate driver 7, and a drain driver 8 for driving the imaging device 5 according to a control signal from a controller. I have.

The image sensor 5 is composed of a plurality of double gate transistors 51 arranged in a matrix. Top gate electrode 101 of double gate transistor 51
Represents the top gate line TGL and the bottom gate electrode 10
2 is the drain electrode 103 on the bottom gate line BGL.
Is connected to the drain line DL, and the source electrode 104 is connected to the ground line GrL.
Below the image sensor 5, a double gate transistor 51 is provided.
A backlight that emits light in the wavelength range that excites the semiconductor layer is mounted.

In the double gate transistor 51 constituting the image pickup device 5, when the voltage applied to the top gate electrode 101 is +25 (V) and the voltage applied to the bottom gate electrode 102 is 0 (V). Then, holes accumulated in the gate insulating film made of silicon nitride and the semiconductor layer disposed between the top gate electrode 101 and the semiconductor layer are discharged and reset. The double gate transistor 51 has 0 between the source and drain electrodes 103 and 104.
In (V), the voltage applied to the top gate electrode 101 is −15 (V), and the voltage applied to the bottom gate electrode 102 is 0 (V), which is generated by light incident on the semiconductor layer. The holes of the hole-electron pairs enter a photo-sensing state in which the holes are accumulated in the semiconductor layer and the gate insulating film. The amount of holes accumulated during this predetermined period depends on the amount of light.

In the photo-sensing state, the backlight irradiates light toward the double gate transistor 51. However, if this state is maintained, the bottom gate electrode 102 located below the semiconductor layer of the double gate transistor 51 shields light, so that the semiconductor layer has sufficient light. No carrier is generated. At this time, when a finger is placed on the insulating film above the double gate transistor 51, the semiconductor layer of the double gate transistor 51 immediately below the concave portion of the finger (corresponding to the groove for determining the fingerprint shape) is reflected by the insulating film or the like. The light applied to the top gate electrode 101 is reduced by -15 without receiving much light and storing a sufficient amount of holes in the semiconductor layer.
In (V), when the voltage applied to the bottom gate electrode 102 becomes +10 (V), the depletion layer spreads in the semiconductor layer, the n-channel is pinched off, and the semiconductor layer has high resistance.

On the other hand, in the photo-sensing state, light reflected by an insulating film or the like is sufficiently incident on the semiconductor layer of the double gate transistor 51 immediately below the convex portion of the finger (the crest between the grooves of the finger). When such a voltage is applied in a state where a large amount of holes are accumulated in the semiconductor layer, the accumulated holes are attracted to and held by the top gate electrode 101, so that the semiconductor layer Is formed on the side of the bottom gate electrode 102, and the semiconductor layer has low resistance. The difference between the resistance values of the semiconductor layers in these read states appears as a change in the potential of the drain line DL.

The top gate driver 6 is connected to the top gate line TGL of the image sensor 5 and selects a signal of +25 (V) or -15 (V) for each top gate line TGL according to a control signal group Tcnt from the controller. Output. The top gate driver 6 excludes the difference in the level of the output signal, the difference in the level of the input signal corresponding thereto, and the difference in the phase of the output signal and the input signal.
It has substantially the same configuration as the shift register constituting the gate driver 2 described above.

The bottom gate driver 7 is connected to the bottom gate line BGL of the image sensor 5 and outputs a signal of +10 (V) or 0 (V) to each bottom gate line BGL according to a control signal group Bcnt from the controller. . The bottom gate driver 7 is substantially the same as the shift register constituting the gate driver 2 except for the difference in the level of the output signal, the difference in the level of the input signal corresponding thereto, and the difference in the phase of the output signal and the input signal. Have the same configuration.

The drain driver 8 is connected to the drain line DL of the image sensor 5, and outputs a constant voltage (+10 (V)) to all the drain lines DL in a predetermined period described later according to a control signal group Dcnt from the controller. Then, the electric charges are precharged. Drain driver 8
Reads out the potential of each drain line DL that changes according to the incidence or non-incidence of light on the semiconductor layer of the double gate transistor 51 during a predetermined period after the precharge, that is, whether or not a channel is formed, It is supplied to the controller as image data DATA.

When an image is taken by the image pickup apparatus, control signal groups Tcnt and Bcnt from the controller are used.
Accordingly, a signal of a predetermined level is output from the top gate driver 6 and the bottom gate driver 7 at a predetermined timing for each line, whereby each line of the image sensor 5 is sequentially set to a reset state, a photo sense state, and a read state. Then, a change in the potential of the drain line DL due to a change in the resistance of the semiconductor layer of the double gate transistor 51 in the line in the read state may be read by the drain driver 8 and supplied to the controller as image data DATA.

Further, the shift register having the configuration in the above-described embodiment or a modified configuration thereof as described above may be applied to applications other than the use as a driver for driving an image sensor or a display device. Can be. For example, these shift registers can be applied to applications such as converting serial data to parallel data in a data processing device or the like.

The shift registers constituting the gate driver 2, the top gate driver 6, and the bottom gate driver 7 in the above embodiment are constituted by a combination of TFTs as field effect transistors. Transistor.
Further, the TFTs constituting the shift register are of the n-channel type, but may be all of the p-channel type. At this time, the high and low levels of each signal need only be set so as to be inverted from each other as compared with the case of n channels.

[0120]

As described above, according to the shift register of the present invention, the level of the output signal from each stage is stabilized.

Further, by applying such a shift register as a driver, it is possible to increase the image quality of an image to be displayed or to enhance the image quality of a captured image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a shift register applied as the gate driver in FIG.

FIG. 3 is a timing chart showing the operation of the shift register of FIG.

FIG. 4 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

FIG. 5 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

FIG. 6 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

FIG. 7 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

FIG. 8 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

9 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

FIG. 10 is a timing chart showing the operation of the shift register of FIG.

11 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

12 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

13 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

14 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 1;

15 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 6;

16 is a diagram illustrating another circuit configuration of the shift register applied as the gate driver in FIG. 7;

FIG. 17 is a block diagram illustrating a configuration of an imaging device according to a modification of the embodiment of the present invention.

FIG. 18 is a diagram illustrating a circuit configuration of a conventional shift register.

FIG. 19 is a diagram illustrating a circuit configuration of a conventional shift register.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display element, 2 ... Gate driver, 3 ... Drain driver, 5 ... Image sensor, 11 ... TFT, 12 ... Pixel capacitance, 21-27, 21 ', 24' ... TFT, 51 ... Double gate transistor, 6 ... Top gate driver, 7
... Bottom gate driver, 8 ... Drain driver, C1
~ C3 ... capacitor, RS (1) ~ RS (3) ... stage, G
L: gate line, DL: drain line, TGL: top gate line, BGL: bottom gate line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G11C 19/00 J G11C 19/00 19/28 D 19/28 G02F 1/136 500 F term (Ref.)

Claims (21)

[Claims] 1. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on by a signal of a predetermined level supplied from one of adjacent stages to a control terminal, and the signal of the predetermined level is turned on. A first transistor that outputs from one end of the current path to the other end, and is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor that outputs the first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and an output signal of the other stage adjacent to the control terminal, A shift register, comprising: a third transistor that is turned on by an output signal of the other stage to release charges accumulated in the wiring; and a capacitor having one end connected to the wiring. 2. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on by a third or fourth signal supplied from the outside to a control terminal, and receives a current from one of adjacent stages. A first transistor that outputs a signal of a predetermined level supplied to one end of the path to the other end of the current path, and accumulates in a wiring formed between a control terminal and the other end of the current path of the first transistor Turned on by the applied charge,
A second transistor that outputs the first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and an output signal of the other stage adjacent to the control terminal, A shift register, comprising: a third transistor that is turned on by an output signal of the other stage to release charges accumulated in the wiring; and a capacitor having one end connected to the wiring. 3. A predetermined control signal which rises after the first or second signal falls is supplied to a control terminal,
A fourth transistor configured to be turned on by the predetermined control signal so as to release charges accumulated in a signal line for outputting an output signal from the other end of the current path of the second transistor. The shift register according to claim 1 or 2, wherein 4. A method according to claim 1, wherein a first or second signal supplied to one end of a current path of said second transistor in an adjacent stage is supplied to a control terminal and turned on by said first or second signal. 3. The device according to claim 1, further comprising: a fourth transistor configured to discharge a charge accumulated in a signal line for outputting an output signal from the other end of the current path of the second transistor. Shift register. 5. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on by a signal of a predetermined level supplied from one of adjacent stages to a control terminal, and the signal of the predetermined level is turned on. A first transistor that outputs from one end of the current path to the other end, and is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor for emitting a signal supplied to one end of the current path via a load from the other end of the current path; and a wiring formed between a control terminal and the other end of the current path of the first transistor Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and via a load when the second transistor is off. A fourth transistor that is turned on by a signal supplied to the control terminal and outputs from the other end of the current path as an output signal a signal supplied from the outside to one end of the current path; A fifth transistor that is supplied with an output signal and that is turned on by the output signal of the other stage to release charges accumulated in the wiring; and a capacitor having one end connected to the wiring. Shift register. 6. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on by a third or fourth signal supplied to a control terminal from the outside, and receives a current from one of adjacent stages. A first transistor that outputs a signal of a predetermined level supplied to one end of the path to the other end of the current path, and accumulates in a wiring formed between a control terminal and the other end of the current path of the first transistor Turned on by the applied charge,
A second transistor for emitting a signal supplied to one end of the current path via a load from the other end of the current path; and a wiring formed between a control terminal and the other end of the current path of the first transistor Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and via a load when the second transistor is off. A fourth transistor that is turned on by a signal supplied to the control terminal and outputs from the other end of the current path as an output signal a signal supplied from the outside to one end of the current path; and a capacitor having one end connected to the wiring. And a shift register comprising: 7. The shift register according to claim 1, wherein the other end of the capacitor includes a capacitor connected to a negative power supply line. 8. The shift register according to claim 1, wherein the other end of the shift register includes a capacitor connected to a positive power supply line. 9. The shift register according to claim 1, wherein the capacitor includes a capacitor whose other end is grounded. 10. A signal of a predetermined level supplied to the first transistor is a start signal supplied at a predetermined timing from the outside at an end stage on the side where an output signal becomes active first. 10. The shift register according to claim 1, wherein the output signal of one of the stages is an output signal of one adjacent stage. 11. The shift register according to claim 1, wherein the first signal and the second signal have phases different from each other by 180 °. 12. The transistor according to claim 1, wherein each of the transistors constituting each of the plurality of stages is a same-channel type field effect transistor.
The shift register according to the paragraph. 13. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. Each stage of the driver is turned on by a signal of a predetermined level supplied from one of the adjacent stages to a control terminal, and the signal of the predetermined level is turned from one end to the other end of the current path. A first transistor that outputs a current to the first transistor, and is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor that outputs the first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and an output signal of the other stage adjacent to the control terminal, An electronic device, comprising: a third transistor that is turned on by an output signal of the other stage to release charges stored in the wiring; and a capacitor having one end connected to the wiring. 14. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. Each stage of the driver is turned on by a third or fourth signal externally supplied to a control terminal, and supplied to one end of a current path from one of the adjacent stages. A first transistor that outputs a signal of a predetermined level to the other end of the current path; and a first transistor that is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor that outputs the first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and an output signal of the other stage adjacent to the control terminal, An electronic device, comprising: a third transistor that is turned on by an output signal of the other stage to release charges stored in the wiring; and a capacitor having one end connected to the wiring. 15. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. Each stage of the driver is turned on by a signal of a predetermined level supplied from one of adjacent stages to a control terminal, and the signal of the predetermined level is turned from one end to the other end of the current path. A first transistor that outputs a current to the first transistor, and is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor for emitting a signal supplied to one end of the current path via a load from the other end of the current path, and a wiring formed between a control terminal and the other end of the current path of the first transistor Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and via a load when the second transistor is off. A fourth transistor which is turned on by a signal supplied to the control terminal and outputs from the other end of the current path as an output signal a signal supplied from the outside to one end of the current path; A fifth transistor that is supplied with an output signal and that is turned on by the output signal of the other stage to release charges accumulated in the wiring; and a capacitor having one end connected to the wiring. Electronic device. 16. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver Each stage of the driver is turned on by a third or fourth signal externally supplied to a control terminal, and supplied to one end of a current path from one of the adjacent stages. A first transistor that outputs a signal of a predetermined level to the other end of the current path; and a first transistor that is turned on by a charge accumulated in a wiring formed between a control terminal and the other end of the current path of the first transistor;
A second transistor for emitting a signal supplied to one end of the current path via a load from the other end of the current path; and a wiring formed between a control terminal and the other end of the current path of the first transistor Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path as an output signal from the other end of the current path, and via a load when the second transistor is off. A fourth transistor that is turned on by a signal supplied to the control terminal and outputs from the other end of the current path as an output signal a signal supplied from the outside to one end of the current path; and a capacitor having one end connected to the wiring. An electronic device comprising: 17. The electronic device according to claim 13, wherein the driving element is a display element. 18. The display device according to claim 17, further comprising: a sixth transistor to which a control terminal is supplied with an output signal of any one of the stages of the driver and one end of a current path to which image data is externally supplied. The electronic device according to claim 17, comprising: 19. The electronic device according to claim 13, wherein said drive element is an image pickup element. 20. The imaging device, comprising: a semiconductor layer that generates carriers by excitation light; a drain electrode and a source electrode connected to both ends of the semiconductor layer; and a first gate insulating film. The first provided on one side
A gate electrode, and a second gate electrode provided on the other side of the semiconductor layer via a second gate insulating film for each pixel, wherein the driver outputs an output signal to the first gate electrode. And a second driver for outputting an output signal to the second gate electrode.
An electronic device according to claim 1. 21. The electronic device according to claim 13, wherein the driver is formed on the same substrate as the drive element.