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JP4621432B2 - Printed wiring board and manufacturing method thereof - Google Patents

Printed wiring board and manufacturing method thereof Download PDF

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Publication number
JP4621432B2
JP4621432B2 JP2004028083A JP2004028083A JP4621432B2 JP 4621432 B2 JP4621432 B2 JP 4621432B2 JP 2004028083 A JP2004028083 A JP 2004028083A JP 2004028083 A JP2004028083 A JP 2004028083A JP 4621432 B2 JP4621432 B2 JP 4621432B2
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bump
metal layer
layer
wiring board
printed wiring
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JP2005223056A (en
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主税 酒井
義春 宇波
富士夫 崎山
裕史 稲谷
朝雄 飯島
健治 大沢
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Fujikura Ltd
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Description

この発明は、プリント配線板およびその製造方法に関し、特に、金属製のバンプによって層間導通を得る構造のプリント配線板およびその製造方法に関するものである。   The present invention relates to a printed wiring board and a manufacturing method thereof, and more particularly to a printed wiring board having a structure in which interlayer conduction is obtained by a metal bump and a manufacturing method thereof.

従来、金属層上にエッチング等によって金属製のバンプ(突起)を形成し、この金属層のバンプ形成面に、層間絶縁層となる接着シートをバンプ頂部が露出するように接着し、層間絶縁層上にもう1枚の金属層を貼り合わせ、これら金属層をエッチング処理して両面に導体回路が形成され、前記バンプが層間導通部をなす構造のプリント配線板がある(例えば、特許文献1、2参照)。   Conventionally, a metal bump (protrusion) is formed on a metal layer by etching or the like, and an adhesive sheet to be an interlayer insulating layer is bonded to the bump forming surface of the metal layer so that the bump top portion is exposed. There is a printed wiring board having a structure in which another metal layer is bonded on top of each other, a conductive circuit is formed on both surfaces by etching these metal layers, and the bumps form interlayer conductive portions (for example, Patent Document 1, 2).

このようなプリント配線板は、ICチップ等をフリップチップ実装方式で両面実装が可能なものである。そして、導体回路と層間絶縁層(絶縁性ベース層)との密着性が高く、それにより、高密度実装に伴い微細化する導体回路がICチップ等を搭載実装されても絶縁性ベース層から剥離しないことが要求される。   Such a printed wiring board can be mounted on both sides of an IC chip or the like by a flip chip mounting method. In addition, the adhesiveness between the conductor circuit and the interlayer insulating layer (insulating base layer) is high. As a result, the conductor circuit that is miniaturized with high-density mounting is peeled off from the insulating base layer even if an IC chip or the like is mounted. It is required not to.

絶縁性ベース層と導体回路との密着性を高める方法としては、(1)接着剤を用いて導体回路と絶縁性ベース層とを接着する方法、(2)導体の絶縁性ベース層に対する接合表面を粗面化して、物理的なアンカ効果を利用する方法、および(3)導体の絶縁性ベース層に対する接合表面に有機皮膜を形成して、導体回路と絶縁性ベース層との化学的な結合力を得る方法、等がある。
特開2001−111189号公報 特開2002−359471号公報
As a method for improving the adhesion between the insulating base layer and the conductor circuit, (1) a method of bonding the conductor circuit and the insulating base layer using an adhesive, and (2) a bonding surface of the conductor to the insulating base layer. And (3) forming an organic film on the bonding surface of the conductor to the insulating base layer to chemically bond the conductor circuit and the insulating base layer. There are ways to get power, etc.
JP 2001-1111189 A JP 2002-359471 A

しかしながら、従来の方法はいずれも問題がある。   However, all the conventional methods have problems.

すなわち、(1)接着剤を用いて接着する方法は、比較的低温範囲での使用に限られ、高温での処理工程がある場合には使用することができない。   That is, (1) the method of bonding using an adhesive is limited to use in a relatively low temperature range, and cannot be used when there is a processing step at a high temperature.

また、(2)導体表面を粗面化して物理的なアンカ効果を利用する方法は、粗化量を大きくすることで密着力は向上するが、ファイン回路(微細回路)形成には不利で、粗面化には限界があるうえ、プリント配線板の製造工程を増やすことになる。   In addition, (2) the method of using the physical anchor effect by roughening the conductor surface improves the adhesion by increasing the amount of roughening, but is disadvantageous for fine circuit (fine circuit) formation, Roughening has a limit and increases the number of manufacturing steps of the printed wiring board.

さらに、(3)導体表面に有機皮膜を形成して化学的な結合力を得る方法は、絶縁性ベース層の材料によって結合効果が期待できないものがあるうえ、プリント配線板の製造工程を増やすことになる。   Furthermore, (3) the method of obtaining an organic bonding force by forming an organic film on the surface of a conductor cannot be expected to have a bonding effect depending on the material of the insulating base layer, and increases the production process of the printed wiring board. become.

この発明の課題は、上記従来のもののもつ問題点を排除して、絶縁層(絶縁性ベース層)と導体回路との密着を補うことで、絶縁性ベース層と導体回路との密着性を高めることのできるプリント配線板およびその製造方法を提供することにある。   An object of the present invention is to improve the adhesion between the insulating base layer and the conductor circuit by eliminating the problems of the conventional one and supplementing the adhesion between the insulating layer (insulating base layer) and the conductor circuit. An object of the present invention is to provide a printed wiring board that can be used and a method for manufacturing the same.

この発明は上記課題を解決するものであって、請求項1に係る発明は、片面に複数個の導電性のバンプが形成された第1の金属層と、第2の金属層とが、各バンプを除く領域に配置された絶縁層を挟んで重ね合わされ、前記各バンプの頂部と前記第2の金属層とが結合されたプリント配線板において、1個以上の補強用バンプを備えているプリント配線板である。   This invention solves the said subject, The invention which concerns on Claim 1 is the 1st metal layer in which the several conductive bump was formed in the single side | surface, and the 2nd metal layer, A printed wiring board in which one or more reinforcing bumps are provided on a printed wiring board that is overlapped with an insulating layer disposed in a region excluding the bumps, and the top of each bump and the second metal layer are combined. It is a wiring board.

請求項2に係る発明は、請求項1記載の発明において、前記補強用バンプは、前記第1、第2いずれか一方の金属層に形成される回路から電気的に独立したランドになっているプリント配線板である。   The invention according to claim 2 is the invention according to claim 1, wherein the reinforcing bump is a land electrically independent from a circuit formed on one of the first and second metal layers. It is a printed wiring board.

請求項3に係る発明は、第1の金属層の片面に複数個の導電性のバンプを形成する工程と、前記第1の金属層のバンプ形成面に各バンプを除いて絶縁層を形成する工程と、第2の金属層を前記絶縁層を挟んで前記第1の金属層に重ね合わせ、前記各バンプの頂部と当該第2の金属層とを結合させる工程と、前記第1、第2の金属層に回路を形成する際、少なくとも1個の補強用バンプを形成する工程と、を有するプリント配線板の製造方法である。   The invention according to claim 3 is the step of forming a plurality of conductive bumps on one side of the first metal layer, and forming an insulating layer on the bump forming surface of the first metal layer except for each bump. A step of superimposing the second metal layer on the first metal layer with the insulating layer sandwiched therebetween, and bonding the top of each bump to the second metal layer; and the first and second layers Forming a circuit on the metal layer, forming at least one reinforcing bump.

請求項4に係る発明は、第1の金属層の片面に複数個の導電性のバンプを形成する工程と、前記第1の金属層のバンプ形成面の前記各バンプを除く領域に、前記各バンプの高さに相当する厚さの絶縁層を形成する工程と、第2の金属層を前記絶縁層を挟んで前記第1の金属層に重ね合わせ、前記各バンプの頂部と当該第2の金属層とを結合させる工程と、前記第1、第2の金属層に回路を形成する際、少なくとも1個の前記バンプを、前記第1、第2いずれか一方の金属層に形成される回路から電気的に独立したランドとして形成する工程と、を有するプリント配線板の製造方法である。   According to a fourth aspect of the present invention, in the step of forming a plurality of conductive bumps on one side of the first metal layer, and in the region excluding the bumps on the bump forming surface of the first metal layer, A step of forming an insulating layer having a thickness corresponding to the height of the bump, and a second metal layer superimposed on the first metal layer with the insulating layer interposed therebetween, and the top of each bump and the second metal layer A circuit in which at least one of the bumps is formed on one of the first and second metal layers when the circuit is formed on the first and second metal layers; Forming a land that is electrically independent of the printed wiring board.

この発明は以上のように、片面に複数個の導電性のバンプが形成された第1の金属層と、第2の金属層とが、各バンプを除く領域に配置された絶縁層を挟んで重ね合わされ、前記各バンプの頂部と前記第2の金属層とが結合されたプリント配線板において、1個以上の補強用バンプを備えた構成としたので、このような補強用バンプを、層間導通用のバンプとしてではなく、絶縁性ベース層と導体回路との密着を補うためのバンプとして利用することにより、絶縁性ベース層と導体回路との密着を補うことができ、その結果、絶縁性ベース層と導体回路との密着性を高めることができる効果がある。   As described above, according to the present invention, a first metal layer having a plurality of conductive bumps formed on one side and a second metal layer sandwich an insulating layer disposed in a region excluding each bump. Since the printed wiring board in which the tops of the bumps and the second metal layer are combined with each other has one or more reinforcing bumps, such reinforcing bumps are connected to the interlayer conductor. By using it as a bump to supplement the adhesion between the insulating base layer and the conductor circuit, not as a common bump, the adhesion between the insulating base layer and the conductor circuit can be compensated. There exists an effect which can improve the adhesiveness of a layer and a conductor circuit.

しかも、このような絶縁性ベース層と導体回路との密着を補うためのバンプは、層間導通用のバンプの形成工程で同時に形成することができるから、プリント配線板の製造工程を増やすことがないうえ、高温での処理工程がある場合にも、ファイン回路(微細回路)を形成する場合にも、絶縁層が化学的結合力に乏しい材料である場合にも、いずれも問題なく利用可能である。   In addition, since the bumps for supplementing the close contact between the insulating base layer and the conductor circuit can be formed at the same time in the bump forming process for interlayer conduction, the manufacturing process of the printed wiring board is not increased. Moreover, it can be used without any problems even when there is a processing step at high temperature, when forming a fine circuit (fine circuit), or when the insulating layer is a material with poor chemical bonding force. .

この発明によるプリント配線板およびその製造方法の一実施形態を、図1を参照して説明する。   An embodiment of a printed wiring board and a method for manufacturing the same according to the present invention will be described with reference to FIG.

まず、図1(a)に示すように、銅箔製の板状の第1の金属層(導体層)11と、ニッケル等によるエッチングバリア層12と、銅製のバンプ形成層13との3層材10を出発材として準備する。   First, as shown in FIG. 1A, three layers of a copper foil plate-shaped first metal layer (conductor layer) 11, an etching barrier layer 12 made of nickel or the like, and a copper bump forming layer 13 are formed. The material 10 is prepared as a starting material.

図1(b)に示すように、3層材10のバンプ形成層13をエッチングし、層間導通を行うべき各位置に層間導通用のバンプ14を形成すると共に、導体の密着補強位置に密着補強用のバンプ15を形成する。バンプ14とバンプ15は、同一のエッチング工程によって形成することができる。なお、バンプ14とバンプ15は、第1の導体層11上に、銅めっきによって形成することもできる。   As shown in FIG. 1B, the bump forming layer 13 of the three-layer material 10 is etched to form interlayer conduction bumps 14 at each position where interlayer conduction should be performed, and adhesion reinforcement is provided at the adhesion reinforcement position of the conductor. A bump 15 is formed. The bump 14 and the bump 15 can be formed by the same etching process. The bumps 14 and the bumps 15 can also be formed on the first conductor layer 11 by copper plating.

つぎに、図1(c)に示すように、第1の導体層11のバンプ形成面(詳細にはエッチングバリア層12の表面)における各バンプ14、15を除く領域に、絶縁層(絶縁性ベース層)16を形成する。   Next, as shown in FIG. 1C, an insulating layer (insulating property) is formed in a region excluding the bumps 14 and 15 on the bump forming surface of the first conductor layer 11 (specifically, the surface of the etching barrier layer 12). Base layer) 16 is formed.

絶縁性ベース層16は、熱可塑性ポリイミドシートの貼り付け、熱可塑性ポリイミド前駆体の塗布等によって形成することができる。絶縁性ベース層16は、バンプ14、15の高さと同等の厚さを有し、図示されているように、バンプ14、15の頂面14A、15Aを覆うことなく、バンプ14、15の頂面14A、15Aが露出するように形成される。   The insulating base layer 16 can be formed by attaching a thermoplastic polyimide sheet, applying a thermoplastic polyimide precursor, or the like. The insulating base layer 16 has a thickness equivalent to the height of the bumps 14 and 15, and as shown in the drawing, the top surfaces of the bumps 14 and 15 are not covered without covering the top surfaces 14A and 15A of the bumps 14 and 15. The surfaces 14A and 15A are formed so as to be exposed.

つぎに、図1(d)に示すように、絶縁性ベース層16上に銅箔製の板状の第2の金属層(導体層)17を配置し、加熱加圧によるプレスキュアによって第2の導体層17を絶縁性ベース層16に貼り合わせる。すなわち、第2の導体層17とバンプ14、15の頂面14A、15Aとを結合させる。この結合方法は、プレス以外にめっきなどでも可能である。   Next, as shown in FIG. 1 (d), a plate-like second metal layer (conductor layer) 17 made of copper foil is disposed on the insulating base layer 16, and the second is cured by press curing by heating and pressing. The conductor layer 17 is bonded to the insulating base layer 16. That is, the second conductor layer 17 and the top surfaces 14A and 15A of the bumps 14 and 15 are combined. This bonding method can be performed by plating as well as pressing.

これにより、バンプ配置部以外の部分に設けられた絶縁性ベース層16とバンプ14、15を挟んで第2の導体層17が形成される。   As a result, the second conductor layer 17 is formed with the insulating base layer 16 and the bumps 14 and 15 provided at portions other than the bump placement portion sandwiched therebetween.

つぎに、図1(e)に示すように、第1の導体層11およびエッチングバリア層12をエッチングし、バンプ14、15と接続された導体回路18と、導体回路18より電気的に独立しバンプ15と接続された独立導体部19を形成する。また、第2の導体層17をエッチングし、バンプ14、15と接続された導体回路20と、導体回路20より電気的に独立しバンプ15と接続された独立導体部21を形成する。これにより、1枚のプリント配線板(両面配線板)30が完成する。   Next, as shown in FIG. 1 (e), the first conductor layer 11 and the etching barrier layer 12 are etched so that the conductor circuit 18 connected to the bumps 14 and 15 is electrically independent of the conductor circuit 18. An independent conductor portion 19 connected to the bump 15 is formed. In addition, the second conductor layer 17 is etched to form a conductor circuit 20 connected to the bumps 14 and 15 and an independent conductor portion 21 that is electrically independent of the conductor circuit 20 and connected to the bump 15. Thereby, one printed wiring board (double-sided wiring board) 30 is completed.

このプリント配線板30では、バンプ14によって上面側の導体回路18と下面側の導体回路20とが導通接続され、バンプ14が層間導通導体をなす。バンプ14は、両端で導体回路18、20と結合しているため、優れた導通性を示す。   In the printed wiring board 30, the conductor circuit 18 on the upper surface side and the conductor circuit 20 on the lower surface side are conductively connected by the bump 14, and the bump 14 forms an interlayer conductive conductor. Since the bumps 14 are coupled to the conductor circuits 18 and 20 at both ends, the bumps 14 exhibit excellent conductivity.

一方、バンプ15が、絶縁性ベース層16の上面側に存在する独立導体部19と、絶縁性ベース層16の下面側に存在する導体回路20とに各々結合するか、または、絶縁性ベース層16の下面側に存在する独立導体部21と、絶縁性ベース層16の上面側に存在する導体回路18とに各々結合する。バンプ15は、導体回路18、20を短絡障害させない範囲で、自由なところに設置可能である。   On the other hand, the bumps 15 are respectively coupled to the independent conductor portion 19 existing on the upper surface side of the insulating base layer 16 and the conductor circuit 20 existing on the lower surface side of the insulating base layer 16, or the insulating base layer 16 The independent conductor portion 21 existing on the lower surface side of the insulating base layer 16 and the conductor circuit 18 existing on the upper surface side of the insulating base layer 16 are coupled to each other. The bump 15 can be installed in any place as long as the conductor circuits 18 and 20 are not short-circuited.

これにより、バンプ15が、導体と絶縁性ベース層との密着補強用のバンプをなし、上面側の導体回路18は、下面側の独立導体部21と密着補強用のバンプ15とによって裏打ちされたような形態で、また、下面側の導体回路20は、上面側の独立導体部19と密着補強用のバンプ15とによって裏打ちされたような形態で、各々、絶縁性ベース層16に対する接合度を増す。   Thereby, the bump 15 forms a bump for reinforcing the adhesion between the conductor and the insulating base layer, and the conductor circuit 18 on the upper surface side is lined with the independent conductor portion 21 on the lower surface side and the bump 15 for adhesion reinforcement. In addition, the conductor circuit 20 on the lower surface side is configured to be lined with the independent conductor portion 19 on the upper surface side and the bumps 15 for adhesion reinforcement, and each has a degree of bonding to the insulating base layer 16. Increase.

これにより、絶縁性ベース層16に対する導体回路18、20の密着性が高められる。しかも、製造工程を増やすことなく、また、高温雰囲気や回路微細化に制限されることなく、また、化学的結合性が乏しい絶縁性ベース層16によるプリント配線板30にも適用可能で、有効である。   Thereby, the adhesiveness of the conductor circuits 18 and 20 with respect to the insulating base layer 16 is improved. In addition, the present invention can be applied to the printed wiring board 30 with the insulating base layer 16 having a poor chemical bondability without being increased in the manufacturing process, limited to high temperature atmosphere and circuit miniaturization, and effective. is there.

図2は、プリント配線板30の導体回路18上に、はんだボール41によってICチップ42がフリップチップ実装されたプリント回路板40を示す。図3は、図2のプリント回路板の要部を示す概略的平面図である。   FIG. 2 shows a printed circuit board 40 in which an IC chip 42 is flip-chip mounted by solder balls 41 on the conductor circuit 18 of the printed wiring board 30. FIG. 3 is a schematic plan view showing a main part of the printed circuit board of FIG.

この発明によるプリント配線板およびその製造方法の一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the printed wiring board by this invention, and its manufacturing method. 図1のプリント配線板にICチップをフリップチップ実装したプリント回路板を示す断面図である。FIG. 2 is a cross-sectional view showing a printed circuit board in which an IC chip is flip-chip mounted on the printed wiring board of FIG. 1. 図2のプリント回路板の要部を示す概略的平面図である。FIG. 3 is a schematic plan view showing a main part of the printed circuit board of FIG. 2.

符号の説明Explanation of symbols

10 3層材
11 第1の金属層(導体層)
12 エッチングバリア層
13 バンプ形成層
14、15 バンプ
16 絶縁層(絶縁性ベース層)
17 第2の金属層(導体層)
18 導体回路
19 独立導体部
20 導体回路
21 独立導体部
30 プリント配線板
40 プリント回路板
41 はんだボール
42 ICチップ
10 Three-layer material 11 First metal layer (conductor layer)
12 Etching barrier layer 13 Bump forming layer 14, 15 Bump 16 Insulating layer (insulating base layer)
17 Second metal layer (conductor layer)
18 Conductor Circuit 19 Independent Conductor 20 Conductor Circuit 21 Independent Conductor 30 Printed Wiring Board 40 Printed Circuit Board 41 Solder Ball 42 IC Chip

Claims (6)

片面に複数個の導電性のバンプが形成された第1の金属層と、第2の金属層とが、各バンプを除く領域に配置された絶縁層を挟んで重ね合わされ、前記各バンプの頂部と前記第2の金属層とが結合されたプリント配線板において、
前記第1の金属層が、1個以上の補強用バンプを備えており、該補強用バンプが、前記絶縁層と前記第1または第2の金属層との間の密着性を高めていることを特徴とするプリント配線板。
A first metal layer having a plurality of conductive bumps formed on one side and a second metal layer are overlapped with an insulating layer disposed in a region excluding the bumps, and the top of each bump. And a printed wiring board in which the second metal layer is bonded,
The first metal layer includes one or more reinforcing bumps, and the reinforcing bumps enhance adhesion between the insulating layer and the first or second metal layer . Printed wiring board characterized by
前記補強用バンプは、前記第1、第2いずれか一方の金属層に形成される回路から電気的に独立したランドになっていることを特徴とする請求項1記載のプリント配線板。   2. The printed wiring board according to claim 1, wherein the reinforcing bump is a land electrically independent from a circuit formed on one of the first and second metal layers. 第1の金属層の片面に複数個の導電性のバンプを形成する工程と、
前記第1の金属層のバンプ形成面に各バンプの頂面が露出するように各バンプを除いて絶縁層を形成する工程と、
第2の金属層を前記絶縁層を挟んで前記第1の金属層に重ね合わせ、前記各バンプの頂部と当該第2の金属層とを結合させる工程と、
前記第1、第2の金属層に回路を形成する際、前記第1または第2の金属層と前記絶縁層との間の密着性を高めることができる少なくとも1個の補強用バンプを形成する工程と、
を有することを特徴とするプリント配線板の製造方法。
Forming a plurality of conductive bumps on one side of the first metal layer;
Forming an insulating layer excluding each bump so that the top surface of each bump is exposed on the bump forming surface of the first metal layer;
A step of superimposing a second metal layer on the first metal layer with the insulating layer in between, and bonding a top of each bump and the second metal layer;
When forming a circuit on the first and second metal layers, at least one reinforcing bump capable of enhancing adhesion between the first or second metal layer and the insulating layer is formed. Process,
A method for producing a printed wiring board, comprising:
第1の金属層の片面に複数個の導電性のバンプを形成する工程と、
前記第1の金属層のバンプ形成面の前記各バンプの頂面が露出するように各バンプを除く領域に、前記各バンプの高さに相当する厚さの絶縁層を形成する工程と、
第2の金属層を前記絶縁層を挟んで前記第1の金属層に重ね合わせ、前記各バンプの頂部と当該第2の金属層とを結合させる工程と、
前記第1、第2の金属層に回路を形成する際、少なくとも1個の前記バンプを、前記第1または第2の金属層と前記絶縁層との間の密着性を高めることができるランドとして形成する工程であって、前記補強用バンプは、前記第1、第2いずれか一方の金属層に形成される回路から電気的に独立するように形成する工程と、
を有することを特徴とするプリント配線板の製造方法。
Forming a plurality of conductive bumps on one side of the first metal layer;
Forming an insulating layer having a thickness corresponding to the height of each bump in a region excluding each bump so that a top surface of each bump of the bump forming surface of the first metal layer is exposed ;
A step of superimposing a second metal layer on the first metal layer with the insulating layer in between, and bonding a top of each bump and the second metal layer;
When a circuit is formed on the first and second metal layers, at least one of the bumps is used as a land that can enhance adhesion between the first or second metal layer and the insulating layer. A step of forming the reinforcing bump, the step of forming the reinforcing bump so as to be electrically independent from a circuit formed on one of the first and second metal layers;
A method for producing a printed wiring board, comprising:
前記第1、第2の少なくともいずれか一方の金属層が、導体回路および該導体回路とは電気的に独立した独立導体部を形成しており、The metal layer of at least one of the first and second forms a conductor circuit and an independent conductor portion electrically independent of the conductor circuit;
該独立導体部と前記補強用バンプとが、該独立導体部とは前記絶縁層を挟んで反対側の金属層を裏打ちしている請求項1または請求項2に記載のプリント配線板。  The printed wiring board according to claim 1, wherein the independent conductor portion and the reinforcing bump line a metal layer opposite to the independent conductor portion with the insulating layer interposed therebetween.
請求項1、2または5に記載のプリント配線板において、前記第1および/または第2の金属層に導体回路が形成され、該導体回路上にフリップチップ実装方式で実装が可能なフリップチップ実装用プリント配線板。6. The printed wiring board according to claim 1, 2, or 5, wherein a conductor circuit is formed on the first and / or second metal layer and can be mounted on the conductor circuit by a flip chip mounting method. Printed wiring board.
JP2004028083A 2004-02-04 2004-02-04 Printed wiring board and manufacturing method thereof Expired - Fee Related JP4621432B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10190231A (en) * 1996-12-26 1998-07-21 Yamaichi Electron Co Ltd Multilayer wiring board
JPH1187932A (en) * 1997-09-02 1999-03-30 Toshiba Corp Manufacture of multilayered wiring board
JP2001326459A (en) * 2000-05-16 2001-11-22 North:Kk Wiring circuit board and its manufacturing method
JP2002368369A (en) * 2001-06-06 2002-12-20 Yamaichi Electronics Co Ltd Flexible printed wiring board and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10190231A (en) * 1996-12-26 1998-07-21 Yamaichi Electron Co Ltd Multilayer wiring board
JPH1187932A (en) * 1997-09-02 1999-03-30 Toshiba Corp Manufacture of multilayered wiring board
JP2001326459A (en) * 2000-05-16 2001-11-22 North:Kk Wiring circuit board and its manufacturing method
JP2002368369A (en) * 2001-06-06 2002-12-20 Yamaichi Electronics Co Ltd Flexible printed wiring board and method of manufacturing the same

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