JP4620970B2 - Quality control method and quality control system for semiconductor products - Google Patents

Description

  In the present invention, when a semiconductor product such as a multi-chip module product is manufactured by assembling a plurality of semiconductor components of different types manufactured from each substrate through respective processing steps in an assembly process, a semiconductor including a manufacturing factory is also included. The present invention relates to a quality control method and a quality control system for a semiconductor product, such as estimating a defect generation source of the product.

  In general, integrated circuits have been designed to be manufactured from a single substrate (silicon wafer). However, in order to realize products such as low power consumption, high speed, space saving, and large capacity, a great development period and a great development cost are required. A product that solves this problem is a multi-chip module product. Multichip module products are also called system-in-package.

  FIG. 2 shows an outline of a manufacturing method of a multichip module product. Multi-chip module products are generally used in a manufacturing process in which a circuit pattern is formed on a substrate (silicon wafer) to manufacture a plurality of the same components from one substrate, and an assembly process in which a plurality of components formed in the processing steps are assembled. I know. In the assembly process, only parts that are determined to be non-defective products in each processing process test are transported and assembled. At the end of the assembly process, the finished product is tested and only good products are delivered to the customer.

  Originally, it is ideal that defective parts resulting from the manufacturing process of the machining process are shaken off during the machining process test and not transferred to the assembly process. However, in recent years, with the complication of the manufacturing process of the machining process, defective parts are not always caught in the machining process test, and defective parts are often sent to the assembly process.

Conventionally, in an integrated circuit manufactured from a single substrate, when a defect is not caught in a processing process test, the source of the defective product is determined using the test result of the assembly process. Yes. Specifically, there are the following methods.
(1) The defective product is disassembled, and the cause of the failure is physically analyzed using a tool such as a scanning electron microscope (SEM) or a focused ion beam processing observation device (FIB).
(2) As described in Patent Document 1, a correlation analysis is performed between the inspection data performed during the manufacturing process and the test result of the assembly process to identify inspection data having a strong correlation.
(3) As described in Patent Document 2, the assembly process test results are mapped in a wafer shape, and the defect distribution is confirmed. At that time, as in Patent Document 3 and Patent Document 4, the identification data (die ID) is used to manage in advance where each individual chip is acquired in the wafer.

Japanese Patent Laid-Open No. 2003-18653

JP 2001-273793 A JP 11-45839 A US Pat. No. 5,302,491

Consider the problem when the above three analysis methods are applied to a multi-chip module product.
Since the method (1) is a physical analysis, it is an effective method, but there is a problem that it takes time and cost.
In the method (2), in recent years, there are many cases where the processing process and the assembly process are different companies or different bases even in the same company, and there is a problem in exchange of information. A company or factory in an assembly process may not be able to obtain various inspection data performed during the manufacturing process. If inspection data of the processing process is not available, it is difficult for a company or factory in the assembly process to determine which part or which part is the process that produced the defective product.
On the other hand, the method (3) is intended for a conventional integrated circuit manufactured from one substrate, and various devices are required when targeting a multi-chip module product.

  The object of the present invention is to devise various devices in the above (3), and use only the test results of the assembly process and the identification data given to the parts to produce which part or which part is the source of the defective product. Provided are a quality control method and a quality control system for a semiconductor product for determining whether it is a process.

  Another object of the present invention is that the failure cannot be detected even in the test result of the assembly process, and even if the product is shipped to the customer and a defective product is found after the shipment, which is the source of the failure? It is an object of the present invention to provide a quality control method and quality control system for a semiconductor product that can determine whether it is a part.

In order to achieve the above object, the present invention provides a semiconductor product manufactured by assembling a plurality of different types of semiconductor components cut out from a plurality of wafers manufactured through different processing steps in an assembly process. A method for quality control of a semiconductor product, comprising: an identification information acquisition step of acquiring positional information on the wafer assigned to each semiconductor component of a plurality of semiconductor components assembled in the assembly process in association with the semiconductor product; and quality obtaining step of obtaining the quality results also include return whether the results from the customer's semiconductor products manufactured over a number of, the quality results of the semiconductor products over the predetermined number obtained in該良not obtaining step The semiconductor component is mapped onto each wafer based on the positional information on each wafer of the semiconductor component obtained in association with the semiconductor product in the identification information obtaining step. Mapping step for creating a two-dimensional distribution of pass / fail results on the wafer corresponding to each semiconductor component, and two-dimensional on the wafer corresponding to each semiconductor component created in the mapping step And an analysis step for estimating a wafer which is a defect generation source of the semiconductor product by comparatively analyzing the distribution of the quality results.

The present invention also relates to a quality control method of a semiconductor product when a semiconductor product is manufactured by assembling a plurality of semiconductor components of different types cut out from a plurality of wafers manufactured through different processing steps in an assembly process. The position information on the wafer given to each semiconductor component of the plurality of semiconductor components assembled in the assembly process and the information of the manufacturing factory that manufactured the wafer from which the semiconductor component was cut are associated with the semiconductor product. an identification information acquiring step of acquiring Te, and quality obtaining step of obtaining the return presence results acceptability results also containing from customers of the semiconductor products manufactured over a predetermined number, the predetermined obtained in該良not obtaining step Manufacture the wafer of the semiconductor component obtained by associating the quality result of the semiconductor product over the number with the semiconductor product in the identification information obtaining step. 2D on the wafer corresponding to each semiconductor component including each manufacturing factory by mapping on each wafer including each manufacturing factory based on the information on the manufacturing factory and the position information on each wafer. A mapping step for creating a distribution of pass / fail results and a distribution analysis of the two-dimensional pass / fail results on the wafer corresponding to each semiconductor component created by the mapping step and for each manufacturing part. And an analysis step for estimating a wafer that is a defect generation source of a semiconductor product.

  Further, the present invention is characterized in that, in the quality acquisition step, the quality result of the semiconductor product is acquired based on the result of testing the electrical characteristics of the semiconductor product.

  Further, the present invention is characterized in that, in the analysis step, when the distribution of the two-dimensional quality result for each semiconductor component is comparatively analyzed, the two-dimensional quality result distribution is quantified.

  Further, the present invention is characterized in that the analysis step includes a display step of displaying a two-dimensional distribution of pass / fail results for each of the semiconductor components created in the mapping step.

  Further, the present invention includes a display step of displaying, in the analysis step, a distribution of the two-dimensional good / bad result created in the mapping step for at least a semiconductor component estimated as a defect generation source of the semiconductor product. And

  According to the present invention, like a multi-chip module product, a semiconductor product divided into a processing step of forming a plurality of semiconductor components on a substrate and an assembly step of assembling separate semiconductor components manufactured through separate processing steps In the manufacturing process, it is possible to quickly estimate the source of the defective product found after the assembly process test or delivery to the customer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a process flow diagram showing a first embodiment of a data analysis program according to the present invention. In step 11, first, the die ID having the coordinate information in the substrate and the quality result of the product in the processing step are read. The die ID is information that can identify the item name, lot ID at the time of manufacturing process, wafer ID for each part, and can grasp the position coordinates formed in the wafer, and there is no gap in the circuit pattern of each part. It is imprinted on. Next, in steps 12a to 12c, the position coordinate information is recognized from the die ID for each item read in step 11, and the quality result of the product is mapped with the position coordinate information. In this embodiment, a case where three types of chips A, B, and C are mounted as components on a multichip module product is shown. In steps 13a to 13c, the distribution of each part item is quantified on the basis of the result of mapping the quality result of the product (for example, after the assembly process) with the position coordinate information for each part item obtained from each of steps 12a to 12c. In step 14, the result of quantification for each item of each part is compared to determine the item of the defective part mounted on the multichip module product and output as the defect source 15. In this way, if the position coordinates on the wafer for each item of each part mounted on the multichip module product can be acquired, the pass / fail result of the product is mapped to the position coordinates on the wafer for each item of each part. It is possible to specify and output the defective part item as the defect source 15 only by quantifying each item of the part and comparing the quantified result for each part item.

  FIG. 2 is a schematic view showing a first embodiment of the manufacturing process of the multichip module product. In this embodiment, a case where three types of chips A, B, and C are mounted as components on a multichip module product is shown. The parts A, B, and C are formed through a number of general integrated circuit manufacturing processes (processing processes) in which a lithography process and a film forming process are repeatedly performed using a wafer. The component A is subjected to an electrical test 22a in a wafer state through a number of manufacturing processes (processing steps) 21a. In the test 22a, it is determined whether each die formed on the wafer is a non-defective product or a defective product. Identification data (die ID) is given to the good product die by the die ID marking 23a and is stamped. Usually, the wafer is cut into parts using a dicing apparatus immediately before being transferred from the manufacturing process (processing process) to the assembly process. Similarly to the part A, the parts B and C are subjected to a number of manufacturing processes (processing steps) 21b and 21c, and electrical tests 22b and 22c are performed in a wafer state. In tests 22b and 22c, it is determined whether each die formed on the wafer is a non-defective product or a defective product. Identification data (die ID) is stamped and cut on the good product die by die ID markings 23b and 23c. It is conveyed to. The parts A, B, and C on which the identification data is engraved are put into an assembly process 31 together with other parts such as a wiring material and a molding material, and a multichip module product is produced. In the assembly process 31, the die IDs engraved on the parts A, B, and C are read by the part identification data reading device (identification information acquiring unit) 92 shown in FIG. The identification data) and the product are associated with each other and stored in the identification data management unit 93. Next, the finished product is subjected to a test 32 of electrical characteristics as a product by a test device (good / bad acquisition means) 95, and the test result is registered in the test result management unit 94. At 33, a product ID (identification data) is given and shipped.

  FIG. 3 is a diagram showing a first example of performance data in which the die ID read in step 11 of FIG. 1 is associated with the product ID and the pass / fail result in the test 32. For example, in this embodiment, a product with the product ID P031202551 has a die ID of the part A of A1025030302, a die ID of the part B of B10220905205, a die ID of the part C of C10240090205, and the pass / fail result in the test 32 is good. It can also be seen that the quality is of A rank. In this example, for the die ID, the first digit from the left is the item name, the next four digits are the lot ID during the manufacturing process, the next two digits are the wafer ID, the next two digits are the X coordinates in the wafer, and the last two The digit is defined as the Y coordinate in the wafer. For example, for the part A with the product ID P031202551, the item name is A, the lot ID is 1025, the wafer ID is 03, and the coordinates formed in the wafer are X = 03, Y = 02. Here, the product ID is the product ID marking 33 of FIG. 2, the die ID of the part A is the die ID marking 23a of FIG. 2, the die ID of the part B is the die ID marking 23b of FIG. 2, and the die ID of the part C is FIG. The die ID marking 23c and pass / fail judgment results are the results given in the test 32 of FIG.

  Here, what is important is that, before the assembly process of the product, as shown in FIG. 4, the position coordinates on the wafer for each item of the components which are mounted and constitute the product are read out from the identification data of the component shown in FIG. It is to be read by the device 92 and stored in the identification data management unit 93. That is, in the present invention, at the time of the product assembly process, a wafer defined as shown in FIG. 4 is provided for each item of the components that are mounted on the company or factory in the manufacturing process that manufactures the components. The position coordinate system above can be acquired. In short, it is necessary to be able to provide a position coordinate system on a wafer for each item of a part from a manufacturing company or factory that manufactures the part.

  FIG. 4 shows a position coordinate system for each item of a part that can be provided from a company or factory in the manufacturing process for manufacturing the part in order to perform mapping of the quality results of the products assembled in steps 12a to 12c of FIG. It is a figure which shows one Example defined (provided). The position coordinate system is defined for each item of the part based on the specification of the lithography process in the manufacturing process. For example, 51a is the coordinate system of the part A. A round outer frame represents a wafer (substrate), and a square with two integers separated by commas inside represents a die of each component. In this embodiment, a coordinate system is defined in which an origin is provided at the lower left of a wafer (substrate), an X axis is provided horizontally, and a Y axis is provided vertically. 51b is the definition of the component B, and 51c is the definition of the coordinate system of the component C. In the present invention, it is a premise that a position coordinate system defined in this way is provided from a company or factory of a manufacturing process (processing process) for manufacturing a part.

  FIG. 5 shows a test of electrical characteristics obtained from the test result unit 94 in the data analysis unit (analysis means) 96 based on the two-dimensional position coordinate system of FIG. It is a figure which shows one Example of the result of mapping the quality result of the product by 32. This example is a result of mapping 350 products that have been subjected to the electrical property test 32 over a period of time. In this embodiment, 350 products include 300 non-defective products and 50 defective products. In step 12, the die ID of the component A has the die ID of the component A, the die ID of the component B, the die ID of the component C, and the information on the pass / fail result in the electrical characteristic test 32 of the product as shown in FIG. A map 52a is created from the combination of the position coordinate information and the pass / fail result in the test 32 of the electrical characteristics of the product. Further, a map 52b is created from the combination of the position coordinate information of the die ID of the part B and the quality result in the test 32 of the electrical characteristics of the product. Further, a map 52c is created from the combination of the position coordinate information of the die ID of the part C and the quality result in the test 32 of the electrical characteristics of the product. Here, the fraction indicated in each die is the result of allocating the number of products that have passed the test 32 of the assembly process for each chip based on the position coordinate information that the denominator has in the die ID. 32 is the number of products determined to be non-defective. For example, in the position coordinates X = 3 and Y = 1 on the map 52a, it means that the number of products that have passed the test 32 is six, and the number of products that are determined to be non-defective products is five. Since the relationship between the number of products that have passed the test 32 and the number of non-defective products is mapped, the sum of the denominator of all coordinates of the map 52a is 350, the sum of the numerators of all coordinates of the map 52a is 300, and all of the maps 52b The sum of the denominators of the coordinates is 350, the sum of the numerators of all the coordinates in the map 52b is 300, the sum of the denominators of all the coordinates of the map 52c is 350, and the sum of the numerators of all the coordinates of the map 52c is 300.

  Thus, in the data analysis unit 96, based on the position coordinates for each of the items A, B, and C of the parts constituting the product, the quality result of the assembly process (the number of products whose denominator passed the test 32, the numerator is the non-defective product) It is possible to map the number of products determined to be two-dimensional. By mapping in two dimensions in this way, it becomes possible to grasp by quantifying the probability for each item of a part that makes a product defective or non-defective as a two-dimensional distribution.

  In the data analysis unit 96, in steps 13a to 13c, the distribution is quantified for each map, that is, for each item of the parts, based on the mapping result of FIG. There are various methods for quantification. For example, there is a method for obtaining the standard deviation of each coordinate value for each map in FIG. 5 and evaluating how much the value varies for each coordinate. The smaller the standard deviation value, the smaller the difference in the value for each coordinate, which means that a part or item of a part that forms a defective product as a product with a random probability (small variation) by a normal combination is incorporated. It will be. On the other hand, the larger the standard deviation value, the greater the difference in the values for each coordinate (the larger the two-dimensional variation), and the greater the correlation between the occurrence of defective products as products (the higher the probability that they are defective products) ) Means that a part or item of parts is incorporated. When the standard deviation of each map is calculated in this embodiment, it is about 0.081 for the map 52a, 0.147 for the map 52b, and about 0.035 for the map 52c. The two-dimensional standard deviation (variation) that causes the component B to be a defective product is the largest, and then approaches the random variation due to the normal combination of the components A and C.

  In addition, when quantifying the distribution, the minimum value can be considered when the denominator is the number of products that have passed the test 32 and the numerator is the number of products that are determined to be non-defective. Of course, when the numerator is the number of products determined to be defective, the maximum value can be considered. The minimum values are obtained as 4/5 = 0.8 for part A, 6/13 = 0.46 for part B, and 13/16 = 0.87 for part C.

  As described above, in the data analysis unit 96, it is possible to identify the item of the part that is the source of the defect that makes the product defective by comparing the results quantified in steps 13a to 13c in step 14. It becomes possible. For example, as one method, by comparing the standard deviation among the items of the parts that make up the product, the item on the map 52b that shows the largest standard deviation (0.147) does not recognize the product. It is possible to determine that the defect source is a non-defective product and output the determination result 15. Further, by comparing the minimum value among the items of the parts constituting the product, the item of the map 52b showing the smallest value (0.46) is a defect source that makes the product defective. It is possible to determine that there is and output the determination result 15.

  In this embodiment, the program to which the present invention is applied indicates that the part B is a problem for the final product, in the manufacturing process company or factory that manufactured the part B, and the assembly process company or factory. Is possible. As described above, the most beneficial effect of the present invention is that a product or a factory in the manufacturing process of manufacturing a part provides a position coordinate system on the wafer for each item of the part as a finished product. By testing the electrical characteristics of the product, the company or factory that produced the defective part can be automatically found.

  FIG. 6 is a block diagram showing an embodiment of the hardware configuration of the product quality management system according to the present invention. In the assembly process manufacturing line 91, a part identification data reader (identification information acquisition means) 92, an identification data management unit 93, a test result management unit 94, a test apparatus (good / bad acquisition means) 95, a data analysis unit (analysis means) 96), which are connected via the local area network 97.

  The component identification data reading device 92 is provided in a manufacturing process company or factory that manufactures a component, has an image imaging sensor, and uses a die ID (including position coordinates) captured by the image imaging sensor as a character such as OCR technology. It is a device that automatically recognizes using recognition technology, and transmits the recognized die ID to the identification data management unit 93 via the local area network 97. In short, the part identification data reader 92 is not necessarily connected to the identification data management unit 93 via the local area network 97, and the position coordinate information is obtained for each part item from the company or factory in the manufacturing process where the part is manufactured. It may be provided and stored in the identification data management unit 93.

  The identification data management unit 93 is a general computer including a control / arithmetic unit, a storage device, an input device, and an output device, and receives die ID information sent from the component identification data reader 92. It has a program that is managed in a database in association with each product. Therefore, it is desirable that the identification data management unit 93 is provided on the side where the parts are assembled to complete the product and the electrical characteristics of the product are tested.

  The identification data management unit 93 has a program for issuing a product ID obtained by assembling parts, and manages the die IDs of the parts A, B, and C in association with the product IDs in a database. The test result management unit 94 is a general computer including a control / arithmetic unit, a storage device, an input device, and an output device. The test result management unit 94 is an electrical unit for products transmitted from the test device 95 via the local area network 97. The pass / fail result in the characteristic test 32 is received and managed in a database for each product. The test device (good / bad acquisition means) 95 is a device for testing the electrical characteristics of a multichip module product completed by assembling components A, B, C, components such as connection materials and mold materials. The data analysis unit 96 is a general computer provided with a control / arithmetic unit, a storage device, an input device, and an output device, acquires data from the database of the identification data management unit 93 and the test result management unit 94, and FIG. 1 is generated, the program shown in FIG. 1 is executed, and the defect source 15 is output. In the example of FIG. 6, the identification data management unit 93, the test result management unit 94, and the data analysis unit 96 are shown separately as separate hardware. However, if the computer is a high-performance computer, it can be realized by a single hardware. Also good.

  FIG. 7 is a diagram showing an example of a screen analyzed by the data analysis unit 96 of FIG. 6 and displayed on the output device, which is a result of executing the program shown in FIG. A window 60 is displayed on the output device, and the mapping result shown in FIG. 5 is displayed as 53a, 53b, and 53c for each item of the component by color-coding the value for each component coordinate. The color coding definition of this example is a striped stripe pattern 61 with a value less than 0.6 and a vertical stripe pattern 62 with a value of 0.6 to less than 0.7. Thus, by color-coding according to the value for each component coordinate, it can be visually seen that dies having a low non-defective rate are concentrated in the vicinity of the center of the wafer for only the component B. Even in the result of the program of FIG. 1, the part B having the largest standard deviation is determined as the defect source. As a result of the determination, the map 53b is highlighted in the frame 63 to visually identify the part B as the defect source. It can be clearly shown.

  As described above, the present invention can automatically determine the previous process of the defect source in quality control or defect analysis, and output the screen as shown in FIG. Provide a method that can support determining

  In Example 1, the failure source was specified by using the result of the test 32 in the assembly process manufacturing line and the die ID assigned to each part. The present invention can be used not only for the result of the test 32 but also for analysis of what is determined as a defective product by customer inspection after the product is shipped.

  FIG. 8 is a block diagram in which a determination 34 by the customer is added after the product ID marking 33 shown in FIG. In this case, the program reads and executes data shown in FIG. 9 as an example. In FIG. 9, there is no pass / fail judgment result column as shown in FIG. 3, but a customer return result column is added instead. The mapping as shown in FIG. 5 is performed using the number of products shipped to the customer as the denominator of each coordinate and the number of products not returned from the customer as the numerator. The processing after mapping is the same as the program of FIG.

  In the first embodiment, the part A is 21a, the part B is 21b, and the part C is 21c, which is produced in a manufacturing process (processing process: manufacturing line) determined for each item of the parts. The present invention is also effective when parts of the same item are produced in different production processes (processing steps: production lines).

  FIG. 10 is a block diagram showing a third embodiment when the same component C is manufactured by two manufacturing lines. The part C is manufactured in the manufacturing process 21d, passed through the test 22d, the die ID marking 23d, and cutting (dicing) 24d, and then sent to the assembly process 31, and is manufactured in the manufacturing process 21e, and the test 22e and the die ID marking 23e. In some cases, parts C sent from either side are treated equally, and one of the parts C is treated as part A or the like. In combination with B, a multi-chip module product is manufactured.

  FIG. 11 is a process flow diagram showing a third embodiment of the data analysis program executed to determine the defect source of the product produced in the manufacturing process of FIG. In step 16, first, a die ID having position coordinate information in the substrate in the processing step and a quality result of the product are read. Here, unlike FIG. 1, information on the manufacturing base (factory) is entered in the die ID. Next, in steps 12d to 12g, the position coordinate information is recognized from the die ID for each item and factory read in step 16, and the quality result of the product is mapped with the two-dimensional position coordinate information. In this embodiment, three types of chips A, B, and C are mounted as parts in a multichip module product. Part A is factory A, part B is factory B, and part C is both factory A and B. This shows the case of production. In steps 13d to 13g, the distribution of the result of mapping in steps 12d to 12g is quantified for each part item and for each factory. In step 14, the quantified result is compared for each item of each part, and the item of the defective part is compared. Is output as the defect source 15.

  FIG. 12 is a diagram showing a third example of the result data in which the die ID read in the process of FIG. 11 is associated with the product ID and the quality result of the product. In the third embodiment, the information on the manufacturing base (factory) is also added to the die ID in FIG. In this third embodiment, the die ID is the item name from the left, the next one digit is the factory, the next three digits are the lot ID at the time of manufacturing the manufacturing process, the next two digits are the wafer ID, the next Two digits are defined as the X coordinate in the wafer, and the last two digits are defined as the Y coordinate in the wafer. For example, for a part A with a product ID of P031202551, the item name is A, the factory is A, the lot ID is 025, the wafer ID is 03, and the position coordinates formed in the wafer (substrate) are X = 03 and Y = 02. Can be identified.

  FIG. 13 shows an example of data distinguished for each mapping target within the processing of the program after reading FIG. In this example, FIG. 13 is classified by parts and by factory. Since there are parts C produced at the factory A and parts C produced at the factory B, the parts C were divided into two parts.

  As mentioned above, the Example of the semiconductor product was shown from Example 1 to 3. However, the present invention is not limited to a semiconductor product. For example, a magnetic disk device in which a magnetic head is formed on a wafer in a processing process and the magnetic head is assembled in a manufacturing process, or a thin film transistor substrate or the like is manufactured in a processing process. The present invention can also be applied to the manufacture of a liquid crystal display in which a backlight substrate is formed and assembled to a product in an assembly process. Since magnetic disk drives and liquid crystal displays also assemble semiconductor products in the assembly process, it is estimated which of the magnetic head and semiconductor product is the failure source, or which of the thin film transistor substrate, backlight substrate, and semiconductor product is the failure source. In order to achieve this, the present invention is effective.

It is a processing flow figure showing the 1st example of the data analysis program concerning the present invention. It is a block diagram which shows the 1st Example of the manufacturing process of the multichip module product which concerns on this invention. It is a figure which shows the 1st Example of the track record data which matched the product ID based on this invention, component ID, and the quality result in an assembly process. It is a figure which shows one Example of the position coordinate system previously provided on each wafer (board | substrate) over arbitrary number (300 pieces) about components AC based on this invention. It is a figure which shows one Example of distribution of the result which mapped the quality result of the product in the assembly process which concerns on this invention for every wafer (board | substrate). It is the block diagram which showed one Example of the quality control system of the product which concerns on this invention. It is a screen which shows one Example of the result analyzed by the data analysis unit which concerns on this invention. It is a block diagram which shows the 2nd Example of the manufacturing process and customer determination of the multichip module product which concerns on this invention. It is a figure which shows the 2nd Example of the performance data which matched the part ID which concerns on this invention, and the return result with respect to product ID from a customer. It is the block diagram which showed the 3rd Example of the manufacturing process of the multichip module product which concerns on this invention. It is the processing flowchart which showed the 3rd Example of the data analysis program which concerns on this invention. It is a figure which shows the 3rd Example of the performance data which matched part ID which concerns on this invention, product ID in an assembly process, and a quality result. It is a figure which shows one Example of the result of having classified data with the item name of the parts which concern on this invention, and a manufacturing base (factory).

Explanation of symbols

11, 16... Die ID and product pass / fail information reading process, 12 a, 12 b, 12 c... Mapping process of pass / fail result with coordinate information of die ID for each part item, 12 d, 12 e, 12 f, 12 g. Mapping process of pass / fail result based on coordinate information and base information of die ID, 13a, 13b, 13c, 13d, 13e, 13f, 13g ... Quantification process of mapping result of pass / fail result, 14 ... Defect source determination process 15a, 21b, 21c, 21d, machining process manufacturing process, 22a, 22b, 22c, 22d, 22e, machining process test, 23a, 23b, 23c, 23d, 23e, die ID marking process, 24a, 24b, 24c, 24d, 24e ... cutting (dicing), 31 ... assembly process manufacturing process, 32 ... assembly process Test, 33 ... Product ID marking process, 34 ... Pass / fail judgment by customer, 51a ... In-wafer coordinate system of part A, 51b ... In-wafer coordinate system of part B, 51c ... In-wafer coordinate system of part C, 52a ... Part Mapping result to A wafer coordinates, 52b ... Mapping result to component B wafer coordinates, 52c ... Mapping result to component C wafer coordinates, 60 ... Window on computer screen, 61 ... Coordinates of hatched parts, 62 ... Vertical stripes Coordinates of pattern parts, 63 ... Mark of failure source determination result, 91 ... Assembly process manufacturing line, 92 ... Part identification data reading device (identification information acquisition means), 93 ... Identification data management unit, 94 ... Test result management unit 95 ... Test apparatus (acceptance / non-acquisition means), 96 ... Data analysis unit (analysis means), 97 ... Local area network.

Claims (9)

A method for quality control of a semiconductor product when a semiconductor product is manufactured by assembling a plurality of semiconductor components of different types cut out from a plurality of wafers manufactured through different processing steps in an assembly process,
An identification information acquisition step of acquiring, in association with the semiconductor product, positional information on the wafer given to each semiconductor component of the plurality of semiconductor components assembled in the assembly step ;
And quality obtaining step of obtaining a quality result including also return whether the results from the customer's semiconductor products manufactured over a predetermined number,
The pass / fail result of the predetermined number of semiconductor products obtained in the pass / fail acquisition step is used as positional information on each wafer of the semiconductor component acquired in association with the semiconductor product in the identification information acquisition step. Mapping step for mapping on each wafer based on each wafer and creating a distribution of two-dimensional quality results on the corresponding wafer for each semiconductor component;
An analysis step for estimating a wafer that is a defect generation source of a semiconductor product by comparing and analyzing the distribution of the two-dimensional quality results on the wafer corresponding to each of the semiconductor components created in the mapping step. A characteristic quality control method for semiconductor products. A method for quality control of a semiconductor product when a semiconductor product is manufactured by assembling a plurality of semiconductor components of different types cut out from a plurality of wafers manufactured through different processing steps in an assembly process,
Identification in which the position information on the wafer given to each semiconductor component of the plurality of semiconductor components assembled in the assembling step and the information of the manufacturing factory that manufactured the wafer from which the semiconductor component was cut are associated with the semiconductor product and acquired. An information acquisition step;
And quality obtaining step of obtaining a quality result including also return whether the results from the customer's semiconductor products manufactured over a predetermined number,
The quality result of the semiconductor product over the predetermined number obtained in the quality acquisition step is the manufacturing factory that manufactured the wafer of the semiconductor component acquired in association with the semiconductor product in the identification information acquisition step. The distribution of the two-dimensional quality results on the wafer corresponding to each semiconductor component including each manufacturing factory by mapping on each wafer including each manufacturing factory based on the information and the positional information on each wafer Mapping step to create
By comparing and analyzing the distribution of the two-dimensional good / bad results on the wafer corresponding to each semiconductor part including each manufacturing factory created in the mapping step, it becomes a defect generation source of semiconductor products including each manufacturing factory. An analysis step for estimating a wafer, and a quality control method for a semiconductor product. 3. The quality control method for a semiconductor product according to claim 1, wherein in the quality acquisition step, a quality result of the semiconductor product is acquired based on a result of testing electrical characteristics of the semiconductor product. 3. The quality of a semiconductor product according to claim 1 or 2, wherein, in the analysis step, the distribution of the two-dimensional quality results is quantified when comparing the distribution of the two-dimensional quality results for each semiconductor component. Management method. 3. The semiconductor product quality control method according to claim 1, wherein the analysis step includes a display step of displaying a two-dimensional quality result distribution for each of the semiconductor parts created in the mapping step. . The analysis step includes a display step of displaying a distribution of the two-dimensional good / bad result created in the mapping step for at least a semiconductor component estimated as a defect generation source of a semiconductor product. 2. A quality control method for semiconductor products according to 2. A quality control system for a semiconductor product when a semiconductor product is manufactured by assembling a plurality of semiconductor components of different types cut out from a plurality of wafers manufactured through different processing steps, respectively, in the assembly step. an identification information acquisition means for acquiring location information on a plurality of semiconductor components the wafer assigned to each semiconductor component in association with the semiconductor products assembled,
A quality acquisition means for obtaining a quality result including also return whether the results from the customer's semiconductor products manufactured over a predetermined number,
The pass / fail results of the predetermined number of semiconductor products obtained by the pass / fail acquisition means are obtained as positional information on the wafers of the semiconductor components acquired in association with the semiconductor products by the identification information acquisition means. Based on the mapping on each wafer, a two-dimensional distribution of quality results on the wafer corresponding to each semiconductor component is created, and 2 on the wafer corresponding to each created semiconductor component. A quality control system for a semiconductor product, comprising: an analysis means for estimating a wafer which is a defect generation source of the semiconductor product by comparing and analyzing the distribution of the quality results of the dimensions. A semiconductor product quality control system for manufacturing a semiconductor product by assembling a plurality of different semiconductor components cut out from a plurality of wafers manufactured through different processing steps in an assembly process,
Identification in which the position information on the wafer given to each semiconductor component of the plurality of semiconductor components assembled in the assembling step and the information of the manufacturing factory that manufactured the wafer from which the semiconductor component was cut are associated with the semiconductor product and acquired. Information acquisition means;
A quality acquisition means for obtaining a quality result including also return whether the results from the customer's semiconductor products manufactured over a predetermined number,
The manufacturing for manufacturing a wafer obtained by cutting out the semiconductor component obtained by associating the result of accepting the semiconductor product over the predetermined number obtained by the accepting / acquisition means with the semiconductor product by the identification information obtaining means Two-dimensional pass / fail results on wafers corresponding to each semiconductor component including each manufacturing factory by mapping on each wafer including each manufacturing factory based on factory information and position information on each wafer The distribution of the two-dimensional quality results on the corresponding wafer for each semiconductor component including the manufacturing factory created is compared and analyzed to generate defects in the semiconductor product including the manufacturing factory. A quality control system for a semiconductor product, comprising an analysis means for estimating a wafer as a source. 9. The semiconductor product according to claim 7, wherein the identification information acquisition means is constituted by an identification data reading device, and the quality acquisition means is constituted by a test device for testing the quality of the electrical characteristics of the semiconductor product. Quality control system.

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