JP2007095953A - Semiconductor device sorting method and semiconductor device sorting device - Google Patents

Abstract

A semiconductor device sorting method and a semiconductor device sorting device that can efficiently eliminate semiconductor devices that are likely to be defective after market shipment.
A wafer main surface on which a semiconductor device to be selected is formed is divided into a plurality of regions, and an inspection defect in each divided region is based on inspection data acquired by an inspection performed in the manufacturing process of the semiconductor device. Calculate the rate. Based on the inspection defect rate, it is determined whether each area is a defective area or a normal area, and selection data in which all semiconductor devices belonging to the defective area are defective products is generated. As a result, it is possible to generate selection data in which a semiconductor device that should be a defective product is made defective among the semiconductor devices that are determined to be non-defective products in the inspection.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device sorting method and a semiconductor device sorting device for sorting a semiconductor device formed on a semiconductor wafer into a non-defective product and a defective product.

  2. Description of the Related Art Conventionally, in a semiconductor device manufacturing process, various inspections for sorting a plurality of semiconductor devices (hereinafter referred to as chips as appropriate) formed on a wafer into non-defective products and defective products have been performed. As such inspections, for example, defect inspection for inspecting the presence or absence of pattern deformation of the wiring formed on the wafer, adhesion of foreign matter, etc., inspection for the presence of scratches on the wafer and film thickness abnormality of the wiring interlayer film, etc. Visual inspection, and electrical inspection for inspecting whether the completed chip operates as specified. Only chips that are determined to be non-defective products in all inspections are selected as non-defective chips, and are advanced to a package sealing process or a shipping process.

In general, since a large number of chips having the same circuit structure are arranged on a wafer, each inspection result described above is stored in a predetermined storage device in association with positional information such as coordinates of the chip on the wafer. Has been. The determination of whether the chip is a non-defective product or a defective product is made based on the inspection results for each chip position stored in the storage device (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 4-61251

  However, in recent semiconductor devices, fine wirings are formed over many layers with low power consumption and high functionality, and the number of processing such as film formation, exposure, etching, etc. in the manufacturing process. Has increased. For this reason, many processing variations such as processing size variations in each processing step are overlapped, and the uniformity of characteristics such as electrical characteristics and functional characteristics of the formed chip in the wafer surface is lowered. Also, the recent increase in wafer diameter is a factor that reduces the in-plane uniformity of chip characteristics.

  For this reason, in-process inspections (line width, film thickness, number of particles attached to the wafer, etc., appearance inspection such as the number of particles adhering to the wafer and electrical inspection such as resistance values) performed in each processing step are narrowed. In addition to reducing processing variations in each processing step, by narrowing the standard range to be non-defective products in finished product inspection (electrical inspection such as electrical characteristics and functional characteristics) performed on completed chips, etc. The variation in the characteristics of chips finally selected as non-defective products is reduced.

  However, there are chips that become defective products (initial failures and accidental failures during use) after shipment, even though only the chips selected as good products as described above are shipped to the market. is doing. Among such chips that become defective products after market shipment (hereinafter referred to as potential defective products), chips that are determined to be non-defective products near the limit of non-defective product determination standards in the above inspection (hereinafter referred to as non-defective products near defective standard values). )) Is considered to be defective due to deterioration or characteristic fluctuation during use.

  It is desired that chips that become such potentially defective products are sorted as defective products before shipment. However, it is impossible to select chips that are determined as non-defective products in all inspection items as defective products. On the other hand, in order to select a chip that is a potentially defective product as a defective product, a method of further narrowing the standard range in inspection can be considered. When this measure is adopted, all non-defective products in the vicinity of the above-mentioned defective standard value become defective products, but many chips that are not potentially defective products (chips that may be determined as non-defective products) are also selected as defective products. As a result, the manufacturing yield of the chip is significantly reduced.

  The present invention has been proposed in view of the above-described conventional circumstances, and a semiconductor device sorting method and a semiconductor device sorting device that can efficiently eliminate a semiconductor device that is likely to become a potential defective product. The purpose is to provide.

  In order to achieve the above object, the present invention employs the following means. That is, according to the semiconductor device sorting method of the present invention, first, based on the inspection data acquired by the inspection performed in the manufacturing process of the semiconductor device to be selected, the semiconductor device is determined as non-defective in the inspection. The semiconductor device that should be a defective product is specified. Next, the identified semiconductor device and the semiconductor device that is determined as a defective product in the inspection are selected as defective products, whereby the semiconductor device formed on the wafer is selected as a good product and a defective product.

  The identification of a semiconductor device to be a defective product is performed, for example, in a state where the main surface of the wafer on which the semiconductor device to be sorted is formed is divided into a plurality of regions. At this time, the defect rate or non-defective rate of the semiconductor devices belonging to each divided area is calculated based on the inspection data. Then, it is determined whether or not the calculated defect rate or non-defective product rate satisfies the defect determination criterion, and all semiconductor devices belonging to the region determined to satisfy the defect determination criterion should be defective. Identified as a device.

  The divided one area does not need to be integrated. For example, a common area division is performed for each exposure unit in an exposure process for forming a semiconductor device, and an area at the same position in each exposure unit is defined as one area. Good. It is also possible to classify the areas common to the wafers belonging to the same lot and classify the areas at the same position in each wafer as one area.

  Also, the semiconductor device that should be a defective product can be specified based on the inspection data. In this case, an area on the wafer where semiconductor devices that are defective in the inspection are concentrated is specified based on the inspection data, and all semiconductor devices belonging to the specified area should be defective. A semiconductor device is used.

  Such a defect concentration region can be identified by, for example, extracting a region surrounded by semiconductor devices that are adjacent to defective semiconductor devices and that are surrounded by non-defective semiconductor devices. It is also possible to specify the defect concentration area based on the number of defects in the area set based on the processing distribution of the processing apparatus used in the processing step for forming the semiconductor device. Furthermore, the inspection data can be specified by extracting a series of unit areas including the number of defects equal to or greater than a preset threshold value.

  On the other hand, in another aspect, the present invention can also provide a semiconductor device sorting apparatus that embodies the sorting method described above. The selection apparatus includes an input unit to which wafer designation information capable of specifying a wafer to be selected is input. The inspection data acquisition unit stores the inspection data in which the results of the inspection performed in the process of manufacturing the semiconductor device on the wafer specified by the input wafer designation information are recorded, for example, the inspection data is collectively stored. From the external storage device. Then, the defective area specifying unit is based on the inspection result recorded in the inspection data acquired by the inspection data acquiring unit and the position information of the semiconductor device recorded in the inspection data in association with the inspection result. The semiconductor device that should be defective is identified from the semiconductor devices that are determined to be non-defective in the inspection. Thereafter, the sorting data generation unit generates sorting data in which the semiconductor device identified as a defective device by the defective area identification unit and the semiconductor device that is identified as a defective product in the inspection are recorded as defective products. To do.

  According to the present invention, a chip that is likely to be a defective product after being shipped to the market can be efficiently eliminated as a defective product, and the quality of semiconductor devices shipped to the market is improved. Can be made.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration of a sorting system including a semiconductor device sorting apparatus according to an embodiment of the present invention, and FIG. 2 is a configuration diagram illustrating a more detailed configuration of the sorting device 1. It is. FIG. 3 is a flowchart for explaining the sorting process of the sorting apparatus 1.

  First, based on FIG. 1, the environment where the sorting apparatus of this embodiment is used will be briefly described. As shown in FIG. 1, the sorting apparatus 1 according to the present embodiment is conventionally used for sorting semiconductor devices, for example, various inspections such as a defect inspection apparatus 31, an appearance inspection apparatus 32, and an electrical characteristic inspection apparatus 33. The semiconductor device is selected using the results of various inspections performed in the inspection device group 3 including the devices.

  Here, the defect inspection apparatus 31 is an apparatus for inspecting the presence / absence of foreign matter adhering to the wafer, the presence / absence of pattern defects such as wiring pattern deformation, and the like. The defect inspection is performed as an in-process inspection in a predetermined process of the semiconductor device manufacturing process. The appearance inspection apparatus 32 is an apparatus for inspecting wafer surface abnormalities such as scratches on the wafer and film abnormalities of the formed film. Similar to the defect inspection, the appearance inspection is performed as an in-process inspection in a predetermined process of the semiconductor device manufacturing process. Furthermore, the electrical characteristic inspection apparatus 33 is an apparatus for inspecting whether or not the semiconductor device chip performs an operation as specified by measuring electrical characteristics. The electrical characteristic inspection is usually performed after the formation of the semiconductor device is completed.

  Each inspection device 31, 32, 33 is configured to output each inspection result together with position information of the semiconductor device (chip). The defect inspection data output from the defect inspection apparatus 31 and stored in the defect inspection data storage unit 21 includes, for example, a flag (for example, a number indicating the number of defects counted in the chip and whether or not the chip is a defective product). , “0” for non-defective products and “1” for defective products) are recorded in association with the coordinates of the chip. The appearance inspection data output from the appearance inspection device 32 and stored in the appearance inspection data storage unit 22 includes, for example, a flag indicating the type of appearance abnormality in the chip, and whether or not the chip is defective. The indicated flag is recorded in association with the coordinates of the chip. Furthermore, in the electrical characteristic inspection data output from the electrical characteristic inspection device 33 and stored in the electrical characteristic inspection data storage unit 23, for example, measured values of various electrical characteristic inspection items of the chip and the chip is defective. Is stored in association with the coordinates of the chip. In this embodiment, each inspection data storage unit 21, 22, 23 is stored in a known storage device 2 such as an HDD (Hard Disk Drive) connected to each inspection device 31, 32, 33 via a network or the like. In this configuration, each inspection data is collectively stored in the storage device 2.

  In addition, here, information such as a wafer number and a lot number for specifying a wafer to be inspected from which inspection data has been acquired, and inspection data acquired by in-process inspection include the process from which inspection data has been acquired. Information for specifying is recorded as a file name and header data of each inspection data.

  The sorting device 1 reads out various inspection data stored in the storage device 2 via a network or the like, and based on the inspection data, the non-defective product in the inspection corresponding to the inspection data, as will be described in detail below. A chip that should be a defective product is identified from the chips that are assumed to be defective. Then, a chip to be defective and a chip which is defective in the inspection data are sorted as defective, and the sorting result is output as sorting data. In the sorting data, for example, a flag indicating whether or not the chip is defective is recorded in association with the coordinates of the chip. In the present embodiment, the sorting data output from the sorting device 1 is stored in the sorting data storage unit 24 provided in the storage device 2. As in the case of each inspection data described above, information such as a wafer number and a lot number for identifying a wafer to be sorted is recorded in the file name and header data of the sorting data so that the information can be identified.

  The sorting data stored in the sorting data storage unit 24 of the storage device 2 is read out by the assembling apparatus 4 via a network or the like, and the assembling apparatus 4 physically selects each chip on the wafer based on the sorting data. Select. Here, the assembling apparatus 4 is, for example, a marking apparatus that performs marking with ink on the surface of a defective chip, or a chip so that a good chip and a defective chip on a wafer can be distinguished from each other in appearance. This is a laser marking device for marking an identification character or the like on the front surface or the back surface. Further, the assembling apparatus 4 may be an apparatus that picks up only non-defective chips after dicing and die-bonds the chips to a package member or the like, or stores the chips in a chip storage container such as a chip tray.

  Note that the data format of each inspection data and selection data described above is not particularly limited, and any data format may be used as long as data can be exchanged between the apparatuses.

  Hereinafter, the detailed configuration of the sorting apparatus 1 according to the present embodiment will be described together with the operation thereof. As shown in FIG. 2, the sorting apparatus 1 includes an input unit 16 for inputting information (for example, a lot number and a wafer number) for specifying a wafer to be sorted by an operator. When the wafer designation information is input to the input unit 16, the data acquisition unit 11 performs all inspection data (in this case, defect inspection data, appearance inspection data, electrical characteristic inspection) in which the specified wafer is a wafer to be inspected. Data) or a part of the inspection data (for example, electrical characteristic inspection data) is read from each inspection data storage unit 21, 22, 23 of the storage device 2, and the inspection data is temporarily stored (FIG. 3 S1 → S2).

  In addition, after acquiring the inspection data or in parallel with the acquisition of the inspection data, an area setting unit 12 constituting the defective area specifying unit 10 is formed on the wafer specified by the input wafer specifying information. Identify the type of chip that is present. In the present embodiment, the area setting unit 12 stores data associating the wafer designation information with the chip type (product type). Then, the area setting unit 12 reads basic information corresponding to the specified chip type from the basic information storage unit 13 including a memory such as a RAM and a storage device such as an HDD, based on the specified chip type (see FIG. 3 S3).

  The basic information includes wafer information, shot information, equipment processing characteristic information, and the like, and these pieces of information are stored in the basic information storage unit 13 in association with the chip type. Here, each information which comprises basic information is demonstrated.

  First, the wafer information is data that associates each chip coordinate recorded in the inspection data with a position on the wafer, and includes the physical dimensions of the chip, the chip area, and the like. The shot information is data for identifying a chip group transferred by one exposure (shot) in an exposure process in which a circuit constituting a chip is transferred onto the wafer by a step-and-repeat method. The shot information includes, for example, an arrangement cycle of a chip group formed by each shot, coordinates indicating the position of each shot on the wafer, or coordinates of a chip at the same position in each shot. The equipment processing characteristic information is data indicating the processing characteristics of the processing equipment used for chip manufacture. Here, the processing characteristics refer to, for example, a distribution tendency generated on a wafer due to processing equipment such as a film thickness distribution in a film forming apparatus and an etching rate distribution in an etching apparatus. In addition, the information includes a distribution tendency of defects that occur on the wafer when an abnormality such as a failure occurs in the processing equipment. For example, in some equipment, in the case of equipment abnormality, a defect (processing defect, manufacturing Information such as a condition deviation is likely to occur. The facility processing characteristic information includes, for example, a flag for designating a region segmentation method, which will be described later, data indicating a distribution shape generated on the wafer, and the like.

  The area setting unit 12 that has acquired the basic information as described above divides the main surface of the wafer on which the chips are formed into a plurality of areas, and identifies the chips belonging to each area (S4 in FIG. 3). At this time, the number of divided areas, the size of the areas, and the like are not particularly limited.

  For example, FIG. 4 and FIG. 5 are diagrams illustrating examples of segmented regions when the region setting unit 12 segments the main surface of the wafer 41 into a plurality of regions. As is well known, since the characteristics of a semiconductor device vary depending on the crystal orientation of the wafer, in each manufacturing process of the semiconductor device, processing is performed with the wafer always directed in the same direction. Therefore, even when the main surface of the wafer is divided into a plurality of regions, it is necessary to define the orientation of the wafer. Therefore, in FIG. 4 and FIG. 5, the notch 42 (or orientation flat) formed on a part of the outer periphery of the wafer used for specifying the orientation of the wafer is downward (at 6 o'clock) in the drawings. Direction).

FIG. 4A is a diagram illustrating a state in which the main surface of the wafer 41 is divided into four (regions A1 to A4) by dividing lines L ₁ and L _{2 formed} by _two straight lines orthogonal to each other at the center of the wafer 41. FIG. 4 (b), section lines L _1, L ₂ consisting of a plurality of parallel straight lines with each other, ... and N dividing the main surface of the wafer 41 in the horizontal direction (An from region A1) by L _n-1 It is a figure which shows a state. FIG. 4 (c), marking lines L _1, L ₂ consisting of a plurality of parallel straight lines with each other, ... and N dividing the main surface of the wafer 41 in the vertical direction (An from region A1) by L _n-1 It is a figure which shows a state. FIG. 4 (d), division line L1 formed of a plurality of concentric circles centered at the wafer 41 around, L2, · · ·, a L _n-1, the main surface of the wafer 41 (An from region A1) N divided It is a figure which shows a state. FIG. 4 (e) shows that the main surface of the wafer 41 is radially divided into N parts by dividing lines L ₁ , L ₂ ,..., L _{n / 2} composed of a plurality of straight lines intersecting at the center of the wafer 41 ( It is a figure which shows the state carried out from area | region A1 to An). Note that the above classification method does not need to be used alone, and may be classified into a combined area. For example, FIG. 4F shows a state in which the main surface of the wafer 41 is divided into N parts by combining the four divisions shown in FIG. 4A and the concentric divisions shown in FIG. .

  FIG. 5A shows a common area division (here, 9 areas (areas A1 to A9)) for each shot (exposure unit) in an exposure process for forming a chip based on the wafer information and shot information. And the area at the same position in each shot 51 is shown as one area. In the section, one section area is not integrated and is distributed to each shot 51. Further, FIG. 5B is a diagram showing a state where one chip is divided into one region based on the wafer information.

  The shape of the region segment as described above is set in advance in the region setting unit 12. For example, one of the segment shapes is appropriately selected based on the above chip type, basic information, or input from the operator. . In addition, when performing the area division illustrated in FIGS. 4A to 4F, the division line may be located on the chip. Such a chip is, for example, in an area where the center point of the chip exists. It only has to belong.

  As described above, when the area division of the main surface of the wafer as illustrated in FIGS. 4 and 5 is completed, the area setting unit 12 specifies, for example, the area division information such as the coordinates of the chips belonging to each area as the defective area. The result is output to the pass / fail judgment unit 14 in the unit 10.

  The pass / fail judgment unit 14 sequentially reads out the inspection data of the chips belonging to each region divided by the region setting unit 12 based on the region division information from the inspection data acquisition unit 11, and calculates the inspection defect rate in each divided region (FIG. 3). S5). The inspection defect rate is a ratio of the total number of defective products included in the area to the total number of chips included in the target area. The total number of defective products can be easily obtained by counting the flags included in the inspection data. In addition, when the inspection data acquisition unit 11 acquires a plurality of types of inspection data for a specified wafer, chips determined as defective products in at least one inspection are counted as defective inspection products, and an inspection failure rate is calculated. The

  And the quality determination part 14 determines whether the test | inspection defect rate computed based on the defect determination criteria set beforehand satisfy | fills the defect determination criteria (FIG. 3 S6). In the present embodiment, a specific failure rate is set as a failure determination criterion, and the pass / fail determination unit 14 determines that the region is a failure region when the inspection failure rate is equal to or higher than a specific failure rate. . Moreover, the quality determination part determines the said area | region as a normal area | region for the area | region whose inspection defect rate is less than the said specific defect rate. Although the inspection defect rate is calculated here, it goes without saying that the same determination can be made even when the pass / fail determination unit 14 calculates the inspection acceptable product rate. In this case, a specific non-defective product rate is set as the defect determination criterion, and when the inspection good product rate is equal to or less than the specific non-defective product rate, the region is determined to be a defective region.

  The quality determination unit 14 notifies the selection data generation unit 15 of the determination result. Based on the information notified from the pass / fail determination unit 14, the selection data generation unit 15 makes all chips belonging to the areas determined as defective areas defective (FIG. 3, S6 Yes → S7). Here, “defect” means that a chip that has been determined to be non-defective in the inspection data of a designated wafer is determined to be defective. In the present embodiment, when the selection data generation unit 15 acquires the inspection data by the inspection data acquisition unit 11, a flag indicating whether the inspection data is defective or not is based on the inspection data and the coordinates of the chip. Corresponding data is generated. Then, based on the notification from the pass / fail determination unit 14, the selection data generation unit 15 performs failure by recording a flag indicating a defective product on all chips belonging to the defective area of the data. At this time, the selection data generation unit 15 does not change the pass / fail determination flag of the chip belonging to the normal region.

  The sorting data generated as described above is output from the sorting data generating unit 15 to the storage device 2 (S8 in FIG. 3) and used by the assembling device 4. When there is no defective area, the selection data generation unit 15 outputs the selection data generated as a defective product in the inspection data (S6 No → S8 in FIG. 3).

FIG. 6 is a diagram showing a specific example of chip selection by the above-described processing. FIG. 6 shows an example in which the area setting unit 12 divides the main surface of the wafer into three concentric areas from the dividing lines L ₁ and L ₂ based on the basic information (FIG. 4 (d). )reference). As described above, in this dividing method, the dividing lines L ₁ and L ₂ pass on the chip. Here, each chip belongs to a region including its center point. In FIG. 6, each chip 43 is indicated by a rectangle, and the boundary of each region is indicated by a bold line.

  As shown in FIG. 6A, when the chips belonging to each of the areas A1, A2, and A3 are specified by the area setting unit 12, the pass / fail judgment unit 14 is based on the inspection data acquired by the inspection data acquisition unit 11. The inspection defect rate of each area A1, A2, A3 is calculated. In FIG. 6A, the quality determination based on the inspection data is indicated on each chip 43 by a circle mark (◯) for a non-defective product and a cross mark (×) for a defective product.

  FIG. 7 is a diagram illustrating the inspection failure rate of each of the areas A1, A2, and A3 illustrated in FIG. As shown in FIG. 7, the inspection defect rate of each region is 8.3% for region A1, 10% for region A2, and 71.1% for region A3. Here, in this example, a defect rate of 56% is set in the pass / fail determination unit 14 as a failure determination criterion. For this reason, the pass / fail determination unit 14 determines that the region A1 and the region A2 are normal regions, and determines that the region A3 is a defective region. Based on this determination, the selection data generation unit 15 makes all chips belonging to the defective area A3 defective. As a result, as shown in FIG. 6B, selection data in which all the chips 43 in the area A3 are defective is output from the generation unit 15.

  The distribution of defective products as shown in FIG. 6A may occur, for example, in a diffusion process in which impurity ions are implanted into the surface portion of the semiconductor substrate to diffuse the impurity diffusion region. For this reason, a chip that is non-defective in the area A3 with a high inspection defect rate has the same type of defect factor as other chips that are defective in the area A3, and can meet the non-defective standard for inspection due to characteristic variations. High nature. For this reason, it is highly possible that the product is a potential defective product that becomes a defective product after being shipped to the market. As described above, according to the present invention, such a potential defective product can be surely eliminated.

  FIG. 8 is a diagram showing another specific example of chip selection by the above-described processing. In FIG. 8, the area setting unit 12 divides the main surface of the wafer for each shot 51 in the exposure process for forming a chip based on the basic information, and is in the same position in each shot 51. A state is shown in which the areas are divided into one area (see FIG. 5A). In this example, as shown in FIG. 8A, the shot 51 is composed of nine chips 43, and the chips at the same position in each shot 51 belong to one segmented region.

  As shown in FIG. 8A, when the chips belonging to the respective regions A1 to A9 are specified by the region setting unit 12, the pass / fail determination unit 14 determines whether each region is based on the inspection data acquired by the inspection data acquiring unit 11. The inspection defect rate (here, the number of defects) of A1 to A9 is calculated. FIG. 8B is a diagram showing pass / fail judgment based on the inspection data of the sorting target wafer in this case. In FIG. 8B, as in FIG. 6A, the non-defective product is indicated by a circle (O) and the defective product is indicated by a cross (X) on each chip 43.

  In FIG. 8B, the number of defects in the area A8 is 5, which is larger than the other areas. Here, in this example, 5 defective rates (40% defective rate) are set in the pass / fail determination unit 14 as the failure determination criteria. For this reason, the pass / fail determination unit 14 determines that the area A8 is a defective area. By this determination, the sorting data generation unit 15 makes all chips belonging to the defective area A8 defective. As a result, as shown in FIG. 8C, sorting data in which the chips 43 in the area A8 are all defective is output from the generation unit 15. In FIGS. 8B and 8C, the region A8 is indicated by a bold line.

  The distribution of defective inspections as shown in FIG. 8A occurs when, for example, foreign matter adheres to the surface of a reticle (or mask) used in the exposure process, or a focus shift occurs during exposure. Sometimes. For this reason, a chip that is non-defective in the area A8 with a large number of defects has the same type of defect factor as other chips that are defective in the area A8, and may be in a non-defective standard for inspection due to characteristic variations. Is expensive. For this reason, it is highly possible that the product is a potential defective product that becomes a defective product after being shipped to the market. As described above, according to the present invention, such a potential defective product can be surely eliminated.

  Further, FIG. 9 is a diagram showing still another specific example of chip selection by the above-described processing. FIG. 9 shows a state in which the region setting unit 12 divides the main surface of the wafer into one region based on the basic information (see FIG. 5B). Usually, in a semiconductor device manufacturing process, for example, a semiconductor device is manufactured in units of lots in which 25 wafers are taken as one unit. The sorting method of this example is suitable for sorting a series of wafers in such a lot.

  When chips belonging to each of the regions classified as described above are specified by the region setting unit 12, the pass / fail determination unit 14 determines the inspection failure rate of each region (here, based on the inspection data acquired by the inspection data acquisition unit 11) Then, the number of defects) is calculated. FIG. 9A is a diagram showing the value of the number of defective inspections in each region counted by the pass / fail judgment unit 14. In FIG. 9A, the numbers shown on each chip 43 are the number of inspection failures in each region. For example, if the number of defects is 3, it means that there are defective products on three wafers in the lot.

  In this example, 19 defect rates (76% defect rate) are set in the pass / fail determination unit 14 as the failure determination criteria. For this reason, the pass / fail determination unit 14 determines the area indicated by the bold line in FIG. 9A as a defective area. Based on the determination, the sorting data generation unit 15 makes all chips belonging to the defective area defective. That is, the sorting data generation unit 15 selects sorting data in which all the chips 43 in the defective area are defective as shown in FIG. 9B as sorting data for each wafer in a series of wafers to be inspected. Output. Here, when the sorting data for each wafer is generated, the sorting data generation unit 15 only performs the defect of the area indicated by the bold line in FIG. 9B, and for the chips in other areas. The inspection result is not changed.

  Since wafers belonging to the same lot are processed by the same apparatus at the same time, defects having the same cause tend to occur. For this reason, a chip that is non-defective in an area with a large number of defects has the same type of defect factor as other chips that are defective in that area, and may be in the non-defective standard for inspection due to characteristic variations. high. For this reason, it is highly possible that the product is a potential defective product that becomes a defective product after being shipped to the market. As described above, according to the present invention, such a potential defective product can be surely eliminated.

  By the way, the case where the area setting unit 12 appropriately selects a preset segment shape and divides the wafer main surface into a plurality of areas has been described above. However, the region setting unit 12 may set a region to be defective based on the inspection data. FIG. 10 is a flowchart showing a semiconductor device selection method when the region setting unit 12 specifies a region to be defective based on the inspection data acquired by the inspection data acquisition unit 11.

  Similar to the flowchart shown in FIG. 3, when wafer designation information is input to the input unit 16, the data acquisition unit 11 displays all inspection data in which the designated wafer is a wafer to be inspected, or one Inspection data is read from the storage device 2, and the inspection data is temporarily stored (S1 → S2 in FIG. 10). Next, the area setting unit 12 specifies the chip type formed on the wafer designated by the inputted wafer designation information after obtaining the inspection data or concurrently with obtaining the inspection data. Corresponding basic information is read from the basic information storage unit 13 (S3 in FIG. 10).

  In this example, next, the region setting unit 12 extracts a region where defective inspection chips are concentrated based on the inspection data acquired by the inspection data acquisition unit 11 (S11 in FIG. 10).

  Here, the defect concentration area can also be specified by extracting a series of unit areas including the number of defects equal to or greater than a preset threshold value in the inspection data. For example, in FIG. 11A, an area composed of 2 × 2 chips is set as a unit area 46, and for example, a series of unit areas 46 in which two or more defective chips are present is specified as a defect concentration area 45. Yes. That is, the defect concentration area 45 specified in this way includes two or more defective chips in any unit area 46 (for example, areas 46a, 46b, and 46c indicated by broken lines in FIG. 11A). It is out.

  When the defect concentration area 45 is specified as described above, the area setting unit 12 determines whether the area is the defect concentration area 45, for example, area classification information such as the coordinates of the chips belonging to the defect concentration area 45. The determination unit 14 is notified. In this case, the quality determination unit 14 immediately determines that the area set as the defect concentration area 45 is a defective area.

  The quality determination unit 14 notifies the selection data generation unit 15 of the determination result. Based on the information notified from the pass / fail determination unit 14, the selection data generation unit 15 makes all chips belonging to the areas determined as defective areas defective (FIG. 10, S12 Yes → S13). Thereafter, similarly to the example shown in FIG. 3, the generated sorting data is output from the sorting data generating unit 15 to the storage device 2 (S8 in FIG. 10) and used by the assembly device 4. When there is no defective area, the sorting data generation unit 15 outputs data generated based on the inspection data as sorting data (S12 No → S8 in FIG. 10).

  As a result of the above-described failure, the sorting data generating unit 15 determines that all the chips 43 in the failure concentration region 45 are defective as shown in FIG. 11B for the wafer 41 shown in FIG. The sorted data is output.

  As described above, a chip that is non-defective in inspection in a defect concentration area with a large number of defects has the same type of defect factor as other chips that are inferior in inspection in that area. There is a high possibility that it is within the standard. For this reason, it is highly possible that the product is a potential defective product that becomes a defective product after being shipped to the market. As described above, according to the present invention, such a potential defective product can be surely eliminated. Further, in this example, since such a defect concentration area is extracted and specified as a defect area according to the inspection data, the defect area can be set more appropriately.

  The extraction of the defect concentration area is performed by the area setting unit 12 creating a map illustrating the position of the defective chip on the wafer based on the inspection data and the wafer information. Can be performed by searching for a shape similar to the processing distribution shape recorded as. Such a search for similar shapes can be performed using a known pattern matching technique.

  Or the said defect concentration area | region can also specify the area | region containing the chip | tip adjacent to the chip | tip with which the specific test | inspection item is defect in the said inspection data as a defect concentration area | region. Such a specification is suitable for the case where a failure due to the same factor is expected across a plurality of adjacent chips, such as a sheet resistance abnormality in the diffusion process described above and a film thickness abnormality in the film formation process.

  Furthermore, the defect concentration area is defined as an area including two or more defective chips adjacent to the defect concentration area, and when there is a defect chip on the outer periphery of the defect concentration area, It can also be specified by sequentially expanding the defect concentration area. In this case, the final defect concentration area is specified when an area in which all of the outer peripheral chips are inspection nondefective chips or an area including a predetermined number or less of inspection defective chips is added to the defect concentration area.

  As described above, according to the present invention, it is possible to appropriately eliminate potential defective products that are highly likely to fail in the market after shipment. For this reason, the quality of the semiconductor device shipped to the market can be improved.

  The present invention is not limited to the embodiments described above, and various modifications and applications are possible within the scope of the effects of the present invention. For example, as shown in FIG. 2, the sorting data generated by the sorting data generation unit 15 is converted into past sorting information such as data indicating the distribution shape on the wafer in the same way as the equipment processing characteristic information, It is also possible to record in the basic information storage unit 13 in association with the formed chip type and use the past sorting information as part of the basic information for sorting other wafers. As a result, when sorting data is generated, it is possible to feed back a distribution tendency of defective products by the latest sorting.

  INDUSTRIAL APPLICABILITY The present invention can efficiently eliminate a chip having a high possibility of being a potentially defective product as a defective product, and is useful as a semiconductor device sorting method and a semiconductor device sorting device.

1 is a configuration diagram showing an example of a sorting system in which a sorting apparatus according to the present invention is used. Configuration diagram of sorting apparatus according to the present invention Flow diagram showing a sorting method according to the present invention Schematic diagram illustrating the area division of the present invention Schematic diagram illustrating the area division of the present invention Schematic diagram illustrating an example of sorting using the sorting method of the present invention Schematic diagram illustrating an example of defective area determination of the present invention Schematic diagram illustrating another example of sorting using the sorting method of the present invention Schematic diagram illustrating another example of sorting using the sorting method of the present invention Flow chart showing a modification of the sorting method according to the present invention Schematic diagram illustrating an example of sorting using the sorting method of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sorting device 2 Storage device 3 Inspection device group 4 Assembly device 21 Defect inspection data storage unit 22 Visual inspection data storage unit 23 Electrical characteristic inspection data storage unit 24 Sorting data storage unit 31 Defect inspection device 32 Visual inspection device 33 Electrical characteristic inspection Device 10 Defected area identification unit 11 Inspection data acquisition unit 12 Area setting unit 13 Basic information storage unit 14 Pass / fail judgment unit 15 Sorting data generation unit 16 Input unit 41 Wafer 45 Defect concentration area

Claims (9)

A semiconductor device sorting method for sorting a semiconductor device formed on a wafer into a good product and a defective product,
Identifying a semiconductor device that should be a defective product from the semiconductor devices that are determined to be non-defective products in the inspection based on the inspection data acquired by the inspection performed in the manufacturing process of the semiconductor device to be selected;
Screening the identified semiconductor device and the semiconductor device which is a defective product in the inspection, as a defective product;
A method for selecting a semiconductor device, comprising: The step of identifying a semiconductor device to be defective is
Dividing the wafer main surface on which the semiconductor device to be selected is formed into a plurality of regions;
Calculating a defect rate or a non-defective rate of a semiconductor device belonging to each of the divided areas based on the inspection data;
Determining whether the calculated defect rate or non-defective product rate satisfies a defect determination criterion;
Identifying all semiconductor devices belonging to the segmented region determined to satisfy the defect determination criteria as semiconductor devices to be the defective products;
The method for selecting a semiconductor device according to claim 1, comprising:   The semiconductor device sorting method according to claim 2, wherein the divided region is set based on a processing distribution of a processing apparatus used in a processing step of forming the semiconductor device.   The semiconductor device sorting method according to claim 2, wherein the divided regions are configured by regions located at the same position in an exposure unit in an exposure step of forming the semiconductor device.   3. The semiconductor device sorting method according to claim 2, wherein the divided area is constituted by areas located at the same position in each wafer belonging to the same lot. The step of identifying a semiconductor device to be defective is
Based on the inspection data, identifying a region on the wafer in which semiconductor devices that are defective in the inspection are concentrated, and
Identifying all semiconductor devices belonging to the specific region as semiconductor devices to be defective products;
The method for selecting a semiconductor device according to claim 1, comprising:   The semiconductor device selection method according to claim 6, wherein the defect concentration region is specified based on the number of defects in the region set based on a processing distribution of a processing apparatus used in a processing step of forming the semiconductor device. .   The semiconductor device sorting method according to claim 6, wherein the defect concentration area is identified by extracting an area in which unit areas containing defective products equal to or more than a preset number of defects are extracted from the inspection data. A semiconductor device sorting apparatus for sorting a semiconductor device formed on a wafer into a non-defective product and a defective product,
Means for acquiring wafer designation information capable of identifying a wafer to be sorted;
Means for acquiring inspection data in which a result of an inspection performed in a manufacturing process of a semiconductor device on the wafer specified by the wafer designation information is recorded;
Based on the inspection result recorded in the inspection data and the position information of the semiconductor device recorded in the inspection data in association with the inspection result, the semiconductor device determined as non-defective in the inspection is selected. Means for identifying a semiconductor device to be a good product;
Means for generating sorting data in which the identified semiconductor device and the semiconductor device which is regarded as a defective product in the inspection are determined as defective products;
An apparatus for sorting semiconductor devices, comprising:

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