JP4617700B2 - Display device and display device layout method - Google Patents

Description

  The present invention relates to a display device and a display device layout method, and more particularly to a display device in which pixels including electro-optic elements are two-dimensionally arranged in a matrix and a switch circuit layout method in the display device.

  In a display device in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, for example, a liquid crystal display device using a liquid crystal cell as the electro-optical element of a pixel, contrast is obtained by applying a voltage to the liquid crystal cell. ing. In the active matrix type liquid crystal display device, a voltage is applied to the liquid crystal cell by providing a capacitor (pixel capacitor) and a switch element (pixel switch) in the pixel region, and charging the pixel capacitor via the pixel switch. Done. In addition, the charge to the pixel capacitor is selected by selecting each pixel of the pixel array unit in a row unit, while a video signal inputted from the outside through a video line is sent to a signal line wired for each pixel column of the pixel array unit. Through each pixel in the selected row.

  As a method for writing an externally input video signal to a pixel, generally, n video lines are wired in a one-to-one correspondence with n signal lines of a pixel array unit, and an external driver is provided. There is known a method of supplying n video signals input from an IC as they are to n corresponding signal lines via n video lines. However, in this writing method, when the number n of signal lines increases with the trend toward higher resolution and higher definition of display devices in recent years, the same number of video lines as the signal lines are wired. It becomes difficult to input a plurality of video signals in parallel through the video line.

  Therefore, the video lines are wired on the display panel by the number N (N << n) which is extremely smaller than n, and the video signals are developed and inputted to the N phase from the outside, while the N video lines and the pixel array unit are input. The switch circuit is arranged in units of N between the signal lines and the N number of switch circuits are simultaneously driven using the same switch control signal, so that N pixels are selected for each pixel in the selected row. A method of simultaneously writing N-phase expanded video signals (hereinafter referred to as “phase expansion driving method”) is used (for example, see Patent Document 1). According to this phase development driving method, the number of video lines wired on the display panel can be greatly reduced.

  In an active matrix liquid crystal display device adopting the phase expansion driving method, when a video signal is input through a video line and a switch control signal for driving the switch circuit is activated, the switch circuit is turned on during the active period. By connecting the video line to the signal line, the potential of the video line (potential determined according to the video signal) is written to the pixel through the signal line. Then, after the signal line has the same potential as the video line, the active period of the switch control signal ends and the switch circuit is turned off, so that the potential corresponding to the video signal is held in the signal line and the pixel. .

Japanese Patent Laid-Open No. 11-65536

  Here, the ON period of the switch circuit is determined by the load of the signal line, the load of the pixels, and the number of pixels in the horizontal direction. In recent years, high-definition image display has been required, and the number of pixels of display devices tends to increase. As described above, when the number of pixels increases with the increase in definition, when the phase expansion driving method is employed, the time for writing to one pixel is shortened due to the small number of video lines. This is because it is necessary to write a video signal to each pixel for one row within a horizontal period determined by the standard.

  Here, for example, assuming that N = 4, that is, a case where a four-phase phase driving method is employed, as shown in FIG. 6, signal lines 52-1 and 52-52 of the pixel array unit 51 are used. .., And four video lines 53-1 to 53-4, a switch circuit (for example, an Nch transistor and a Pch transistor connected in parallel in units of four signal lines) Switches) 54-1, 54-2,... Are arranged. And these transfer switches 54-1, 54-2,... Are driven by the same switch control signal CS (because they are transfer switches, so that they are in reverse phase to each other). become.

  In FIG. 6, only one system of control lines 55-1 and 55-1X is shown as a control line for supplying switch control signals CS and CSX having opposite phases to the transfer switches 54-1, 54-2,. However, when the number n of pixels in the horizontal direction is n = 100 pixels, actually, 25 lines (= 100/4) of control lines 55-1, 55-1X to 55-25, 55-25X are prepared. Will be. In the case of n = 100 pixels, 1/25 (H is a horizontal scanning period) is 1/25 of the writing time. If the time for writing to one pixel is shortened, a sufficient potential cannot be written to the pixel, resulting in a decrease in image quality, such as a decrease in contrast and vertical streak-like noise due to variations in pixel characteristics. appear.

  On the other hand, by increasing the number of video lines to some extent, a method of improving the problem caused by the writing time can be considered. However, when this improvement method is employed, the phase expansion drive method cannot be employed for the following reasons associated with the layout of the transfer switches 54-1, 54-2,. The reason will be described below.

  When arranging the transfer switches 54-1, 54-2,..., Since the control lines 55-1, 55-1X to 55-25, 55-25X are common in units of four, the switch circuit is larger than the pixel size. Is larger (the switch size tends to be larger than the pixel size as the definition becomes higher), it is necessary to arrange a switch circuit in one pixel width, video lines 53-1 to 53-4 and signal lines Considering that a low-resistance wiring layer is required as 52-1, 52-2,..., Transfer switches 54-1 and 54-2, 54- for two adjacent pixels as shown in FIG. 3 and 54-4,... Must be arranged in a two-stage vertically stacked area within a two-pixel width region.

  As described above, in the active matrix type liquid crystal display device adopting the phase expansion driving method, the transfer switches 54-1, 54-2,... I have to adopt a configuration to do. However, if the transfer switches 54-1 and 54-2, 54-3 and 54-4,... For two adjacent pixels are vertically stacked in a two-pixel width region, the signal lines of two adjacent pixels Therefore, there is a difference between the parasitic capacitance of each pixel, that is, the parasitic capacitance between the signal line of the odd pixel and the signal line of the even pixel.

  The present invention has been made in view of the above problems, and the object of the present invention is to provide a difference in parasitic capacitance for each signal line of two adjacent pixels even when the number of video lines is increased. It is an object of the present invention to provide a display device capable of laying out a switch circuit without causing a problem, and a switch circuit layout method in the display device.

  In order to achieve the above object, according to the present invention, a pixel array in which pixels including electro-optic elements are two-dimensionally arranged in a matrix on a substrate and signal lines are wired for each column in the matrix array. When the number of the signal lines is n, each of the n signal lines is adjacent to each other in units of N (N is an integer of 2 or more). N / N video lines are wired so that the output terminals are positioned between the signal lines, and switch means is connected between the output terminals of the n / N video lines and the two signal lines. The structure to do is taken.

  In the display device having the above-described configuration, when two switch means corresponding to two signal lines are arranged in a region corresponding to two pixels, the video line is positioned between two adjacent signal lines at the output end. In addition, the switch means is connected between the output terminal and two signal lines, so that the two switch means can be laid out symmetrically in a side-by-side manner for every two pixels.

  According to the present invention, the video line is wired so that its output end is located between every two adjacent signal lines, and the switch means is connected between the output end and the two signal lines. Thus, since the two switch means can be laid out symmetrically in a side-by-side manner for every two pixels, the switch circuit can be laid out without causing a difference in parasitic capacitance between the signal lines of two adjacent pixels.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of the configuration of a display device according to an embodiment of the present invention. Here, as an example, an active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. As is clear from FIG. 1, in the active matrix liquid crystal display device according to this embodiment, the pixel array unit 11, the vertical drive circuit 12, and the switch circuit 13 are provided on the same substrate (hereinafter referred to as a display panel) 14. It is the composition which was made.

  In the pixel array unit 11, pixels 20 including liquid crystal cells as electro-optical elements are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (not shown), and m rows of the pixels 20 are arranged. In the arrangement of n columns, scanning lines 15-1 to 15-m are wired for each row, and signal lines 16-1 to 16-n are wired for each column. The first glass substrate is disposed opposite to a second glass substrate (not shown) with a predetermined gap, and a liquid crystal material is sealed between the first glass substrate and the display panel. 14 is constituted.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel (pixel circuit) 20. As apparent from FIG. 2, the pixel 20 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 21, a liquid crystal cell 22 in which the pixel electrode is connected to the drain electrode of the TFT 21, and one of the drain electrode of the TFT 21. And a storage capacitor 23 to which the electrodes are connected. Here, the liquid crystal cell 22 means a liquid crystal capacitance Clc generated between the pixel electrode and a counter electrode formed opposite to the pixel electrode.

  The TFT 21 has a gate electrode connected to the scanning line 15 (15-1 to 15-m) and a source electrode connected to the signal line 16 (16-1 to 16-n). Further, for example, the counter electrode of the liquid crystal cell 22 and the other electrode of the storage capacitor 23 are connected to the common line 24 in common for each pixel. A common voltage (counter electrode voltage) Vcom is applied to the common electrode of the liquid crystal cell 22 via the common line 24.

  The vertical drive circuit 12 is disposed, for example, on the left side of the pixel array unit 11. Here, the configuration in which the vertical drive circuit 12 is disposed on the left side of the pixel array unit 11 is described as an example, but the vertical drive circuit 12 is disposed on the right side of the pixel array unit 11 or on both the left and right sides of the pixel array unit 11. It is also possible to adopt a configuration in which The vertical drive circuit 12 is configured by a shift register, a buffer circuit, and the like, and is synchronized with a vertical clock pulse VCK (generally, vertical clock pulses VCK and VCKX having phases opposite to each other) by receiving a vertical start pulse VST. Thus, the vertical scanning pulses φV1 to φVm are sequentially output and applied to the scanning lines 15-1 to 15-m of the pixel array unit 11, whereby the pixels 20 are sequentially selected in units of rows.

  The switch circuit 13 includes n switches SW1 to SWn corresponding to the number n of pixels in the horizontal direction of the pixel array unit 11, that is, the signal lines 16-1 to 16-n. One end of each of the n switches SW1 to SWn is commonly connected in units of, for example, four pixels of the number n of pixels in the horizontal direction of the pixel array unit 11, that is, four signal lines 16-1 to 16-n. In addition, each other end is connected to one end of each of the signal lines 16-1 to 16-n. A number of video lines 17 are wired on the display panel 14 with respect to the switch circuit 13.

  Here, the video lines 17 are wired in n / N lines when N lines (N is an integer of 2 or more, 4 lines in this example) for each of the signal lines 16-1 to 16-n. Will be. N video signals Vsig1 to VsigN are input to the video lines 17-1 to 17-N from the outside of the display panel 14.

  In the switch circuit 13, one end of the first switch group SW1 to SW4 that is commonly connected is the first video line 17-1, and one end of the second switch group SW5 to SW8 that is commonly connected is the second video line. 17-2,..., One end of the last switch group SWn-3 to SWn connected in common is connected to the Nth video line 17-N. These four switch groups SW1 to SW4, SW5 to SW8,..., SWn-3 to SWn are inputted from the outside of the display panel 14 via control lines 18-1 to 18-4. On / off control is performed by the control signals CS1 to CS4.

  As the switches SW1 to SWn of the switch circuit 13, for example, as shown in FIG. 3, a transfer switch (analog switch) 30 in which an Nch transistor Qn and a Pch transistor Qp are connected in parallel is used. However, the switches SW1 to SWn are not limited to the transfer switch 30, and only an Nch transistor or only a Pch transistor can be used.

  FIG. 4 is a circuit diagram showing a circuit configuration when the transfer switches 30-1 to 30-4 are used as the switches SW1 to SW4 for the first switch group, for example. When the transfer switch is used, switch control signals CS1, CS1X to CS4, CS4X having opposite phases to each other are required as switch control signals. In order to transmit the switch control signals CS1, CS1X to CS4, CS4X, a total of eight control lines 18-1, 18-1X to 18-4, 18-4X are wired.

  FIG. 5 is a plan pattern diagram showing a layout of the transfer switches 30-1 to 30-4 in the first switch group SW1 to SW4. In FIG. 5, four transfer switches 30-1 to 30-4 provided in units of four pixels in the horizontal direction, that is, four signal lines 16-1 to 16-4 are arranged in a region corresponding to two pixels in the horizontal direction. They are arranged side by side. The video line 17-1 is branched into two systems. The two output terminals 17-1A and 17-1B of the video line 17-1 are positioned between two adjacent signal lines 16-1 and 16-2 and between 16-3 and 16-4. Has been placed.

  Transfer switches 30-1 and 30-2 are connected between one output terminal 17-1A and the two signal lines 16-1 and 16-2. As an example, between the output terminal 17-1A and the signal line 16-1, the Nch transistor and the Pch transistor of the transfer switch 30-1 are arranged in a vertically stacked form with the Nch transistor on the upper side, and the output terminal 17-1A. And the signal line 16-2, the Pch transistor and the Nch transistor of the transfer switch 30-2 are arranged in a vertically stacked manner with the Pch transistor on the upper side.

  Thereby, the transfer switches 30-1 and 30-2 are arranged side by side in a region for two pixels in the horizontal direction. In the transfer switch 30-1, the gate electrodes of the Nch transistor and the Pch transistor are connected to the control lines 18-1 and 18-1X by connection wirings 19-1 and 19-2, respectively. In the transfer switch 30-2, the gate electrodes of the Nch transistor and the Pch transistor are connected to the control lines 18-2 and 18-2X by connection wirings 19-3 and 19-4, respectively.

  Also, transfer switches 30-3 and 30-4 are connected between the other output terminal 17-1B and the two signal lines 16-3 and 16-4. As an example, between the output terminal 17-1B and the signal line 16-3, the Nch transistor and the Pch transistor of the transfer switch 30-3 are arranged in a vertically stacked manner with the Nch transistor on the upper side, and the output terminal 17-1B. And the signal line 16-4, the Pch transistor and the Nch transistor of the transfer switch 30-4 are arranged in a vertically stacked manner with the Pch transistor on the upper side.

  Thereby, the transfer switches 30-3 and 30-4 are arranged side by side in a region for two pixels in the horizontal direction. In the transfer switch 30-3, the gate electrodes of the Nch transistor and the Pch transistor are connected to the control lines 18-3 and 18-4X by connection wirings 19-5 and 19-6, respectively. In the transfer switch 30-4, the gate electrodes of the Nch transistor and the Pch transistor are connected to the control lines 18-4 and 18-4X by connection wirings 19-7 and 19-8, respectively.

  Here, the video lines 17-1 and the signal lines 16-1 to 16-4 need to use low resistance wiring layers, whereas the control lines 18-1, 18-1X to 18-4, For the 18-4X and the connection wirings 19-1 to 19-8, a wiring layer having a somewhat higher resistance than the video lines 17-1 and the signal lines 16-1 to 16-4 can be used.

  In this example, the case of the layout of the transfer switches 30-1 to 30-4 in the first switch group SW1 to SW4 has been described as an example, but the second switch group SW5 to SW8 to the last switch group are described. The layout of each transfer switch in SWn-3 to SWn is exactly the same.

  In the example shown in FIG. 5, the transfer switches 30-1 and 30-3 are arranged with the Nch transistor on the upper side and the Pch transistor on the lower side, and the transfer switches 30-2 and 30-4 are arranged with the Pch transistor. Although the Nch transistor is arranged on the upper side with the Nch transistor on the lower side, this arrangement example is only an example, and all the transfer switches 30-1 to 30-4 are arranged with the Nch transistor on the upper side and the Pch transistor on the lower side. Conversely, it is also possible to arrange the Pch transistor on the upper side and the Nch transistor on the lower side.

  As described above, pixels 20 using liquid crystal cells as electro-optic elements are arranged in a matrix, and pixels in which signal lines 16-1 to 16-n are wired for each pixel column in the matrix arrangement. In the active matrix liquid crystal display device including the array unit 11, the time for writing to one pixel can be increased by increasing the number N of video lines 17-1 to 17-N. As an example, when the number of pixels n in the horizontal direction is set to n = 100 pixels, the prior art can secure only 1 / 25th of the 1H period as the writing time to the pixel, whereas the 1H period A quarter of the time can be secured. Accordingly, a sufficient potential can be written to the pixel, so that the problem of image quality deterioration such as contrast reduction and vertical stripe noise can be solved.

  Further, each of the n video lines 17-1 to 17-N is adjacent to each other in units of N (four in this example) for each of the n signal lines 16-1 to 16-n. Wiring is performed so as to be positioned between each signal line, and a switch circuit, in this example, transfer switch 30, is connected between each output end of these video lines 17-1 to 17-N and two signal lines. By adopting the layout method, the layout of the two transfer switches 30-1 and 30-2, 30-3 and 30-4,. The switch circuit can be arranged without causing a difference in the parasitic capacitance between the signal lines of two adjacent pixels.

  Further, as is clear from FIG. 5 in particular, the video line 17-1 and the signal lines 16-1 to 16-4 do not have to be routed around the transfer switches 30-1 to 30-4. The same can be said for the eight control lines 18-1, 18-1X to 18-4, 18-4X. Thus, since there is no routing wiring around the transfer switches 30-1 to 30-4, the vertical direction (vertical direction) and the horizontal direction (horizontal direction) of the transfer switches 30-1 to 30-4 are accordingly increased. Therefore, it is possible to dispose the switch circuit 13 even in a liquid crystal display device with a fine pixel pitch accompanying high definition, and to ensure sufficient writing time for the video lines 17-1 to 17-. Even when the number N of wirings N is increased, the switch circuit 13 can be arranged without increasing the size of the display panel 14.

  Furthermore, due to the layout structure of the switch circuit, each of the signal lines 16-1 to 16-4 and each of the control lines 18-1, 18-1X to 18-4, 18-4X have the same amount of coupling capacitance. Will have. In addition, since the arrangement of the two signal lines with respect to each of the video lines 17-1 to 17-N (output ends) is symmetric, the noise components on the two signal lines are canceled, so that they are adjacent to each other. There is also an advantage that it is less affected by noise of the video signal written through the signal line, and an image display with better image quality becomes possible.

  In the above embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. However, the present invention is not limited to this application example, and the electric The present invention can be applied to all display devices in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, such as an organic EL display device using organic EL (electro luminescence) elements as optical elements.

1 is a block diagram illustrating a schematic configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. It is a circuit diagram which shows an example of a circuit structure of a pixel (pixel circuit). It is a circuit diagram which shows a transfer switch. It is a circuit diagram which shows the circuit structure of the switch circuit in the active matrix type liquid crystal display device which concerns on this embodiment. It is a plane pattern figure which shows the layout of the switch circuit in the active matrix type liquid crystal display device which concerns on this embodiment. It is a circuit diagram which shows the circuit structure of the switch circuit which concerns on a prior art example. It is a plane pattern figure which shows the layout of the switch circuit which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12 ... Vertical drive circuit, 13 ... Switch circuit, 14 ... Display panel, 15, 15-1 to 15-m ... Scan line, 16, 16-1 to 16-n ... Signal line, 17- 1-17-N: Video line, 18-1-18-4 ... Control line, 20 ... Pixel, 21 ... TFT (pixel transistor), 22 ... Liquid crystal cell (liquid crystal capacitor), 23 ... Retention capacitor, 30, 30- 1-30-4 ... Transfer switch

Claims (5)

A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix on a substrate, and signal lines are wired for each column with respect to the matrix-like arrangement;
When the number of the signal lines is n, the output end is located between every two adjacent signal lines in units of N (N is an integer of 2 or more) for each of the n signal lines. A plurality of n / N video lines wired to
First and second switch means connected between each output end of the plurality of video lines and the two signal lines;
First and second control lines that are wired along the column direction of the matrix-like pixel array and transmit control signals for controlling the first and second switch means;
With
The first and second control lines are connected to the first and second switch means by connection wiring extending in the row direction from the first and second control lines, and the first and second control lines are connected to the first and second control lines via the connection wiring. And a display device for supplying the control signal to the second switch means. The display device according to claim 1, wherein the first and second switch means are transfer switches in which Nch transistors and Pch transistors formed in two stages in the row direction are connected in parallel. The display device according to claim 2, wherein the first and second switch means include an Nch transistor and a Pch transistor formed in the same stage with an output end of the video line interposed therebetween. Each of the first and second control lines includes a pair of wirings for controlling the Nch transistor and the Pch transistor,
The pair of wires, claim 3 Symbol mounting of the display device are arranged adjacent to each other in the row direction. 5. The display device according to claim 1, wherein the video line has an output end branched into a plurality of systems after intersecting the first and second control lines. 6.

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