JP4585964B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  The solid-state imaging device detects the electric charge accumulated in the photodiode as an electric signal by photoelectric conversion, and particularly comprises a cell and a signal detection circuit two-dimensionally arranged in a vertical direction and a horizontal direction on a semiconductor substrate. Is done.

  Conventionally, as a solid-state imaging device, a MOS type image sensor and a CCD (Charge coupled device) are known. In the MOS type image sensor, the signal charge converted in the photoelectric conversion region (photodiode) is amplified by the transistor. It is characterized by high sensitivity, low power consumption, and capable of single power supply operation. More specifically, the potential of the signal charge accumulation region is modulated by signal charges generated by photoelectric conversion. The amplification coefficient of the amplification transistor varies depending on its potential. In the case of the MOS type image sensor, since the amplification transistor is included in the pixel portion, a reduction in pixel size and an increase in the number of pixels are expected.

  Further, the MOS type image sensor has an advantage that various circuits can be easily incorporated on the same substrate. For example, peripheral circuits (register circuit, timing circuit), A / D (analog-digital) conversion circuit, command circuit, D / A (digital-analog) conversion circuit, DSP (Digital Signal Processor), and the like. Thus, low cost can be realized by incorporating a functional circuit on the same chip as the MOS type image sensor.

  FIG. 9 shows an example of a circuit schematic diagram of a MOS type image sensor. The image capturing area 10 is composed of a plurality of cells (11-1-1, 11-1-2... 11-3-3), and each cell is two-dimensionally arranged.

  Each cell 11 includes a photodiode 12 (12-1-1, 12-1-2, ... 12-3-3) which is a photoelectric conversion element, and a charge transfer transistor 13 (13-1-1, 13). -1-2, ... 13-3-3), a reset transistor 14 (14-1-1, 14-1-2, ... 14-3-3) for erasing charges, and amplification It comprises transistors 15 (15-1-1, 15-1-2,... 15-3-3). In this case, the photoelectric conversion region includes a photodiode 12 and a charge transfer transistor 13. In addition, the signal detection circuit area includes a reset transistor 14 and an amplification transistor 15.

  Peripheral circuit areas such as a horizontal shift register 21 and a vertical shift register 22 are arranged in the peripheral area of the image capturing area 10. The horizontal pixel selection wiring 24 and the reset wiring 23 select a horizontal cell position by the horizontal shift register 21. Further, the horizontal pixel selection wiring 24 is connected to the gate of each charge transfer transistor 13 in order to determine a line for reading signal charges. Further, the vertical voltage input transistor 28 is connected to the vertical signal line 26 in order to select the vertical cell position.

  Next, FIG. 10 and FIG. 11 are an example showing a top view and a cross-sectional configuration of a metal-oxide semiconductor (MOS) type solid-state imaging device which is one of the conventional solid-state imaging devices.

  The top view is shown in FIG. This consists of three areas. First, a charge transfer transistor including a photodiode 101, a transfer gate 103, and a detection capacitor 104, second, a reset transistor including a detection capacitor 104, a reset gate electrode 108, and a drain region 106; The amplifying transistor 105 includes a drain region 106, a source region 115, and an amplifying gate 114.

FIG. 11 shows a cross-sectional view thereof. FIG. 11A is a cross-sectional view taken along section AA ′ of FIG. On the semiconductor substrate 113, the photodiode 101, the transfer gate 103 composed of the transfer gate electrode of the transfer transistor that transfers the charge accumulated in the photodiode 101 by incident light and the gate insulating film 107, and the photodiode 101 A phototransistor region including a detection capacitor 104 that accumulates charges transferred via the transfer gate 103 is provided. Further, a reset transistor region having the gate electrode 108, the drain region 106, and the detection capacitor 104 as a source region is provided. Also included is an amplifying transistor 105 comprising a drain region 106, a gate electrode 114, and a source region 115. The gate insulating film is composed of a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), or the like. FIG. 11B is a cross-sectional view taken along a line BB ′ in FIG. Here, the channel width W under the gate is determined by the width of the region sandwiched between the element isolation regions 110.

  The operation principle is as follows. The light detected by the photodiode 101 is converted into electric charge, and the transfer gate 103 is turned on to move to the detection capacitor 104. Further, the charge accumulated in the detection capacitor 104 is moved to the amplification transistor 105 to perform signal amplification processing. Here, the reset gate electrode 108 completely removes the charge accumulated in the detection capacitor 104 before the charge accumulated in the photodiode 101 is moved to the detection capacitor 104 by turning on the transfer gate 103. Is formed. The charge can be completely moved to the drain region 106 by turning on the reset gate electrode 108 before moving the charge to the detection capacitor 104. Further, it is necessary to apply a positive voltage to the drain region 106 so that the voltage is higher than that of the detection capacitor 104. By doing so, it is possible to completely remove the carrier of the detection capacitor 104 when the incident signal is taken in.

Therefore, conventionally, efforts have been made to reduce the capacity of the detection capacitor unit in the solid-state imaging device (see, for example, Patent Document 1).
JP-A-5-291550

Normally, the signal accumulated in the detection capacitor unit 104 is read as the voltage Vfd,
Vfd = Qfd / Cfd
Represented as: Qfd is a charge accumulated in the detection capacitor unit 104 from the photodiode 101, and Cfd is a capacitance value of the detection capacitor unit 104. In the MOS type solid-state imaging device, pixel portions are arranged in an array, but in order to obtain a more detailed signal as an image, it is necessary to reduce the pixel cell size. If the cell size is reduced, the area of the photodiode is reduced, and the accumulated charge Qfd is reduced. Therefore, when Qfd is constant, Cfd needs to be reduced in order to increase Vfd.

  Conventionally, Cfd is substantially equivalent to Csub, and it is possible to reduce Cfd by reducing the area Sfd of the detection capacitor 104. Cfd is expressed as follows (see FIG. 12).

Csub = ε · Sfd / dfd
Cfd = Csub + Co + Cr + Cs + Cd

  Here, Csub is the capacitance between the detection capacitor 104 and the substrate 113, dfd is the distance between the detection capacitor 104 and the substrate 113, Cr is the capacitance between the detection capacitor 104 and the reset gate electrode 108, and Co is the detection capacitance. The capacitances Cs and Cd between the unit 104 and the transfer gate 103 are the capacitances between the detection capacitor unit 104 and the source 115 and the drain 106 of the amplification transistor 105.

  However, as the detection capacitor unit 104 is further miniaturized, not only Csub but other capacitance components cannot be relatively ignored, and Cfd cannot be easily reduced. In order to reduce the capacitance Cfd, for example, it is effective to reduce the capacitance Cr generated between the detection capacitance unit 104 and a reset transistor which is a transistor adjacent thereto. As a result, the charge-voltage conversion efficiency in the detection capacitor unit 104 can be increased.

In order to reduce the capacitance between the detection capacitor 104 and the reset transistor, the channel width W under the reset gate electrode 108 may be reduced. In short,
Cr = ε · Lr · W / (Lr / 2) = 2 · ε · W
It is expressed. Here, W is the channel width under the reset gate electrode 108, ε is the dielectric constant, and Lr is the gate length of the reset gate electrode 108. Usually, the channel width of the transistor is determined by the width of the activation region. The width (channel width) of the active region is almost determined by the resolution of the stepper used in the lithography process in the semiconductor manufacturing process, and it is difficult to make it smaller than 0.2 to 0.3 μm at present. .

  In order to solve the above-described conventional problems, an object of the present invention is to provide a semiconductor solid-state imaging device capable of reducing the capacitance Cfd of the detection capacitor unit and increasing the output voltage.

In order to achieve the above object, a solid-state imaging device of the present invention includes a photodiode that photoelectrically converts incident light into a signal charge on a semiconductor substrate, a transfer transistor that transfers the signal charge accumulated in the photodiode, A detection capacitor for storing the signal charge transferred by the transfer transistor; a reset transistor for discharging the signal charge stored in the detection capacitor to a drain; the photodiode; the transfer transistor; the detection capacitor ; An ion for supplying a carrier having a polarity opposite to that of the channel at least at a boundary between the channel under the gate electrode of the reset transistor and the groove element isolation. The seed has a structure in which the gate width of the reset transistor is the gate length Remote, characterized in that short.

  Here, it is preferable that the ion species supplying carriers having a polarity opposite to that of the channel is continuously distributed from under the gate electrode of the reset transistor to the detection capacitor portion or the drain.

  The effective gate width of the reset transistor is preferably 0.01 μm or more and 0.4 μm or less. In addition, the effective gate length of the reset transistor is preferably 0.1 μm or more and 1.0 μm or less.

  The solid-state imaging device according to the present invention further includes a carrier having a polarity opposite to that of the majority carrier of the photodiode at a boundary portion between an activation region forming the photodiode and an element isolation region regulating the activation region. It is characterized in that ionic species supplying the water are distributed.

  As described above, distribution of ion species having a charge opposite to that of the channel in the vicinity of the boundary between the activation region and the element isolation region limits the resolution limit of the stepper used in the lithography process. Therefore, the effective channel width can be further reduced with high accuracy. According to this means, the channel width can be reduced to about 0.01 to 0.1 μm.

  As a result, (1) it is possible to reduce the effective channel width of the reset transistor without increasing the number of steps as compared with the conventional method, and to increase the output voltage by reducing the capacitance of the detection capacitor section. Thus, a solid-state imaging device with high sensitivity and high image quality can be realized. (2) It is an extremely simple processing step, and an effect that it is suitable for mass production can be obtained.

  Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a top view of the solid-state imaging device according to Embodiment 1 of the present invention. The difference from the conventional example is that charges in the boundary region between the channel below the reset gate electrode 108 and the element isolation region 110 in FIG. Distribution of ion species (P-type or N-type) 111 having Other configurations are the same as those of the conventional configuration shown in FIGS.

  FIG. 2 shows a cross-sectional view. FIG. 2A corresponding to the A-A ′ sectional view of FIG. 1 is the same as the conventional embodiment. However, FIG. 2B corresponding to the BB ′ cross-sectional view of FIG. 1 differs from the conventional embodiment in that the ion species having a charge opposite in polarity to the carrier (electron or hole) of the channel is formed on the side wall of the element isolation region 110. 111 (P-type or N-type) is distributed.

  In general, the channel width of a transistor is determined by the width of an activation region sandwiched between element isolation regions. FIG. 1 shows a boundary line 100 between the activation region and the element isolation region. The area surrounded by the boundary line 100 is the activation area. As the channel width W under the reset gate electrode 108 is reduced, the capacitance value Cfd of the detection capacitor 104 can be reduced. FIG. 3 shows the reset transistor. As described above, the reset transistor includes the drain 106, the reset gate electrode 108, and the detection capacitor unit 104. 3A is a cross-sectional view taken along the line B-B ′ of FIG. 10 in the conventional embodiment, and FIG. 3B is a cross-sectional view taken along the line B-B ′ of FIG. 1 according to the present embodiment. As shown in FIG. 3A, when ions are not distributed near the sidewall of the element isolation region 110, the channel width W is determined by the width of the activation region 112. On the other hand, when ions (polarity opposite to the channel) 111 are distributed in the vicinity of the sidewall of the element isolation region 110 as shown in FIG. 3B, the channel width W is reduced. The reason is that in the region where the ions 111 are implanted, the potential of the conduction band is increased and the electron density is reduced.

  The advantages of this configuration will be described. The width of the activation region 112 is almost determined by the resolution of a reduction projection exposure apparatus (stepper) used in the lithography process in the semiconductor manufacturing process, and is reduced to about 0.2 to 0.3 μm in the current technology. It is difficult.

  Further, if the performance of the stepper is improved and the resolution is improved in the future, it is considered that processing of 0.2 μm or less is possible. However, in that case, damage to the substrate surface becomes a problem, and fluctuations in the channel width W are likely to occur, so that effective control of the channel width W is extremely difficult.

  On the other hand, in the configuration of this embodiment, ions 111 that supply carriers having a polarity opposite to that of the channel are distributed near the boundary between the activation region 112 and the element isolation region 110. This makes it possible to reduce the effective channel width W while reducing damage to the substrate surface.

  Further, the channel width of the transistor is effectively determined by the channel width under the gate electrode. This ion species is not distributed only in the boundary region overlapping the gate electrode 108 and the activation region. It is desirable to distribute as follows. In other words, it is desirable that the distribution be continuously performed not only under the reset gate electrode 108 but also from under the reset gate electrode 108 to the detection capacitor 104 or the drain region 106. The reason is that not only the channel length under the gate is reduced, but also the channel width of the drain and source regions is reduced, thereby further reducing the capacitance.

  Since the implantation type for forming the channel of the reset transistor is usually N-type, arsenic (As) is common. Therefore, the ion species 111 distributed near the boundary between the activation region 112 and the element isolation region 110 needs to be P-type ions, and boron (b) is generally used. It is desirable that the ion species 111 is distributed about 0.05 to 0.2 μm from the boundary. The reason is that if the distribution amount of P-type ions is too large, the channel width becomes extremely narrow, and even if the reset gate electrode 108 is turned on, it becomes difficult to move the carriers of the detection capacitor 104 to the drain region 106. Because. If the distribution is about 0.05 to 0.2 μm, it is possible to simultaneously reduce the channel width and remove the carrier of the detection capacitor 104. In this case, it is desirable that the width of the active region formed by the stepper is about 0.1 to 0.4 μm, and the gate width is 0.01 μm or more and 0.4 μm or less. In this region, the transistor capacitance is reduced, and the carrier removal of the detection capacitor 104 can be realized at the same time.

  As its manufacturing method, it is possible to apply a trench isolation structure normally used in the manufacturing method of a field effect transistor. As shown in FIG. 4, (a) a trench 117 is formed in a region serving as an element isolation portion in the region of the Si substrate 113, and (b) an ion 111 having a charge opposite in polarity to the carrier of the channel is formed in the trench 117. (C) an oxide film 110 is deposited, the surface of the substrate is planarized, and an element such as a gate electrode may be formed. In this method, it is possible to easily perform sidewall implantation (ion 111 implantation at the boundary between the activation region 112 and the element isolation region 110) while minimizing the number of additional steps.

  According to this manufacturing method, the above-described structure can be realized only by adding one ion implantation step to the normal trench isolation forming step. In this case, the damage given to the activation region (channel) 112 around the ion species 111 by the ion implantation can be recovered by performing heat treatment. The heat treatment temperature is desirably 700 to 900 ° C., and the time is desirably 10 to 120 minutes.

  Thus, by reducing the effective channel width, the capacity of the reset gate can be reduced, and miniaturization exceeding the limit of the lithography process becomes possible.

  According to the embodiment of the present application, the effective channel width can be reduced to about 0.1 μm. That is, the channel width is about ½ to ３ compared to the conventional form not using this method, and the capacitance between the detection capacitor 104 and the reset gate is also about ½ to ３. Can be reduced.

  If the capacitance of the detection capacitor unit 104 decreases, the amount of change in the output voltage when the charge transferred from the photodiode to the detection capacitor unit 104 is converted to a voltage increases. Thereby, the detection sensitivity can be improved and the S / N (signal-to-noise ratio) can be improved, so that the image of the MOS type solid-state imaging device can be improved.

  Here, the gate length is preferably as long as possible, and at least the gate width is preferably shorter than the gate length. The first reason is that if the gate length is increased, the variation in channel width is averaged, and the variation in characteristics of the reset transistors formed in each cell formed in an array can be reduced. Because. The second reason is that by increasing the gate length, the maximum applied voltage between the drain and the source of the reset transistor can be increased. When the reset gate is turned on, the detection capacitor section This is because the charge 104 can be easily removed.

  The gate length is preferably 0.1 μm or more and 1.0 μm or less. Below 0.1 μm, the gate length is too short, and it is difficult to obtain good transistor characteristics due to the hot channel effect and the like. Further, when the thickness is 1.0 μm or more, the capacitance of the detection capacitor unit 104 and the reset gate cannot be ignored with respect to the capacitance of the detection capacitor unit 104. As a result, the applied voltage to the detection capacitor unit 104 can be applied from 1 to 5V.

(Embodiment 2)
A top view and a cross-sectional view of the solid-state imaging device according to Embodiment 2 of the present invention are shown in FIGS. 5 and 6, respectively. In consideration of the reduction of the leakage current of the photodiode 101, at least in the vicinity of the boundary between the activation region and the element isolation region of the photodiode 101, ions having a polarity opposite to that of ions (usually N-type) that supply charges forming the photodiode 101 It is preferable to implant and distribute ions (usually P-type) that supply electric charges. Further, as shown in FIG. 5, continuously (that is, so as to surround the entire activation region in the unit cell), the reverse polarity to the ions (usually N-type) that supply charges forming the photodiode 101 and the channel. Ions (usually P-type) for supplying the charge may be implanted. FIG. 5 shows a boundary line 100 between the activation region and the element isolation region. The inside of the region surrounded by the boundary line 100 is an activated region, and the outside is an element isolation region.

  The difference between the second embodiment and the first embodiment is that a charge having a polarity opposite to that of an ion (usually N-type) that supplies the charge forming the photodiode 101 is formed near the boundary 100 between the activation region and the element isolation region. This is to distribute the supplied ions (usually P-type). Other configurations are the same as those in FIGS.

  If there is a leak current in the photodiode, charge is generated even without incident light, and an output signal is generated as if there was incident light. This becomes noise (white scratches). Normally, the channel of both the reset transistor and the photodiode is N-type, and it is the P-type ions that are distributed near the boundary between the activation region and the element isolation region of the photodiode. That is, it is preferable to distribute the ion species 111 of the same type as the P type as shown in FIG. 5 in the vicinity of the boundary between the activation region and the element isolation region of the photodiode.

  This is because the ions 111 can be distributed as shown in FIGS. 5 and 6 without increasing the number of processes by simultaneously performing the ion implantation in the manufacturing process. According to the above embodiment, noise can be reduced and image quality can be improved without increasing the number of steps.

(Embodiment 3)
FIG. 7 shows a top view of the solid-state imaging device according to Embodiment 3 of the present invention.

  In the second embodiment, the case where the photodiode 101 and the detection capacitor unit 104 are configured on a one-to-one basis has been described. On the other hand, in the third embodiment, the photodiode 101 and the detection capacitor 104 / reset transistor / amplification transistor are configured in a many-to-one relationship. In that case, the ratio is generally 2: 1 or 4: 1. When it is 2 to 1, it is called 2 pixels 1 cell, and when it is 4 to 1, it is called 4 pixels 1 cell. This many-to-one configuration has an advantage that the area of the photodiode 101 is increased because the area occupied by the transistor is smaller than that of the normal one-to-one configuration.

  In the third embodiment, as in the first and second embodiments, the photodiode 101 is located near the boundary 100 between the photodiode 101 and the element isolation region, and near the boundary 100 between the transistor channel and the element isolation region. The ionic species supplying a carrier having a polarity opposite to that of the majority carrier is distributed. By doing so, it is possible to reduce white scratches in the photodiode 101 and at the same time reduce the capacitance of the detection capacitor unit 104. There is also an effect that it can be realized without increasing the number of manufacturing steps.

(Embodiment 4)
FIG. 8 shows a top view of the solid-state imaging device according to Embodiment 4 of the present invention.

  The fourth embodiment is different from the third embodiment in that the detection capacitor 104 / reset transistor / amplification transistor is separated without sharing the drain / source. By doing so, it is possible to increase the degree of freedom in the arrangement of the photodiode 101 / transistor.

  Also in this case, a carrier having a polarity opposite to the majority carrier of the photodiode 101 is supplied near the boundary 100 between the photodiode 101 and the element isolation region, and near the boundary 100 between the transistor channel and the element isolation region. Distribute ion species. By doing so, as in the third embodiment, it is possible to reduce white defects of the photodiode 101 and at the same time reduce the capacitance of the detection capacitor unit 104.

  The present invention is particularly suitable for a miniaturized MOS type solid-state imaging device and a camera including the solid-state imaging device, and is provided in a high-sensitivity and high-quality image sensor, a digital still camera, a camera-equipped mobile phone, and a notebook computer. Suitable for cameras and camera units connected to information processing equipment.

FIG. 1 is a structural diagram (top view) of a solid-state imaging device according to Embodiment 1 of the present invention. FIG. 2A is a structural diagram (cross-sectional view) of the solid-state imaging device according to Embodiment 1 of the present invention. FIG. 2B is a structural diagram (sectional view) of the solid-state imaging device according to Embodiment 1 of the present invention. FIG. 3A is an explanatory diagram regarding the channel width reduction of a transistor. FIG. 3B is an explanatory diagram regarding the channel width reduction of the transistor. FIG. 4A shows a method for manufacturing the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 4B shows a method for manufacturing the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 4C is a method for manufacturing the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 5 is a structural diagram (top view) of the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 6A is a structural diagram (cross-sectional view) of a solid-state imaging device according to Embodiment 2 of the present invention. FIG. 6B is a structural diagram (cross-sectional view) of the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 7 is a structural diagram (top view) of a solid-state imaging device according to Embodiment 3 of the present invention. FIG. 8 is a structural diagram (top view) of a solid-state imaging device according to Embodiment 4 of the present invention. FIG. 9 is a configuration diagram of a conventional solid-state imaging device. FIG. 10 is a structural diagram (top view) of a conventional solid-state imaging device. FIG. 11A is a structural diagram (cross-sectional view) of a conventional solid-state imaging device. FIG. 11B is a structural diagram (sectional view) of a conventional solid-state imaging device. FIG. 12 is an explanatory diagram regarding the capacity of the detection capacity unit of the solid-state imaging device.

Explanation of symbols

10 Signal Extraction Regions 12-1-1 to 12-3-3 Photodiodes 13-1-1 to 13-3-3 Charge Transfer Transistors 14-1-1 to 14-3-3 Amplifying Transistors 15-1-1-1 15-3-3 reset transistor 21 horizontal shift register 22 vertical shift register 23-1 to 3 reset wiring 24-1 to 3 horizontal pixel selection wiring 25-1 to 3 current stabilizing transistor 26-1 to 3 vertical signal wiring 28-1 -3 Voltage input transistor 100 Boundary line 101 between activation region and element isolation region Photodiode 102 Wiring 103 Transfer gate electrode 104 Detection capacitor 105 Charge amplification transistor 106 Drain region 107 Gate insulating film 108 Reset gate electrode 109 Silicon insulating film 110 Element isolation region 111 ions (ion species)
112 Activation region 113 Semiconductor substrate (Si substrate)
114 Gate electrode (charge amplification transistor)
115 source region (charge amplification transistor)
116 Silicon Insulating Film 117 Trench

Claims (6)

A photodiode that photoelectrically converts incident light into signal charge on a semiconductor substrate, a transfer transistor that transfers signal charge accumulated in the photodiode, and a detection capacitor that accumulates signal charge transferred by the transfer transistor, A reset transistor for discharging the signal charge accumulated in the detection capacitor portion to a drain, and a trench type element isolation surrounding an active region of the photodiode, the transfer transistor, the detection capacitor portion, and the reset transistor. ,
At least at the boundary between the channel under the gate electrode of the reset transistor and the groove element isolation, there is a structure in which ion species supplying carriers having a polarity opposite to that of the channel is distributed, and the gate width of the reset transistor is A solid-state imaging device characterized by being shorter than a gate length.   2. The solid-state imaging device according to claim 1, wherein ion species that supply carriers having a polarity opposite to that of the channel are continuously distributed from below the gate electrode of the reset transistor to the detection capacitor or the drain.   The solid-state imaging device according to claim 1, wherein an effective gate width of the reset transistor is 0.01 μm or more and 0.4 μm or less.   The solid-state imaging device according to claim 1, wherein an effective gate length of the reset transistor is 0.1 μm or more and 1.0 μm or less.   Further, ion species supplying carriers having a polarity opposite to that of majority carriers of the photodiode are distributed at the boundary between the activation region forming the photodiode and the element isolation region for regulating the activation region. The solid-state imaging device according to claim 1. Further, continuously with the ion species distributed at the boundary between the activation region that forms the photodiode and the element isolation region that regulates the activation region, on the side wall of the channel under the gate electrode of the reset transistor, 6. The solid-state imaging device according to claim 5, wherein ion species supplying carriers having a polarity opposite to that of the channel are distributed.

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