JP4561328B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device such as a CCD (Charge Coupled Device) sensor or a CMOS (complementary MOS) sensor, and a manufacturing method thereof.

  In a solid-state imaging device such as a CCD or a CMOS sensor, a substrate structure in which an n-type epitaxial layer is stacked on an n-type semiconductor substrate or a substrate structure in which a p-type epitaxial layer is stacked on a p-type semiconductor substrate is generally used. . In the CCD sensor, the former substrate structure is often used, and in the CMOS sensor, the latter substrate structure is often employed.

  In a CCD sensor, a substrate structure in which an n-type epitaxial layer is stacked on an n-type semiconductor substrate is often used. When a vertical overflow drain is to be realized, the semiconductor substrate itself may be n-type. This is because it is a premise. In a CMOS sensor, a substrate structure in which an n-type epitaxial layer is stacked on an n-type semiconductor substrate may be employed in order to suppress blooming during high-luminance subject imaging.

  FIG. 8 is a cross-sectional view of a conventional solid-state imaging device using an n-type semiconductor substrate.

An n-type epitaxial layer 102 is formed on the n-type semiconductor substrate 101, and a p-type well 103 is formed in the n-type epitaxial layer 102. The p-type well 103 is formed with a CCD sensor or an image sensor constituting a CMOS sensor. A p ⁺ contact region 104 is formed in the p-type well 103, and a terminal 105 connected to the p ⁺ contact region 104 is formed. An n ⁺ contact region 106 is formed in the n-type epitaxial layer 102, and a terminal 107 connected to the n ⁺ contact region 106 is formed.

  In the solid-state imaging device described above, the terminal 105 formed on the surface side is fixed to the ground potential GND, and the substrate voltage Vsub is applied between the terminal 105 and the terminal 107, whereby the p-type well 103 and the n-type semiconductor substrate. A reverse bias can be easily applied to the terminal 101. The overflow barrier is controlled by controlling the substrate voltage Vsub in the range of about 6 to 12V. Further, the substrate voltage Vsub is controlled to about 20 V at the time of the electronic shutter. As described above, in the above substrate configuration, the voltage between the p-type well 103 and the n-type semiconductor substrate 101 can be easily and appropriately controlled from the surface side.

  Patent Document 1 discloses a substrate structure in which a p-type epitaxial layer 112 is formed on an n-type semiconductor substrate 111 as shown in FIG. 9, but this substrate structure is not actually used. The reason for this will be described.

  When the p-type epitaxial layer 112 is fixed to the ground potential GND and the substrate voltage Vsub is applied between the p-type epitaxial layer 112 and the n-type semiconductor substrate 111, the p-type epitaxial layer 112, the n-type semiconductor substrate 111, The depletion layer 113 generated between the layers extends to the chip end face F. Since the chip end surface F has more defects than the inside of the substrate, when the depletion layer 113 extends to the chip end surface F, a very large leakage current is generated at the chip end surface F. For this reason, an appropriate reverse bias cannot be applied between the p-type epitaxial layer 112 and the n-type semiconductor substrate 111, and wasteful power consumption occurs due to a leakage current.

  In the substrate structure shown in FIG. 9, no voltage can be applied to the n-type semiconductor substrate 111 and the p-type epitaxial layer 112 from the front side. For this reason, it is necessary to form a terminal on the back side of the n-type semiconductor substrate 111. Usually, on the back surface of the n-type semiconductor substrate 111, there are various films deposited simultaneously with the process on the front surface side. Therefore, it is necessary to newly add a cleaning process for removing these unnecessary films. Process cost increases. In addition, it is necessary to change the package structure, which increases the package cost.

  From the above situation, conventionally, as shown in FIG. 8, a p-type well 103 is formed in an n-type epitaxial layer 102 formed on an n-type semiconductor substrate 101, and an imaging element is formed in the p-type well 103. Yes. In this structure, since the pn junction between the p-type well 103 and the n-type epitaxial layer 102 does not exist on the chip end face F, the above problem does not occur. In addition, the substrate voltage Vsub can be applied using the terminals formed on the front surface side. For the same reason, a substrate structure in which an n-type epitaxial layer is formed on a p-type semiconductor substrate is not adopted, and a substrate structure in which a p-type epitaxial layer is formed on a p-type semiconductor substrate is often used.

By the way, when an n-type semiconductor substrate is used, an n-type region is formed as a sensor portion in the p-type well 103 formed in the n-type epitaxial layer 102, and a p-type channel is formed between the sensor portions. A stopper is formed. The channel stopper is provided in order to prevent color mixing by preventing inflow and outflow of signal electrons between adjacent sensor portions.
JP-A 62-16565

  However, as pixels become finer, it is becoming difficult to prevent color mixing. This is because the area between the pixels becomes very narrow, and the width of the channel stopper formed between the pixels also becomes narrow. As a measure for preventing color mixing, forming the channel stopper deeply can be raised. For this purpose, there is a problem that the number of times of ion implantation is increased and a high energy ion implantation apparatus capable of performing deep ion implantation is required, resulting in an increase in cost.

  This is because, when a substrate structure having the n-type epitaxial layer 102 on the n-type semiconductor substrate 101 is employed, it is necessary to inject an amount of p-type impurity to cancel the n-type of the n-type epitaxial layer 102. This is because it becomes difficult to produce a concentration and deep p-type channel stopper.

  Therefore, from the viewpoint of easily preventing color mixing, it is preferable to use a substrate structure in which a p-type epitaxial layer is formed on an n-type semiconductor substrate. However, when epitaxial layers having different polarities are formed on a semiconductor substrate, there is a problem that a leak current is generated on the chip end face F described above. Similarly, for example, when holes are used as signal charges, it may be preferable in terms of device characteristics to use a substrate structure in which n-type epitaxial is formed on a p-type semiconductor substrate.

  The present invention has been made in view of the above circumstances, and its object is to have a substrate structure in which an epitaxial layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and to be generated on a chip end face. An object of the present invention is to provide a solid-state imaging device and a method for manufacturing the same that can suppress leakage current.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a first conductive type semiconductor substrate, a second conductive type epitaxial layer formed on the semiconductor substrate, and an imaging formed on the epitaxial layer. An element portion; a buried electrode embedded in the epitaxial layer so as to surround the imaging element portion; and a first conductivity type semiconductor formed in the epitaxial layer around the buried electrode and electrically connected to the semiconductor substrate And having a layer.

In the solid-state imaging device of the present invention, the inner epitaxial layer surrounded by the buried electrode and the outer epitaxial layer surrounded by the buried electrode and the first conductivity type semiconductor layer formed in the epitaxial layer so as to surround the imaging element portion. The layers are electrically separated.
The embedded electrode is electrically connected to the first conductivity type semiconductor substrate via the first conductivity type semiconductor layer. Therefore, when a substrate voltage is applied between the buried electrode and the inner epitaxial layer, the substrate voltage is applied between the epitaxial layer and the semiconductor substrate. Here, since the epitaxial layer outside the buried electrode is in an electrically floating state, no voltage is applied between the outer epitaxial layer and the semiconductor substrate.

  In order to achieve the above object, a method for manufacturing a solid-state imaging device according to the present invention includes a step of forming a second conductivity type epitaxial layer on a first conductivity type semiconductor substrate, and an imaging element region in the epitaxial layer. Forming a trench surrounding the first conductive type impurity in the trench, and forming a buried electrode containing a first conductivity type impurity in the trench, and heat-treating the first conductivity type impurity in the buried electrode on the inner wall of the trench by heat treatment. Forming a first conductive type semiconductor layer that is diffused in a layer and electrically connected to the semiconductor substrate; and forming an image sensor in the image sensor region of the epitaxial layer.

  In the manufacturing method of the solid-state imaging device of the present invention described above, after forming the groove surrounding the imaging element region in the epitaxial layer, the embedded electrode containing the first conductivity type impurity is formed in the groove, and heat treatment is performed in the embedded electrode. By diffusing the first conductivity type impurity in the epitaxial layer on the inner wall of the groove, the epitaxial layer inside the groove and the epitaxial layer outside are electrically separated, and the buried electrode is electrically connected to the semiconductor substrate. Is manufactured.

  According to the solid-state imaging device and the method of manufacturing the same of the present invention, it has a substrate structure in which an epitaxial layer of the second conductivity type is formed on the semiconductor substrate of the first conductivity type, and suppresses leakage current generated at the chip end face. It is possible to realize a solid-state imaging device that can do this.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  FIG. 1 is a schematic cross-sectional view of a solid-state imaging device according to this embodiment. FIG. 2 is a plan view of the solid-state imaging device according to the present embodiment.

For example, an n ⁺ semiconductor layer 2 containing n-type impurities at a higher concentration than the n-type semiconductor substrate 1 and having a lower resistance than the n-type semiconductor substrate 1 is formed on the n-type semiconductor substrate 1 made of an n-type silicon wafer. ing. The n ⁺ semiconductor layer 2 is provided so that the substrate voltage Vsub is applied to the entire chip with a small time constant. The n ⁺ semiconductor layer 2 also has the purpose of reducing the influence on the sensor sensitivity due to uneven concentration of n-type impurities in the n-type semiconductor substrate 1 and reducing the electronic shutter voltage.

A p-type epitaxial layer 3 made of p-type epitaxial silicon is formed on the n ⁺ semiconductor layer 2. A buried electrode 4 is formed in the p-type epitaxial layer 3 so as to surround the imaging element region Ar. The buried electrode 4 is, for example, polysilicon or amorphous silicon containing n-type impurities (phosphorus (P) or arsenic (As)) at a high concentration.

An n ⁺ diffusion layer 5 is formed in the p-type epitaxial layer 3 around the buried electrode 4, that is, in a portion adjacent to the buried electrode 4. The n ⁺ diffusion layer 5 is formed to a depth that surrounds the imaging element region Ar and reaches the n ⁺ semiconductor layer 2. The n ⁺ diffusion layer 5 may be formed to a depth that reaches the n-type semiconductor substrate 1 through the n ⁺ semiconductor layer 2.

The p-type epitaxial layer 3 is electrically separated into an inner p-type epitaxial layer 3a and an outer p-type epitaxial layer 3b by the embedded electrode 4 and the n ⁺ diffusion layer 5 surrounding the imaging element region Ar. The diffusion width d of the n ⁺ diffusion layer 5 with the embedded electrode 4 as the center is, for example, 0.5 μm to 1 μm.

  A p-type well 6 is formed in the inner p-type epitaxial layer 3a as necessary. An image sensor portion is formed in the p-type well 6 in the image sensor region Ar. The image sensor section has a sensor section and a transfer register in the case of a CCD sensor, and has a sensor section and a transistor section in the case of a CMOS sensor.

A p ⁺ contact region 7 is formed in the p-type well 6. The p ⁺ contact region 7 is provided so that the entire inner p-type well 6 and p-type epitaxial layer 3a are biased with a small time constant. In the example illustrated in FIG. 2, the p ⁺ contact region 7 is formed so as to surround the inner region, but may be interrupted and is not particularly limited.

An insulating film 8 made of a silicon oxide film or the like is formed on the p-type epitaxial layer 3. A terminal 9 connected to the p ⁺ contact region 7 is formed in the insulating film 8. The terminal 9 may be formed at least at one point on the p ⁺ contact region 7.

  A terminal 10 connected to the buried electrode 4 is formed on the insulating film 8. The terminal 10 should just be formed in at least one place.

  The terminal 9 is fixed to the ground potential GND, and the substrate voltage Vsub is applied between the terminal 9 and the terminal 10. In the present embodiment, the substrate voltage Vsub is supplied using the terminals 9 and 10 formed on the surface side (one surface side) of the n-type semiconductor substrate 1. The substrate voltage Vsub at the time of imaging is, for example, 6 to 12V, and the substrate voltage Vsub at the time of the electronic shutter is about 20V.

  FIG. 3 is a cross-sectional view of the main part of the image pickup element portion formed in the inner p-type epitaxial layer 3a. FIG. 3 shows a cross-sectional structure of a CCD sensor as an example, but a CMOS sensor may be used.

An n-type semiconductor region 21 is formed in the p-type well 6 in the region of the sensor unit 20, and a p ⁺ semiconductor region 22 is formed on the surface of the n-type semiconductor region 21. Since the p ⁺ semiconductor region 22 is formed on the surface, the sensor unit 20 composed of a buried photodiode with reduced dark current is configured. Although not shown, a plurality of sensor units 20 are arranged in a matrix.

  A p-type well 23 is formed on both sides of the n-type semiconductor region 21, and a transfer channel 24 composed of an n-type region is formed in the p-type well 23.

  A p-type region between the n-type semiconductor region 21 and the transfer channel 24 on one side (right side in the figure) transfers the signal charges (electrons in this example) accumulated in the n-type semiconductor region 21 of the sensor unit 20. 24 becomes a read gate region 25 for reading to 24. A channel stopper 26 containing a p-type impurity at a high concentration is formed between the n-type semiconductor region 21 and the transfer channel 24 on the other side (left side in the drawing).

  A transfer electrode 27 is formed on the transfer channel 24 via an insulating film 8. The transfer electrode 27 is made of, for example, polysilicon.

  Although not shown, a light shielding film that covers the transfer electrode 27 and opens the sensor unit 20 is formed, and an inner lens, a color filter, and an on-chip lens are formed in an upper layer as necessary.

  In the solid-state imaging device, the terminal 9 is fixed to the ground potential GND, and the substrate voltage Vsub is applied between the terminal 9 and the terminal 10. In the present embodiment, the substrate voltage Vsub is supplied using the terminals 9 and 10 formed on the surface side (one surface side) of the n-type semiconductor substrate 1. The substrate voltage Vsub at the time of imaging is, for example, 6 to 12V, and the substrate voltage Vsub at the time of the electronic shutter is about 20V.

The embedded electrode 4 and the n ⁺ diffusion layer 5 electrically isolate the inner p-type epitaxial layer 3a and the outer p-type epitaxial layer 3b. Since the embedded electrode 4 is electrically connected to the n ⁺ semiconductor layer 2 via the n ⁺ diffusion layer 5, the substrate voltage Vsub is applied between the terminal 9 and the terminal 10 to thereby form the inner p A reverse bias is applied between the type epitaxial layer 3 a and the n ⁺ semiconductor layer 2 below it. Since the outer p-type epitaxial layer 3 b is in an electrically floating state, it remains at a potential approximately equal to the potential of the n ⁺ semiconductor layer 2 and the n-type semiconductor substrate 1.

Thus, since no reverse bias is applied between the outer p-type epitaxial layer 3b and the n-type semiconductor substrate 1 and the n ⁺ semiconductor layer 2, the depletion layer does not extend. Therefore, a leakage current generated between the p-type epitaxial layer 3b outside the chip end face F and the n-type semiconductor substrate 1 can be suppressed.

  In the present embodiment, since the substrate voltage Vsub can be applied using the terminal 9 formed on the surface of the p-type epitaxial layer 3 and the terminal 10, it is necessary to provide a substrate voltage application terminal on the back surface of the n-type semiconductor substrate 1. There is no. For this reason, process cost and package cost are not increased.

  This is because, on the back surface of the n-type semiconductor substrate 1, various films deposited simultaneously with the process on the front surface side are usually present. This is because it is necessary to newly add a cleaning process for removing unnecessary films. It is also necessary to change the package structure.

  Also, compared with the case where the image pickup element portion is formed in the n-type epitaxial layer, the problem is caused in particular in a solid-state image pickup device having a small pixel of 2 μm or less by forming the image pickup element portion in the p-type epitaxial layer. Color mixing can be suppressed.

Further, by interposing an n ⁺ semiconductor layer 2 having a low resistance if necessary between the n-type semiconductor substrate 1 and the p-type epitaxial layer 3, the substrate voltage Vsub can be applied to the entire chip with a small time constant. For this reason, a high-speed electronic shutter operation can be realized. In addition, the influence on the sensor sensitivity due to the uneven concentration of the n-type impurity in the n-type semiconductor substrate 1 can be reduced, and the electronic shutter voltage can also be reduced.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 4A, an n ⁺ semiconductor layer 2 is formed on an n-type semiconductor substrate 1. The n ⁺ semiconductor layer 2 is formed using, for example, an epitaxial growth method in which an n ⁺ epitaxial layer is formed on the n-type semiconductor substrate 1 even if an ion implantation method in which an n-type impurity is implanted into the surface of the n-type semiconductor substrate 1 is used. Also good.

Next, as shown in FIG. 4B, a p-type epitaxial layer 3 is formed on the n ⁺ semiconductor layer 2 by an epitaxial growth method. In the case of a general visible light solid-state imaging device, a p-type epitaxial layer 3 having a p-type impurity concentration of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ and a thickness of several μm to several tens μm is used. Form.

Next, as shown in FIG. 5A, a groove M surrounding the entire image sensor region Ar is formed. For example, after forming an etching mask having a pattern exposing a portion to be the groove M on the p-type epitaxial layer 3 by using a lithography technique, the groove M is formed by dry etching the p-type epitaxial layer 3. The trench M is formed with a depth that allows the n ⁺ diffusion layer 5 to be formed later to reach the n ⁺ semiconductor layer 2.

Next, as shown in FIG. 5B, for example, polysilicon or amorphous silicon containing n-type impurities at a high concentration (for example, 1 × 10 ¹⁹ cm ⁻³ or more) is buried in the trench M, A buried electrode 4 is formed. For example, after polysilicon or amorphous silicon containing n-type impurities is deposited on the p-type epitaxial layer 3 so as to fill the trench M, unnecessary polysilicon or amorphous silicon on the p-type epitaxial layer 3 is entirely etched or CMP is performed. The embedded electrode 4 is formed by removing by the above.

Next, as shown in FIG. 6A, heat treatment is performed to diffuse phosphorus (p) or arsenic (As), which are n-type impurities in the buried electrode 4, and n ^{+ is formed on} the inner wall of the trench M. A diffusion layer 5 is formed. By the buried electrode 4 and the n ⁺ diffusion layer 5, the p-type epitaxial layer 3 is electrically separated into an inner p-type epitaxial layer 3a and an outer p-type epitaxial layer 3b.

  Next, as shown in FIG. 6B, a p-type well 6 is formed in the inner p-type epitaxial layer 3a by ion implantation as necessary. In the subsequent steps, the sensor portion and the terminal are formed, but the order of the steps is not limited.

That is, as shown in FIG. 7A, an image sensor constituting a CCD sensor or a CMOS sensor is formed in the inner p-type epitaxial layer 3a. For example, in the case of a CCD sensor, various semiconductor regions shown in FIG. 3 are formed by ion implantation, the insulating film 8 is formed, and the transfer electrode 27 is formed. Further, a p ⁺ contact region 7 is formed in the p-type well 6, and a terminal 9 connected to the p ⁺ contact region 7 is formed.

  Then, as shown in FIG. 7B, a terminal 10 connected to the embedded electrode 4 is formed.

  After passing through the above steps, although not shown, the chip of the solid-state imaging device is obtained by cutting into individual solid-state imaging devices.

  According to the manufacturing method of the solid-state imaging device according to the above-described embodiment, the inner p-type epitaxial layer 3a where the imaging element unit is formed and the outer p-type epitaxial layer 3b can be electrically separated. In addition, a substrate structure in which leakage current is suppressed can be manufactured.

  Since the imaging element portion can be formed in the inner p-type epitaxial layer 3a formed on the n-type semiconductor substrate 1, the number of ion implantations for forming the p-type channel stopper 26 can be reduced. A high energy ion implantation apparatus for ion implantation at a deep position becomes unnecessary.

  Therefore, a solid-state imaging device with a small pixel size and suppressed color mixture can be manufactured at low cost.

The present invention is not limited to the description of the above embodiment.
In this embodiment, the example using the substrate structure in which the p-type epitaxial layer 3 is formed on the n-type semiconductor substrate 1 has been described. However, the substrate structure in which the n-type epitaxial layer is formed on the p-type semiconductor substrate is used. Also good. In this case, the polarities of various semiconductor regions may be reversed. For example, polysilicon or amorphous silicon containing boron which is a p-type impurity may be used as the embedded electrode 4.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a schematic sectional drawing of the solid-state imaging device concerning this embodiment. It is a top view of the solid-state imaging device concerning this embodiment. It is principal part sectional drawing of the image pick-up element part formed in a p-type epitaxial layer. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is sectional drawing of the solid-state imaging device which concerns on a prior art example. It is a figure for demonstrating the problem of the solid-state imaging device concerning a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate (1st conductivity type semiconductor substrate), 2 ... n ⁺ semiconductor layer (high concentration semiconductor layer), 3 ... p-type epitaxial layer (2nd conductivity type epitaxial layer), 3a ... inner p Type epitaxial layer, 3b ... outside p type epitaxial layer, 4 ... embedded electrode, 5 ... n ⁺ diffusion layer (first conductivity type semiconductor layer), 6 ... p type well, 7 ... p ⁺ contact region, 8 ... insulating film , 9 ... Terminal, 10 ... Terminal, 20 ... Sensor part, 21 ... n-type semiconductor region, 22 ... p ⁺ semiconductor region, 23 ... p-type well, 24 ... Transfer channel, 25 ... Read gate region 25, 26 ... Channel stopper 26, 27 ... transfer electrodes, 101 ... n-type semiconductor substrate, 102 ... n type epitaxial layer, 103 ... p-type well, 104 ... ^{p +} contact region, 105 ... terminal, 106 ... ^{n +} contact region 107 ... Child, 111 ... n-type semiconductor substrate, 112 ... p-type epitaxial layer, 113 ... depletion layer, F ... tip end face, Ar ... imaging element region, M ... groove, Vsub ... substrate voltage, GND ... ground potential

Claims (5)

A first conductivity type semiconductor substrate;
An epitaxial layer of a second conductivity type formed on the semiconductor substrate;
An image sensor section formed in the epitaxial layer;
A buried electrode containing a first conductivity type impurity buried in the epitaxial layer so as to surround the imaging element portion;
A solid-state imaging device comprising: a first conductivity type semiconductor layer formed in the epitaxial layer around the embedded electrode and electrically connected to the semiconductor substrate. A high-concentration semiconductor layer of a first conductivity type formed between the semiconductor substrate and the epitaxial layer and having a higher impurity concentration of the first conductivity type than the semiconductor substrate;
The solid-state imaging device according to claim 1, wherein the first conductivity type semiconductor layer is formed to a depth reaching the high-concentration semiconductor layer. The solid-state imaging device according to claim 1, further comprising a voltage application terminal connected to the embedded electrode. Forming a second conductivity type epitaxial layer on the first conductivity type semiconductor substrate;
Forming a groove surrounding the imaging element region in the epitaxial layer;
Forming a buried electrode containing a first conductivity type impurity in the trench;
Diffusing the first conductivity type impurity in the buried electrode into the epitaxial layer on the inner wall of the trench by heat treatment to form a first conductivity type semiconductor layer electrically connected to the semiconductor substrate;
And a step of forming an image sensor in the image sensor region of the epitaxial layer. Before the step of forming the epitaxial layer, further comprising the step of forming a first conductivity type high concentration semiconductor layer having a first conductivity type impurity concentration higher than that of the semiconductor substrate on the semiconductor substrate;
5. The method of manufacturing a solid-state imaging device according to claim 4, wherein in the step of forming the groove, the groove is formed to a depth that allows the first conductive semiconductor layer to be formed later to reach the high-concentration semiconductor layer.

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