JP4542201B2 - Manufacturing method of coreless wiring board - Google Patents

Description

The present invention relates to a method for manufacturing a coreless wiring board.

  In recent years, electronic components such as IC chips and LSIs have been rapidly integrated due to the demand for higher functionality and lighter, thinner and smaller electronic devices. Furthermore, higher density wiring and multi-terminals are required. Recently, as such a package substrate, a coreless wiring substrate having no core substrate has been proposed (Patent Document 1, etc.). The coreless wiring board mainly consists of a build-up layer that can be made into a high-density wiring in which dielectric layers and conductor layers made of resin materials (polymer materials) are alternately formed. The wiring length is shortened to support high frequency applications.

JP 2004-186265 A

  By the way, the electronic component and the wiring board are flip-chip connected via joints called solder bumps, and in the gap (around the solder bumps), in order to improve the thermal fatigue life of the solder bumps, An underfill material made of a curable resin is filled and formed. Here, in order to satisfactorily fill and form the underfill material without generating voids or the like, the flowability of the underfill material on the surface of the wiring board (the surface of the solder resist layer) is important. Therefore, conventionally, when removing resin residue in the opening of the solder resist layer in desmear treatment (potassium permanganate, etc.), the surface of the solder resist layer is simultaneously roughened to improve the flowability of the underfill material. Attempts have been made.

  However, it is very cumbersome to simultaneously control (two-way management) the surface roughness of the solder resist layer and the removal of the resin residue on the bottom of the opening by the desmear process. Further, in the desmear treatment, there is a problem that the efficiency of the solder resist layer surface is not sufficiently obtained compared with the effect of removing the resin residue, and thus the efficiency is poor. Another problem is that the desmear treatment conditions must be changed depending on the material of the solder resist layer.

The present invention has been made in view of the above problems, and provides a method for manufacturing a coreless wiring board suitable for obtaining a wiring board in which the surface of the board is easily roughened and the flowability of the underfill material is good. The purpose is to provide.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the method of manufacturing the coreless wiring board of the present invention includes:
A method of manufacturing a coreless wiring board in which dielectric layers and conductor layers made of a resin material are alternately laminated without having a core board ,
A step of preparing a reinforcing substrate with a metal foil in which a peelable metal foil having a metal roughening treatment on its surface is arranged on the reinforcing substrate;
A first sheet forming step of forming a first resin sheet to be a first dielectric layer forming one main surface of the wiring board in a form surrounding the metal foil;
A laminated sheet body forming step of alternately laminating metal patterns and resin sheets on the first resin sheet to obtain a laminated sheet body including a wiring laminated portion to be a wiring board on the metal foil,
A peripheral part cutting step of cutting the laminated sheet body together with the reinforcing substrate along the boundary between the wiring laminated part and the peripheral part and removing the peripheral part,
A separation step of separating the wiring laminated portion and the reinforcing substrate;
Removing the metal foil adhering to the wiring laminated portion and exposing the roughened surface of the first dielectric layer formed to a surface roughness corresponding to the roughened surface of the metal foil;
Are included in this order.
In this case, in the step of preparing the reinforcing substrate with metal foil, the metal foil subjected to the metal roughening treatment can be arranged so as to be in close contact with the semi-cured base resin sheet.
Moreover, the roughened surface of metal foil can also be made into 5 micrometers or more and 15 micrometers or less by the 10-point average roughness (Rz) prescribed | regulated to JIS-B-0601.
In addition, after the metal foil removing step, the method includes a step of forming an opening in the first dielectric layer and a desmearing step of removing a resin residue at the bottom of the opening of the opening, and the surface roughness on the roughened surface of the metal foil Correspondingly, the surface roughness of the roughened surface of the first dielectric layer may be set to 5 μm or more and 15 μm or less in terms of the ten-point average roughness (Rz) defined in JIS-B-0601.
Furthermore, it is possible to provide a step of removing the peripheral portion of the laminated sheet body to expose the outer edge of the metal foil.
Furthermore, the metal foil constitutes a metal foil adhesion body in which two copper foils are adhered to each other through metal plating, and in the separation step, by peeling at the interface between one and the other of the copper foil, The wiring laminated part which is an area | region on the metal foil close_contact | adherence body in a lamination sheet body can also be made to provide the process of isolate | separating from a reinforcement board | substrate in the state in which one side of copper foil adhered.

According to this, the 1st resin sheet which should become the 1st dielectric layer which makes one main surface of a coreless wiring board is formed on the metal foil of the reinforcement board with metal foil by which the metal roughening process was performed on the surface. As a result (first sheet forming step), an anchor was formed between the first resin sheet and the metal foil, and the surface of the first dielectric layer exposed by removing the metal foil in the metal foil removing step was roughened. It will be a thing. Therefore, the roughened surface of the first dielectric layer can be easily obtained, and as a result, a coreless wiring board with good underfill material flowability can be obtained. In addition, since the surface of the metal foil is roughened, the adhesion between the first resin sheet or the reinforcing substrate with metal foil and the metal foil is improved by the anchor effect, and the laminated sheet body is formed well. There is also an effect that can be done.

Further, after the metal foil removing step, for example , when performing a step of forming an opening in the first dielectric layer by a laser and a desmear step of removing the resin residue at the bottom of the opening, in the desmear step, the first dielectric There is no need for the purpose of surface roughening of the layer, and only the removal of the resin residue at the bottom of the opening is sufficient. That is, it is not necessary to control the surface roughness of the first dielectric layer and the removal of the resin residue at the bottom of the opening at the same time, and process management becomes easy. In this case, the surface roughness of the first dielectric layer is substantially determined by the surface-roughened metal foil . In the desmear process for removing the resin residue at the bottom of the opening, the first dielectric layer Although the surface of the film is somewhat roughened, the roughness is hardly changed.

The principal part enlarged view of the coreless wiring board of this invention. The figure showing the manufacturing process of the coreless wiring board of this invention. The figure following FIG. The figure following FIG. The figure following FIG. The figure following FIG. Schematic of the coreless wiring board (with stiffener) of the present invention.

<Coreless wiring board>
An embodiment of a coreless wiring board according to the present invention will be described with reference to the drawings. FIG. 1 is an enlarged view of a main part schematically showing a cross-sectional structure of the coreless wiring board 1. The coreless wiring substrate 1 is mainly composed of a wiring laminated portion L in which dielectric layers B1 to B5 and conductor layers M1 to M4 are alternately laminated.

  The conductor layers M1 to M4 are composed of wirings 22 and 24 and pads 21 and 25 made of Cu plating. The surfaces of the pads 21 and 25 are Ni-Au plated. The conductor layers M1 to M4 are connected to each other by vias 23, whereby a conduction path (for signal, power supply, and ground) from the pad 21 to the pad 25 is formed.

  The dielectric layers B1 to B5 are mainly made of a polymer material such as an epoxy resin, and appropriately include an inorganic filler such as silica powder that adjusts the dielectric constant and withstand voltage. Among these, the dielectric layers B2 to B4 are called build-up resin insulation layers and via layers, insulate the conductor layers M1 to M4, and have vias 23 formed therethrough for interlayer connection. On the other hand, the dielectric layers B1 and B5 are called solder resist layers, and openings 11a and 13a for exposing the pads 21 and 25 are formed. The dielectric layers B2 to B4 are made of, for example, a polymer material 12 having a Young's modulus lower than that of the polymer materials 11 and 13 of the dielectric layers B1 and B5 in order to relieve stress generated in the wiring laminated portion L. Can be used.

  A main surface MP1 formed by the first dielectric layer B1 is a mounting surface for an electronic component such as an IC chip or LSI, and a solder bump 9 (Sn / Pb) for flip-chip connecting the electronic component to the pad 21. Etc.) are formed. On the other hand, the back surface MP2 formed by the fifth dielectric layer B5 is used as a connection surface to the external substrate, and the pad 25 is used as a back surface land for connection to the external substrate by a ball grid array (BGA) or the like.

  As shown in FIG. 7, in the coreless wiring substrate 1 configured as described above, a metal reinforcing frame (stiffener) ST is bonded to the main surface MP1 so as to surround the central solder bump 9. The inside of the stiffener ST is an electronic component mounting portion CS. The electronic component is flip-chip connected to the solder bump 9, and a gap between the electronic component and the main surface MP1 (around the solder bump 9) is made of epoxy resin containing glass filler. An electronic device is configured by filling and forming an underfill material.

  The surface of the first dielectric layer (solder resist layer) B1 that forms the main surface MP1 of the coreless wiring substrate 1 has sufficient roughness so that the flowability of the underfill material is good. It has become. Specifically, the arithmetic mean roughness (Ra) specified in JIS-B-0601 is 0.5 μm or more (preferably 0.7 μm or more) and 1.5 μm or less (preferably 1.1 μm or less). It is said. Alternatively, the ten-point average roughness (Rz) specified in JIS-B-0601 is about 5 μm or more (preferably 8 μm or more) and 15 μm or less (preferably 11 μm or less). Below this range, the flowability of the underfill material may be poor and voids may be generated. Further, the adhesion between the underfill material and the first dielectric layer (solder resist layer) B1 is deteriorated. On the other hand, if it exceeds this range, a plating sag defect occurs during Ni / Au plating. Further, the flowability of the underfill material becomes excessive, and the filling property may be deteriorated.

<Manufacturing method of coreless wiring board>
An embodiment of a method for manufacturing a coreless wiring board according to the present invention will be described with reference to the drawings. 2 to 6 are process diagrams showing the manufacturing process of the coreless wiring board 1. This manufacturing method will be briefly described. By forming the laminated sheet body SS (wiring laminated portion L) on the reinforcing substrate 3 by a well-known build-up method, and then peeling the wiring laminated portion L from the reinforcing substrate 3. It is easy to manufacture. Moreover, since the wiring laminated portion L can be formed on both surfaces of the reinforcing substrate 3 at the same time, mass production is easy. Hereinafter, each step will be described in detail.

(1) Step 1
In the base sheet forming step, as shown in FIG. 2, a base resin sheet 31 is formed on the reinforcing substrate 3 for reinforcement during manufacturing. Although the reinforcement board | substrate 3 is not specifically limited, For example, a heat resistant resin board (for example, bismaleimide-triazine resin board), a fiber reinforced resin board (for example, glass fiber reinforced epoxy resin), etc. can be used. In addition, the base resin sheet 31 is mainly made of a polymer material such as an epoxy resin, and is formed on the main surface of the reinforcing substrate 3 by vacuum lamination, like other resin sheets S1 to S5 described later. Although only one main surface of the reinforcing substrate 3 is shown in FIG. 2, the base resin sheet 31 is formed on both surfaces of the reinforcing substrate 3 in this step.

(2) Step 2
In the adhesion metal foil arrangement step, as shown in FIG. 2, the adhesion Cu foil 4 is arranged on the base resin sheet 31 so as to be included in the main surface 31 a. The contact Cu foil 4 is one in which two Cu foils 4a and 4b are in close contact via, for example, Cr thin plating and can be peeled off. Further, the surface of the contact Cu foil 4 is roughened by Cu roughening treatment. The Cu roughening treatment can be performed using, for example, a roughening agent containing an inorganic acid and a copper oxidizing agent. Such surface roughened adhesion Cu foil 4 can be obtained by subjecting adhesion Cu foil (before roughening) to Cu roughening treatment before this step (metal roughening treatment step). .

  In addition, the surface roughness of the adhesion Cu foil 4 subjected to the Cu roughening treatment is important for determining the surface roughness of the first dielectric layer (solder resist layer) B1 of the coreless wiring substrate 1 as described later. Specifically, the ten-point average roughness (Rz) specified in JIS-B-0601 is about 5 μm or more (preferably 8 μm or more) and 15 μm or less (preferably 11 μm or less). Below this range, the surface roughness of the first dielectric layer B1 becomes insufficient, and the flowability of the underfill material becomes poor, which may cause voids and the like. Further, the adhesion between the underfill material and the first dielectric layer (solder resist layer) B1 is deteriorated. On the other hand, if it exceeds this range, a plating sag defect occurs during Ni / Au plating. Further, the flowability of the underfill material becomes excessive, and the filling property may be deteriorated.

  Moreover, it is preferable to arrange | position the contact | adherence Cu foil 4 in the state in which the base resin sheet 31 is semi-hardened. That is, the surface-roughened contact Cu foil 4 can be brought into close contact with the semi-cured base resin sheet 31 to obtain an anchor effect, and the contact Cu foil 4 is not peeled off from the base resin sheet 31 in the subsequent steps. The laminated sheet body SS (wiring laminated portion L) can be obtained satisfactorily.

(3) Process 3
In the first sheet forming step, as shown in FIG. 2, the first resin sheet S <b> 1 is formed so as to surround the close contact Cu foil 4, and the close contact Cu foil 4 is formed between the first resin sheet S <b> 1 and the base resin sheet 31. Is sealed. Here, the first resin sheet S1 includes a portion to be the first dielectric layer B1 forming the main surface MP1 of the coreless wiring substrate 1 on the contact Cu foil 4. The first resin sheet S1 is formed by vacuum lamination. Thus, the adhesion Cu foil 4 is sealed between the first resin sheet S1 and the base resin sheet 31, and the first resin sheet S1 adheres closely to the adhesion Cu foil 4 whose surface is roughened (anchor effect). ), The laminated sheet body SS (wiring laminated portion L) can be satisfactorily obtained without the adhesion Cu foil 4 being peeled off from the first resin sheet S1 and the base resin sheet 31 in the subsequent steps.

(4) Step 4
In the laminated sheet body forming step, as shown in FIG. 3, metal patterns (conductor layers M1 to M4) and resin sheets S2 to S5 (including dielectric layers B2 to B5) are alternately laminated on the first resin sheet S1. Thus, a laminated sheet body SS is obtained. Such lamination of the metal pattern and the resin sheet can be performed by a known build-up method (build-up is performed on both surfaces of the reinforcing substrate 3). The laminated sheet SS obtained as a result includes the wiring laminated portion L to be the coreless wiring substrate 1 on the adhesive Cu foil 4. Further, the upper surface of the laminated sheet SS corresponds to the rear surface MP2 of the coreless wiring substrate 1, the opening 13a is formed in the fifth resin sheet S5, and the pad 25 is exposed inside. In addition, the wiring lamination | stacking part L is comprised as what arranged the block used as the coreless wiring board 1 in multiple numbers.

(5) Process 5
In the peripheral part cutting step, as shown in FIG. 4, the multilayer sheet body SS is cut together with the reinforcing substrate 3 along the boundary V between the wiring laminated part L and the peripheral part E, and the peripheral part E is removed. The boundary V exists along the outer edge of the adhesive Cu foil 4 (or inside thereof), and when the peripheral portion E is removed by cutting, the boundary Cu foil 4 sealed by the first resin sheet S1 is removed. An outer edge (a new outer edge when the outer edge is removed) appears. That is, since the contact portion between the first resin sheet S1 and the base resin sheet 31 is lost by removing the peripheral portion E, the wiring laminated portion L and the reinforcing substrate 3 (and the base resin sheet 31) are in close contact with each other in the stacking direction. It will be in the state connected via 4 only.

(6) Step 6
In the peeling process, as shown in FIG. 5, the wiring laminated portion L and the reinforcing substrate 3 are peeled off at the interface between the close contact Cu foil 4 (the interface between the Cu foil 4a and the Cu foil 4b). According to the manufacturing method as described above, the step (step 4) of forming the laminated sheet body SS that requires adhesion to the reinforcing substrate 3, and the wiring laminated portion L that requires ease of peeling from the reinforcing substrate 3. Since both of the peeling step (step 6) can be carried out satisfactorily, the production is easy.

(7) Step 7
In the metal foil removing step, as shown in FIG. 6, the Cu foil 4a adhering to the wiring laminated portion L is removed to expose the first dielectric layer B1. The removal of the Cu foil 4a is performed by chemical etching using, for example, a hydrogen peroxide-sulfuric acid based etching solution. Here, since the surface of the Cu foil 4a that is in close contact with the first dielectric layer B1 is subjected to the roughening treatment as described above, the surface (main surface) of the first dielectric layer B1 that appears when the Cu foil 4a is removed. MP1) also has sufficient roughness. Specifically, the surface roughness of the first dielectric layer B1 after this step is 0.5 μm or more (preferably 0.7 μm or more) in terms of arithmetic average roughness (Ra) specified in JIS-B-0601. .About.5 μm or less (preferably 1.1 μm or less). Alternatively, the ten-point average roughness (Rz) specified in JIS-B-0601 is about 5 μm or more (preferably 8 μm or more) and 15 μm or less (preferably 11 μm or less). If it falls below this range, the flowability of the underfill material on the main surface MP1 of the coreless wiring board 1 after manufacture may be poor, and voids may be generated. Further, the adhesion between the underfill material and the first dielectric layer (solder resist layer) B1 is deteriorated. On the other hand, if it exceeds this range, a plating sag defect occurs during Ni / Au plating. Further, the flowability of the underfill material becomes excessive, and the filling property may be deteriorated.

(8) Step 8
In the laser opening step, as shown in FIG. 6, an opening 11a is formed in the first dielectric layer B1 by laser. The opening 11a is formed at a position corresponding to the pad 21 formed under the first dielectric layer B1, and the pad 21 is exposed at the bottom. A CO ₂ laser, a UV laser, a YAG laser, or the like is used for forming the opening 11a using such a laser.

(9) Step 9
In the desmear process, the resin residue (smear) on the bottom of the opening 11a (the surface of the pad 21) is removed. The desmear treatment is performed with a chemical solution such as potassium permanganate or O ₂ plasma. Here, as described above, the surface (main surface MP1) of the first dielectric layer B1 that appears when the Cu foil 4a is removed in the step 7 (metal foil removing step) has sufficient roughness. In the desmear process, there is no need for the purpose of roughening the surface of the first dielectric layer B1, but only for the purpose of removing the smear on the surface of the pad 21. That is, it is not necessary to control the surface roughness of the first dielectric layer B1 and the removal of the smear in the opening 11a at the same time by the desmear process, thereby facilitating process management. In the desmear process for removing smear on the surface of the pad 21, the surface of the first dielectric layer B1 is somewhat roughened, but the surface roughness of the first dielectric layer B1 is almost changed before and after this step. do not do.

(10) Post-process After the desmear process (process 9), Ni-Au plating is performed on the surfaces of the pads 21 and 25. Then, the wiring laminated portion L is cut for each block to be the coreless wiring substrate 1, and solder bumps 9 (Sn / Pb or the like) are formed on the pads 21. Thereafter, the stiffener ST is bonded to the main surface MP1, and after undergoing predetermined inspection such as electrical inspection and appearance inspection, the coreless wiring substrate 100 shown in FIG. 7 is completed.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, In the range which does not lose the identity with the invention embodied in these, it can change suitably.

DESCRIPTION OF SYMBOLS 1 Coreless wiring board B1-B5 Dielectric layer M1-M4 Conductor layer 3 Reinforcement board 4 Adhesive metal foil 31 Base resin sheet S1 1st resin sheet S1-S5 Resin sheet SS Laminated sheet body L Wiring laminated part E Surrounding part ST Stiffener
100 Coreless wiring board (with stiffener)

Claims (6)

A method of manufacturing a coreless wiring board in which dielectric layers and conductor layers made of a resin material are alternately laminated without having a core board ,
A step of preparing a reinforcing substrate with a metal foil in which a peelable metal foil having a metal roughening treatment on its surface is arranged on the reinforcing substrate;
A first sheet forming step of forming a first resin sheet to be a first dielectric layer forming one main surface of the wiring board in a form surrounding the metal foil;
A laminated sheet body forming step of alternately laminating metal patterns and resin sheets on the first resin sheet to obtain a laminated sheet body including a wiring laminated portion to be the wiring board on the metal foil;
A peripheral part cutting step of cutting the laminated sheet body together with the reinforcing substrate along a boundary between the wiring laminated part and the peripheral part, and removing the peripheral part;
A separation step of separating the wiring laminated portion and the reinforcing substrate;
Metal foil removal that removes the metal foil adhering to the wiring laminate and exposes the roughened surface of the first dielectric layer formed to a surface roughness corresponding to the roughened surface of the metal foil Process,
In this order. A method for manufacturing a coreless wiring board. The method of manufacturing a coreless wiring board according to claim 1, further comprising:
In the step of preparing the metal foil reinforcing substrate, producing the metallic foil metal roughening treatment has been performed, the coreless wiring board being arranged so as to be in intimate contact with the ground resin sheet in a semi-cured state Method. The coreless wiring board manufacturing method according to claim 1, further comprising:
The method for producing a coreless wiring board, wherein the roughened surface of the metal foil has a 10-point average roughness (Rz) specified in JIS-B-0601 of 5 μm or more and 15 μm or less. The method of manufacturing a coreless wiring board according to claim 3, further comprising:
A step of forming an opening in the first dielectric layer after the metal foil removing step;
A desmear process for removing resin residue at the bottom of the opening;
Including
Corresponding to the surface roughness on the roughened surface of the metal foil, the surface roughness on the roughened surface of the first dielectric layer is 5 μm or more in terms of the 10-point average roughness (Rz) specified in JIS-B-0601. A method for manufacturing a coreless wiring board, wherein the coreless wiring board is 15 μm or less. The coreless wiring board manufacturing method according to any one of claims 1 to 4, further comprising:
A method of manufacturing a coreless wiring board, comprising: removing a peripheral portion of the laminated sheet body to expose an outer edge of the metal foil. The coreless wiring board manufacturing method according to claim 5, further comprising:
The metal foil constitutes a metal foil adhesion body in which two copper foils are adhered to each other through metal plating, and in the separation step, the metal foil is peeled off at the interface between one and the other of the copper foil. , manufacture of coreless wiring board characterized in that it comprises the step of separating the wiring laminate portion is a region on the metal foil adhesion body in the laminated sheet from the reinforcing substrate while is attached state of the copper foil Method.