JP4539001B2 - Power MOS transistor control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device for a power MOS transistor.
[0002]
[Prior art]
An example of a conventional power MOS transistor control device is shown in FIG. In FIG. 9, a power MOS transistor 50 and a load 51 are connected in series to a power supply Vcc, and the power MOS transistor 50 is PWM-controlled by a pulse wave generation circuit 52 and a non-inverting amplifier circuit 53 so that a predetermined current i is supplied to the load 51. It can flow. However, if this is done, there is a problem in that the current i flowing through the load 51 changes greatly when the power MOS transistor 50 is switched, resulting in large noise. This is because the time change di / dt of the current is proportional to the amount of noise. As a countermeasure, instead of the pulse current waveform of FIG. 10A, the current at the time of PWM control is tilted as shown in FIG. 10B to reduce the current fluctuation di / dt with respect to time and reduce the noise. Has been proposed. As a circuit configuration, a trapezoidal waveform voltage is output from a trapezoidal wave generation circuit instead of the pulse wave generation circuit 52 of FIG. A voltage similar to this waveform is applied to the load 51, and the conduction current i of the load 51 is a value obtained by dividing this voltage by the load resistance. Therefore, when the load resistance is constant, it is possible to output a current similar to the waveform created by the trapezoidal wave generation circuit.
[0003]
However, in the case of a load such as a lamp in which a current that is ten times the normal current flows at the moment of lighting, the load resistance at the time of lighting is very low, so that there is a problem that a very large current gradient occurs and noise is generated. In view of this, Japanese Patent Application Laid-Open No. 2000-138570 proposes a method of controlling with current instead of load voltage.
[0004]
However, when such a method is adopted, as shown in FIG. 11, since the current gradient di / dt takes a certain constant value (di / dt) const, the maximum load current imax is affected by fluctuations in load resistance and power supply voltage. Changes (imax1> imax2), and the time T during which the current i is inclined changes. Specifically, when the load current is large, the slope time T (= T1) becomes long, and when the load current is small, the slope time T (= T2) becomes short. In this case, since the current gradient di / dt is constant, the amount of noise is constant.
[0005]
Here, attention is paid to the time T when the current i is inclined. If the slope di / dt with respect to time of current is small, noise is reduced, but there is a demerit that heat generation of the power MOS transistor is increased. This is due to the following reason. Normally, the power MOS transistor is used in a linear region (non-saturated region). In this linear region, the gate-source voltage is large and the drain-source voltage is small. On the other hand, while the current i is inclined, the T uses the saturation region of the power MOS transistor. In this saturation region, the gate-source voltage is small, the drain-source voltage is large, and it is consumed more than the linear region. The power increases, and the heat generation of the power MOS transistor increases.
[0006]
Therefore, a control for minimizing the noise within a range where the noise is below a certain value and the heat generation does not increase is considered.
At this time, in the case of a load in which a current that is 10 times the normal current when the lamp is turned on, an upper limit value (di / dt) max of the gradient with respect to the current time is set, and the current gradient is controlled during lighting, Reduce noise. When the load resistance value of the lamp rises and the current value decreases, control is performed to keep the current slope time constant. By adopting this control, the slope of the current with respect to time in the small current region can be further reduced as compared with Japanese Patent Laid-Open No. 2000-138570, and noise can be reduced. Further, since the current value is reduced, it is not necessary to consider the increase in heat generation.
[0007]
In introducing the control as described above, it is necessary to control the inclination time to be constant. As a simple method for detecting the tilt time, a circuit configuration shown in FIG. 12 can be considered. In FIG. 12, a voltage difference (corresponding to a current flowing through the resistor 60) at both terminals of the current detection resistor 60 is detected, amplified by the differential amplifier circuit 61, differentiated by the differentiation circuit 62, and voltage detection circuits 63, 64 are detected. The time when the current is tilted is detected by comparing the magnitude of the current change.
[0008]
However, since the current detection resistor 60 of FIG. 12 has a very small resistance value of several tens of mΩ, if a noise of about several tens of mV is applied to the input of the differentiation circuit 62, a large output voltage is generated in the differentiation circuit 62 and erroneous detection is performed. There is a drawback that it is easy to do.
[0009]
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object thereof is to provide a control device for a power MOS transistor capable of suppressing noise and heat generation with a novel configuration.
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, when a voltage is applied to the gate terminal of the power MOS transistor, a pulse-shaped current having a rising edge and a falling edge flows to the load. Here, the gate-source voltage of the power MOS transistor accompanying the voltage application to the gate terminal of the power MOS transistor is detected by the gate-source voltage detection means. Then, the feedback means obtains the deviation between the rise and fall times and the target value in the current waveform of the current load from the gate-source voltage of the power MOS transistor by the gate-source voltage detection means, The power MOS transistor is feedback controlled so as to eliminate the deviation.
[0011]
In this way, even if the resistance value of the load changes as the load is driven, the rise and fall current gradients in the load energization current waveform are set to a predetermined value or less and the rise and fall times are set to a predetermined value. The following can be achieved, and noise and heat generation can be suppressed.
[0012]
Further, the rise and fall times of energization current waveform This time the load, as determined by measuring the duration of the saturation region in transistor characteristics, in particular, as claimed in claim 2, the first The comparison means compares the detected gate-source voltage with a first judgment value between the off-time voltage and the threshold voltage, and also detects the detected gate-source voltage by the second comparison means. The first judgment value and the second judgment value are compared with the second judgment value between the threshold voltage and the on-time voltage, and based on the comparison result by the first and second comparison means by the timing means. If the continuation time is measured as the continuation time of the saturation region in the transistor characteristics, the time during which the current is inclined can be easily detected. In the case of the circuit configuration of FIG. 12, if noise of about several tens of mV is applied to the input of the differentiating circuit 62, a large output voltage is generated in the differentiating circuit 62 and is easily misdetected. Because no differentiation circuit is used, there is no false detection.
[0013]
According to a third aspect of the present invention, the power MOS transistor may be feedback controlled so that the rise time is constant and the fall time is constant.
[0014]
Further, as described in claim 4 , it is more preferable that the load is a lamp.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration of a power MOS transistor control device in the present embodiment.
[0016]
In FIG. 1, a power MOS transistor 1 and a load 2 are connected in series to a power supply Vcc. The load 2 is a lamp. A gate voltage control circuit 3 is connected to the gate terminal of the power MOS transistor 1. A control logic 4 is connected to the gate voltage control circuit 3. A trapezoidal wave is output from the gate voltage control circuit 3 to the gate terminal of the power MOS transistor 1 according to a command from the control logic 4, and the power MOS transistor 1 is PWM-controlled by this signal to flow a predetermined current i to the load 2. Can do.
[0017]
FIG. 2 shows a specific configuration of the gate voltage control circuit 3. In FIG. 2, the gate voltage control circuit 3 includes constant current circuits 31 and 32, a switch 33, a capacitor 34, bipolar transistors 35 and 36, and resistors 37, 38 and 39. When the load is driven (when the lamp is lit), the switch 33 is open, the transistor 36 is turned on, and the transistor 35 is turned on when the capacitor 34 is charged by the constant current circuit 31. From this state, when the drive of the load is stopped (when the lamp is extinguished), the switch 33 is closed, and the capacitor 34 is discharged through the constant current circuit 32. The waveform at this time falls in an oblique shape. Then, the transistor 35 is turned off. On the other hand, when the load is driven from the discharge state of the capacitor 34, the switch 33 is opened, and the capacitor 34 is charged by the constant current circuit 31. The waveform at this time rises obliquely. Then, the transistor 35 is turned on. In this way, a trapezoidal wave is generated.
[0018]
Further, a gate-source voltage detection circuit 5 as a gate-source voltage detection means is connected to the gate-source terminal of the power MOS transistor 1 in FIG. It is possible to detect the gate-source voltage Vgs of the power MOS transistor 1 due to the voltage application. The gate-source voltage detection circuit 5 includes a differential amplifier 6 and resistors 7, 8, 9, and 10. A series circuit including resistors 7 and 8 is connected between the gate terminal of the power MOS transistor 1 and the ground, and a point a between both resistors is connected to a non-inverting input terminal of the differential amplifier 6. The inverting input terminal of the differential amplifier 6 is connected to the source terminal of the power MOS transistor 1 through the resistor 8. The differential amplifier 6 is negatively fed back via a resistor 10. In the differential amplifier 6, the difference between the gate voltage and the source voltage of the power MOS transistor 1 is amplified and output.
[0019]
The output terminal of the differential amplifier 6 of the gate-source voltage detection circuit 5 is connected to the inverting input terminal of the comparator 12 of the voltage detection circuit 11 and to the inverting input terminal of the comparator 14 of the voltage detection circuit 13. Yes. A reference power supply 15 is connected to the non-inverting input terminal of the comparator 12, and a reference power supply 16 is connected to the non-inverting input terminal of the comparator 14. The voltage value at the reference power supply 15 corresponds to 1/2 (= Vt / 2) of the threshold voltage Vt as a comparison value with respect to the gate-source voltage Vgs, and the voltage value at the reference power supply 16 corresponds to the gate-source voltage Vgs. The comparison value corresponds to 4 volts.
[0020]
Further, the output terminals of the comparators 12 and 14 are connected to the control logic 4.
Next, the operation of the power MOS transistor control device will be described.
[0021]
The operation will be described using the time chart of FIG. FIG. 3 shows the energization current i of the power MOS transistor, the gate-source voltage Vgs, and the outputs of the comparators 12 and 14 from the top.
[0022]
The control logic 4 shown in FIG. 1 applies a voltage to the gate terminal of the power MOS transistor 1 through the gate voltage control circuit 3 to form a pulse shape with rising and falling slopes as shown in FIG. Current i. That is, the rising edge is oblique in the period from t1 to t2, and the falling edge is oblique in the period from t3 to t4. At this time, with respect to the gate-source voltage Vgs in the power MOS transistor 1 in FIG. 3, the gate-source voltage Vgs is 0 volt when the power MOS transistor 1 shown in the period up to t1 in FIG. . In addition, the gate-source voltage Vgs is in the vicinity of the threshold voltage Vt of the power MOS transistor 1 when the current shown in the periods t1 to t2 and t3 to t4 in FIG. During the period in which this current is tilted, the operating region of the power MOS transistor 1 is a saturation region, the gate-source voltage is small, and the drain-source voltage is large. Furthermore, a large voltage of 5 to 10 volts is applied to the gate-source voltage Vgs when the switch is on during the period from t2 to t3 in FIG. During a period in which this current is constant, the linear region (unsaturated region) of the power MOS transistor 1 is used, and the gate-source voltage is large and the drain-source voltage is small.
[0023]
The gate-source voltage Vgs is amplified by the differential amplifier 6 shown in FIG. Then, in the voltage detection circuit 11 (comparator 12) and the voltage detection circuit 13 (comparator 14), the gate-source voltage Vgs is compared with 1/2 of the threshold voltage Vt (= Vt / 2) and 4 volts. The voltage detection circuit 11 (comparator 12) and the voltage detection circuit 13 (comparator 14) compare the Vgs value with the boundary determination value (Vt / 2 or 4 volts) to obtain the saturation region of the MOS transistor in FIG. And the non-saturation region can be detected. Thereby, the control logic 4 detects the time during which the current is inclined (Tup, Tdown in FIG. 3).
[0024]
Specifically, the rise time (Tup in FIG. 3) during which the current at the time of turning on the power MOS transistor 1 is controlled to be 1 in the voltage detection circuit 11 where the Vgs value is 1 of the threshold voltage Vt of the power MOS transistor 1. It is detected as a time from exceeding / 2 (= Vt / 2) to exceeding 4 volts (an intermediate value of the gate-source voltage at which the power MOS transistor 1 can be sufficiently turned on) in the voltage detection circuit 13. Further, after the fall time (Tdown in FIG. 3) for controlling the slope of the current when turning off the power MOS transistor 1 falls below 4 volts in the voltage detection circuit 13, Vt in the voltage detection circuit 11 It is detected as the time until it becomes / 2.
[0025]
In this way, the rising and falling times Tup and Tdown in the current waveform of the current load 2 are obtained by measuring the duration of the saturation region in the transistor characteristics. The voltage detection circuit 11 serving as the comparison means compares the detected gate-source voltage Vgs with the first determination value between the off-time voltage and the threshold voltage, and detects the voltage as the second comparison means. The circuit 13 compares the detected gate-source voltage Vgs with a second determination value between the threshold voltage and the on-time voltage, and further controls the voltage detection circuit 11, Based on the comparison result of 13, the duration between the first judgment value and the second judgment value is measured as the duration of the saturation region in the transistor characteristics. In this way, it is possible to easily detect the time during which the current is inclined.
[0026]
Further, the control logic 4 in FIG. 1 as feedback means obtains the deviation between the rise and fall times Tup, Tdown and the target value in the current-carrying current waveform of the load 2, and the power MOS transistor so as to eliminate the deviation. 1 is feedback controlled.
[0027]
An example of a specific circuit configuration for this purpose is shown in FIG. FIG. 6 is a time chart for explaining the operation.
In FIG. 5, the output signal A from the voltage detection circuit 11 is input to the NAND gate 42 via the inverter 41, and the output signal B from the voltage detection circuit 13 is input to the NAND gate 42. An output signal of the NAND gate 42 is directly input to the NAND latch circuit 43 and also input to the NAND latch circuit 43 via the 200 μs generation circuit 44. Further, the output signal of the NAND latch circuit 43 is input to the AND gate 48 via the inverter 46 and also input to the exclusive OR circuit 45 and the AND gate 47. Further, the output signal of the above-described NAND gate 42 is input to the exclusive OR circuit 45. The output signal of the exclusive OR circuit 45 is input to AND gates 47 and 48, and the output signals of the AND gates 47 and 48 are an α signal and a β signal.
[0028]
With such a circuit configuration, as shown in FIG. 6, the output (point C voltage) of the NAND gate 42 is at the L level from the falling edge of the signal A to the falling edge of the signal B. In synchronization with the fall of the output of the NAND gate 42 (the fall of the signal A), a 200 μs pulse that is a reference time is generated in the 200 μs generation circuit 44 (see the voltage at the point D). Sent. When the time T from the fall of the signal A to the fall of the signal B is longer than 200 μs, the L level α signal is output, and when the time T is shorter than 200 μs, the L level β signal is output. A signal is output.
[0029]
The duration of the L level in the α and β signals reflects the deviation between the rise and fall times Tup and Tdown and the target value in the current-carrying current waveform of the load 2, and the signals α and β Thus, the currents in the constant current circuits 31 and 32 of the gate voltage control circuit 3 in FIG. 2 are controlled, and the rise time Tup and the fall time Tdown in the current-carrying current waveform of the load 2 become 200 μs which is the reference time. Thus, the power MOS transistor 1 is feedback controlled. Specifically, the currents in the constant current circuits 31 and 32 are increased or decreased, that is, the charge / discharge speed of the capacitor 34 in FIG. That is, when the rise / fall times Tup and Tdown are shorter than the reference time of 200 μs, the gate voltage control circuit 3 outputs an output that reduces the current gradient. Conversely, when the rise / fall times Tup and Tdown are longer than the reference time of 200 μs, the gate voltage control circuit 3 outputs an output that increases the current gradient.
[0030]
Specifically, when a lamp is used as the load 2, the driving is started at t10 as shown in FIG. In the period up to t11, the lamp resistance is small. During this period, the current change per time di / dt is increased as shown in FIG. Further, the lamp resistance is large after t12 in FIG. During this period, as shown in FIG. 8C, the current change per time di / dt is made very small. Further, in the transition period from t11 to t12 in FIG. 7, di / dt is set to an intermediate value as shown in FIG. 8B.
[0031]
As a result, during the period when the lamp resistance shown in FIG. 8A is low, the period when the lamp resistance shown in FIG. 8B is an intermediate value, and the period when the lamp resistance shown in FIG. Start up / down control. At this time, as shown in FIG. 8A, in the period when the lamp resistance is small, by setting di / dt to be equal to or less than a predetermined value, noise can be reduced to a certain level and heat generation can also be suppressed to a certain level. . Further, as shown in FIG. 8C, noise can be extremely reduced by reducing di / dt during a period when the lamp resistance is large. Further, since the current value is small, it is not necessary to consider heat generation. Furthermore, as shown in FIG. 8B, noise can be reduced by setting di / dt to an intermediate level during a period in which the lamp resistance is an intermediate value.
[0032]
By the control as described above, it is possible to perform the control so that the time during which the current is inclined (rise / fall time) Tup and Tdown are set to a fixed time. That is, the power MOS transistor is feedback controlled so that the rise time is constant and the fall time is constant.
[0033]
Further, since the differentiating circuit 62 in FIG. 12 is not employed, even when noise of about several tens of mV is applied to the power MOS transistor 1, the signal is not amplified and there is no fear of malfunction. That is, in the case of the circuit configuration of FIG. 12, if noise of about several tens of mV is applied to the input of the differentiating circuit 62, a large output voltage is generated in the differentiating circuit 62 and is likely to be erroneously detected. Since no resistors or differentiating circuits are used, there is no false detection.
[0034]
As described so far, when the rising and falling edges are inclined in the pulse-shaped current as the load current waveform (when the current is inclined), the saturation region of the power MOS transistor is used and the pulse Focusing on the fact that the linear region (non-saturated region) of the power MOS transistor is used when making the current constant in the shape current, the rise in the current waveform of the load 2 from the gate-source voltage Vgs of the power MOS transistor Further, the portion where the fall is oblique is obtained as the duration of the operation region of the power MOS transistor 1 (saturation region in transistor characteristics). This method is more accurate and easier than the case where the rise time and the fall time in the energization current waveform are obtained from the temporal change of the energization current of the load 2 (in the case of FIG. 12). When a pulse-shaped current with rising and falling slopes is applied to the load 2, the noise can be reduced to a certain value or less by controlling the slope of the current, and the current flowing through the load 2 The rise time and the fall time can be controlled to suppress heat generation due to the energization of the load. Therefore, even if the resistance value of the load 2 changes as the load 2 is driven, the rising and falling current slopes in the current-carrying current waveform of the load 2 are set to a predetermined value or less and the rising and falling times are set to a predetermined value. The following can be achieved, and noise and heat generation can be suppressed.
[0035]
Even when the power supply voltage (Vcc) fluctuates, the rise and fall times Tup and Tdown can be set to desired values.
Since the threshold voltage of the power MOS transistor varies depending on the temperature, the temperature of the power element may be detected and the rise / fall time may be measured using the threshold voltage at that temperature. That is, temperature compensation of the Vt value may be performed.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a control device for a power MOS transistor according to an embodiment.
FIG. 2 is a configuration diagram of a gate voltage control circuit.
FIG. 3 is a time chart for explaining the operation.
FIG. 4 is a graph showing transistor characteristics.
FIG. 5 is a circuit configuration diagram showing an example of a time measurement circuit in a control logic.
FIG. 6 is a time chart for explaining the operation.
FIG. 7 is a time chart for explaining the operation.
FIG. 8 is a time chart for explaining the operation.
FIG. 9 is a configuration diagram of a control device for a power MOS transistor for explaining the prior art.
FIG. 10 is a diagram showing a current waveform.
FIG. 11 is a diagram for explaining a difference in slope time due to a difference in load current.
FIG. 12 is a configuration diagram of a control device for a power MOS transistor for explaining the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Power MOS transistor, 2 ... Load, 3 ... Gate voltage control circuit, 4 ... Control logic, 5 ... Gate-source voltage detection circuit, 6 ... Differential amplifier, 7, 8, 9, 10 ... Resistance, 11 ... Voltage detection circuit, 12 ... comparator, 13 ... voltage detection circuit, 14 ... comparator, 15 ... reference power supply, 16 ... reference power supply, Vcc ... power supply.

Claims (4)

A power MOS transistor (1) and a load (2) are connected in series to the power supply (Vcc), and a voltage is applied to the gate terminal of the power MOS transistor (1) to cause rise and fall of the load (2). A control device for a power MOS transistor in which an oblique pulse-shaped current flows.
A gate-source voltage detection means (5) for detecting a gate-source voltage (Vgs) of the power MOS transistor (1) accompanying voltage application to the gate terminal of the power MOS transistor (1);
Based on the gate-source voltage (Vgs) of the power MOS transistor (1) by the gate-source voltage detection means (5) , the current load (2) is measured by measuring the duration of the saturation region in the transistor characteristics. The rise and fall times (Tup, Tdown) in the current waveform of the current are calculated, and the rise and fall times (Tup, Tdown) in the current waveform of the current load (2) and the target value are obtained. Feedback means (4) for obtaining a deviation and feedback-controlling the power MOS transistor (1) so as to eliminate the deviation;
A control device for a power MOS transistor, comprising: First comparison means (11) for comparing the detected gate-source voltage (Vgs) with a first determination value between the off-time voltage and the threshold voltage;
Second comparison means (13) for comparing the detected gate-source voltage (Vgs) with a second determination value between the threshold voltage and the on-time voltage;
Based on the comparison result by the first and second comparison means (11, 13), the duration between the first judgment value and the second judgment value is used as the duration of the saturation region in the transistor characteristics. Timing means (4) for measuring;
The power MOS transistor control device according to claim 1 , further comprising: The power MOS transistor control device according to claim 1 or 2 , wherein the power MOS transistor (1) is feedback-controlled so that the rise time is constant and the fall time is constant. . It said load (2) the control unit of the power MOS transistor according to any one of claims 1 to 3, characterized in that a ramp.

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