JP4522445B2 - Display device - Google Patents

Description

  The present invention relates to a display device used in a word processor, a personal computer, a television broadcast receiver, and the like. In particular, the present invention relates to a display device such as an active matrix liquid crystal display device.

  The liquid crystal display device is a flat display device having excellent features such as high definition, thinness, light weight, and low power consumption. In recent years, the display performance has been improved, the production capacity has been improved, and price competition with other display devices has been achieved. The market size is expanding rapidly as power improves.

  In such a liquid crystal display device, the problem of viewing angle dependence of the gamma characteristic, which is the gradation dependence of display luminance, such as whitening, has newly emerged as a problem related to viewing angle characteristics under the circumstances where display quality is being improved. ing.

  The problem of the viewing angle dependence of the γ characteristic is a problem in which the γ characteristic at the time of observation from the front direction is different from the γ characteristic at the time of observation from the oblique direction. The difference in γ characteristics between the observation from the front direction and the observation from the oblique direction means that the gradation display state differs depending on the observation direction. The problem of the viewing angle dependency of the γ characteristic is a particularly serious problem when displaying an image such as a photograph or when displaying a television broadcast received by a receiver.

  As a technique for improving the problem of viewing angle dependency of the γ characteristic, a technique called multi-picture element driving has been proposed (see Patent Document 1). Multi-pixel drive is a technology that improves the viewing angle dependence of viewing angle characteristics, that is, gamma characteristics, by dividing one display picture element into two or more sub-picture elements with different luminance. is there.

  Hereinafter, the principle of multi-picture element driving will be described with reference to FIGS.

  FIG. 8 is a graph showing the γ characteristic in the liquid crystal display panel of the liquid crystal display device. In the graph shown in FIG. 8, the vertical axis represents the luminance ratio, and the horizontal axis represents the gradation (voltage). In the graph shown in FIG. 8, the characteristic indicated by the solid line is a γ characteristic when a liquid crystal display panel driven by a normal driving method is observed from the front direction. The most normal visibility is obtained. Here, the normal driving method means a driving method in which one display picture element is not divided into a plurality of sub-picture elements. In the graph shown in FIG. 8, a characteristic indicated by a broken line is a γ characteristic when a liquid crystal display panel driven by a normal driving method is observed from an oblique direction, and in the case of having such a γ characteristic, There is a deviation of the γ characteristic from the normal visibility. It should be noted that the degree of deviation is small at a portion where the luminance ratio is close to 0 or 1, and is large at a portion where the luminance ratio is far from 0 or 1. That is, the degree of deviation is small in the portion showing bright luminance and dark luminance, and large in the portion showing halftone. For this reason, the halftone display luminance in the visual recognition from the oblique direction becomes very large, and as a result, white floating or the like occurs in the visual recognition from the oblique direction.

  On the other hand, in the multi-pixel drive, when obtaining a target brightness in one display picture element, the average brightness in a plurality of sub-picture elements constituting the one display picture element is set as the target brightness. In addition, the drive of the picture element is controlled. In the multi-pixel drive, the γ characteristic when observed from the front direction is the same as that of the normal driving method. That is, in the multi-pixel drive, the γ characteristic when observed from the front direction becomes a characteristic indicated by a solid line in the graph shown in FIG. 8, and the most normal visibility is obtained. On the other hand, in the multi-pixel drive, the γ characteristic when observed from the oblique direction becomes the characteristic indicated by the alternate long and short dash line in the graph shown in FIG. 8, and the luminance deviation is reduced. This is because the areas near the bright luminance and the dark luminance where the deviation of luminance is small are displayed for each sub-picture element, and the area of the halftone luminance is displayed by the average of the luminance of the sub-picture element. .

  Next, FIG. 9 shows a configuration example of display picture elements of a liquid crystal display device driven by multi-picture element driving.

  As shown in FIG. 9, one display picture element 120 is divided into a plurality of sub picture elements 121, 122. The sub picture element 121 is connected to the scanning line Gn and the signal line Sm via a TFT (Thin Film Transistor) 123. The sub picture element 122 is connected to the scanning line Gn and the signal line Sm via the TFT 124. The gate electrodes of the TFTs 123 and 124 are connected to a common (same) scanning line Gn. The source electrodes of the TFTs 123 and 124 are connected to a common (same) signal line Sm.

  The sub-picture element 121 has a liquid crystal capacitor CLC100 and an auxiliary capacitor CCS100. One of the liquid crystal capacitor CLC100 and the auxiliary capacitor CCS100 is connected to the drain electrode of the TFT 123. The other electrode of the liquid crystal capacitor CLC100 is connected to the counter voltage VCOM100. The other electrode of the auxiliary capacitance CCS 100 is connected to the auxiliary capacitance wiring 125. As a result, a storage capacitor counter voltage (hereinafter referred to as a CS voltage) can be applied to the storage capacitor CCS 100 from the storage capacitor wiring 125.

  Further, the sub-picture element 122 has a liquid crystal capacitor CLC101 and an auxiliary capacitor CCS101. One electrode of each of the liquid crystal capacitor CLC 101 and the auxiliary capacitor CCS 101 is connected to the drain electrode of the TFT 124. The other electrode of the liquid crystal capacitor CLC101 is connected to the counter voltage VCOM101. The other electrode of the auxiliary capacitor CCS 101 is connected to the auxiliary capacitor line 126. Thereby, a CS voltage different from the CS voltage that can be supplied to the auxiliary capacitor CCS100 can be applied to the auxiliary capacitor CCS101 from the auxiliary capacitor wiring 126.

  FIG. 10 shows an example of waveforms of the source voltage and the CS voltage applied to each of the sub-picture elements 121 and 122 in the display picture element 120 shown in FIG.

  In the display picture element 120 having the configuration shown in FIG. 9, different CS voltages are applied to the plurality of divided sub picture elements 121 and 122, respectively. As a result, the voltage applied to the drain electrode of the TFT 123 is different from the voltage applied to the drain electrode of the TFT 124. In the sub-picture elements 121 and 122, the gradations displayed are also different from each other. In this case, the CS voltage is driven by AC (alternating current). Specifically, the source electrodes of the TFTs 123 and 124 are turned on at the same gate timing, but the voltages of the CS electrodes (that is, the auxiliary capacitors CCS100 and CCS101) connected to the drain electrodes of the TFTs 123 and 124 are different from each other. Therefore, the actually held voltage differs between the TFT 123 and the TFT 124. As a result, the sub-picture elements 121 and 122 can display different luminances, that is, different gradations.

  Note that the amplitude of the CS voltage in the auxiliary capacitance wiring 125 and the amplitude of the CS voltage in the auxiliary capacitance wiring 126 have substantially the same amplitude and frequency as shown in FIG. In the next frame, the CS voltage is inverted in accordance with the inversion of the source voltages of the TFTs 123 and 124. Thus, the CS voltage is driven by AC.

Here, the voltage Va applied to the sub-picture element 121 and the voltage Vb applied to the sub-picture element 122 are relative to the original applied voltage Vm that gives the target luminance.
Vm = (Va + Vb) / 2
Satisfy the relationship. From this, it can be seen that the target luminance is obtained by averaging the display luminances of the sub-picture elements 121 and 122.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for performing CS voltage inversion with a period longer than the frame period for a high-definition liquid crystal display panel with a short horizontal scanning period.

  In a high-definition liquid crystal display panel, the horizontal scanning period is shortened and the number of auxiliary capacitors is increased. In such a liquid crystal display panel, the waveform of the signal (auxiliary capacitor drive signal) for applying the CS voltage is dull. Since the degree of the waveform dullness varies depending on the location in the liquid crystal display panel, the effective voltage applied to the sub-pixel electrode also varies depending on the location in the liquid crystal display panel. As a result, the liquid crystal display panel has a problem of uneven display brightness.

  In order to solve the above problem, in the technique disclosed in Patent Document 2, the oscillation cycle of the CS voltage is lengthened. Thereby, in the technique disclosed in Patent Document 2, unevenness in the luminance of the display is reduced.

  For example, when the waveform of the CS voltage is inverted every frame, as shown in FIG. 10, it is necessary to prepare two types of CS voltage waveforms (that is, the CS voltage waveform that is the basis of Va and Vb).

  In addition, the graphs of FIGS. 11A and 11B show an example in which the waveform of the CS voltage is inverted every two frames. When the waveform of the CS voltage is inverted every two frames, it is necessary to further prepare a CS voltage having a waveform whose phase is shifted by one frame, and as shown in the graphs of FIGS. , “CSVtypeA1” to “VCSVtypeA4” need to prepare four types of CS voltages. In this case, the CS voltage signal line on the liquid crystal display panel is composed of “CSVtypeA1” to “CSVtypeA4” in the direction perpendicular to the both ends of the picture element and the auxiliary capacitance wiring 150 as shown in FIG. A main line 151 is arranged. The CS voltage is supplied to each auxiliary capacitor 152 by the auxiliary capacitor line 150 drawn from the main line 151.

  In addition, FIG. 13 shows auxiliary capacity drive signal wiring on the glass substrate of the liquid crystal display panel.

  A source driver 162 that supplies a display signal to the signal line Sm and a gate driver 163 that supplies a scanning line drive signal (scanning line signal) to the scanning line Gn are mounted on the glass substrate 161 of the liquid crystal display panel 160. . Here, gate drivers 163A and 163B are mounted as the gate driver 163.

  A signal for controlling the source driver 162, a signal for controlling the gate driver 163, and a storage capacitor driving signal are generated by a controller (not shown) and supplied to the source driver 162. Among these signals, the signal for controlling the gate driver 163 and the auxiliary capacitance drive signal are given to the wiring 165 on the glass substrate 161 through the wiring 164 provided on the package of the source driver 162. Further, among these, a signal for controlling the gate driver 163 is supplied to the input terminal of the gate driver 163A through the wiring 165 on the glass substrate 161.

  The gate driver 163A generates the scanning line driving signal and supplies the control signal (a signal for controlling the source driver 162 and a signal for controlling the gate driver 163) to the gate driver 163B at the next stage.

  The wiring 165 on the glass substrate 161 for supplying the auxiliary capacity driving signal extends the basic wiring 166 in the direction orthogonal to the scanning line Gn as a basic signal line. The auxiliary capacity drive signal is supplied to each auxiliary capacity CCS through the auxiliary capacity line CSL drawn from the main line 166. In FIG. 13, reference numerals “CLC”, which are not described, are liquid crystal capacitors, and reference numerals “VCOM” are counter voltages.

  Further, as a method for mounting a driving LSI (Large Scale Integration) such as a gate driver, Patent Literature 3 discloses a driver socket (so-called interposer substrate) made of silicon, for example, and is configured with a narrow pitch. A liquid crystal driver mounting package in which output terminals of a driving LSI are expanded is disclosed. This liquid crystal driver mounting package is convenient because the terminal pitch of the base material (so-called tape carrier) that relays the connection between the LSI and the panel does not need to be narrow.

  Hereinafter, this technique will be described with reference to FIGS.

  FIG. 14A is a top view of the IC chip mounting package according to Patent Document 3, and FIG. 14B is a cross-sectional view taken along line GG in FIG.

  It can be said that the feature of the IC chip mounting package according to Patent Document 3 is the driver socket 401.

  15 and 16 are diagrams showing the driver socket 401. FIG. FIG. 15A is a perspective view showing a state in which the liquid crystal driver 601 that is an integrated circuit is mounted on the driver socket 401, and FIG. 15B is a view taken along the line I1-I1 in FIG. It is sectional drawing. Further, FIG. 16 is a diagram showing how the liquid crystal driver 601 is mounted in the driver socket 401.

  As shown in FIGS. 15A and 15B, a driver socket 401 includes a bump 402 between a driver socket and a film (see a film 501 in FIG. 14B), a bump 403 between a driver and a driver socket, and a driver socket. A wiring 405 is provided.

  The driver-driver socket bump 403 of the driver socket 401 connects the driver socket 401 and the driver bump 404 provided on the liquid crystal driver 601 (see FIG. 15B). The bump pitch between the driver-driver socket bump 403 and the driver bump 404 is substantially the same, for example, 20 μm or less.

  On the other hand, the driver socket-film bump 402 of the driver socket 401 connects the driver socket 401 and the wiring 502 provided on the film 501 (see FIG. 14B). The pitch of the bumps 402 between the driver socket and the film is, for example, 50 μm or more, which is wider than the bump pitch between the bumps 403 between the driver and driver sockets 403 and the driver bumps 404.

  Then, the driver socket 401 provided with the liquid crystal driver 601 shown in FIG. 15A is mounted on the film 501 shown in FIG. 14B using the driver socket-film bump 402.

When the driver socket 401 is not used, the pitch of the bumps on the film 501 to be mounted needs to be 20 μm or less in accordance with the pitch of the driver bumps 404 of the liquid crystal driver 601, but when the driver socket 401 is used. Can be set to 50 μm, which is the pitch of the driver socket-film bumps 402 of the driver socket 401.
Japanese Patent Laying-Open No. 2004-62146 (released on February 26, 2004) JP 2005-189804 A (published July 14, 2005) International Publication Number WO 2007/052761 A1 (published on May 10, 2007)

  In the technique disclosed in Patent Document 1, in order to reduce the unevenness of display brightness in the liquid crystal display panel described above, it is necessary to reduce the impedance of the wiring that supplies the auxiliary capacitance drive signal to the auxiliary capacitance. As a method for reducing the impedance of the wiring, a method of increasing the line width of the wiring can be considered.

  Here, the wiring is arranged on the same panel as the pixel that performs display, that is, on the same glass substrate as the pixel that performs display. Since the wiring provided on the glass substrate has a large wiring resistance, the line width of the wiring must be sufficiently thick in order to reduce the impedance of the wiring. As a result, in the liquid crystal display panel, the basic wiring becomes very thick, and the area other than the display pixels becomes large. As a result, the liquid crystal display panel has a problem that it is difficult to narrow the frame.

  In the technique disclosed in Patent Document 2, the influence of waveform dullness is suppressed by increasing the oscillation period of the CS voltage, and the unevenness in luminance of the display is reduced. More types of voltage waveforms. For this reason, the liquid crystal display panel requires a large number of voltage sources for generating the CS voltage, and accordingly, the area other than the display pixels becomes large. As a result, the technique disclosed in Patent Document 2 also has a problem that it is difficult to narrow the frame.

  Note that the technique disclosed in Patent Document 3 is merely a technique for a suitable mounting method of a driving LSI, and is not a technique premised on application to a display device driven by multi-picture element driving.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of narrowing the frame in a display device driven by multi-picture element driving. .

  In order to solve the above-described problem, the display device according to the present invention provides each scanning based on a plurality of scanning lines and a scanning line driving signal supplied to each scanning line constituting the plurality of scanning lines. And a scanning line driving device for driving a line. One display picture element is divided into a plurality of sub-picture elements, and the plurality of sub-picture elements are connected to different auxiliary capacity wirings. And driving the auxiliary capacitors connected to the auxiliary capacitor lines based on the auxiliary capacitor drive signals supplied to the auxiliary capacitor lines constituting the different auxiliary capacitor lines. The sub-picture elements can be displayed at different luminances, and the scanning line driving device supplies an auxiliary capacitance driving signal to be supplied to each auxiliary capacitance wiring to each auxiliary capacitance wiring. The first terminal and each of the scanning lines A plurality of second terminals for supplying the scanning line drive signals to be supplied to the respective scanning lines, and at least one of the plurality of first terminals is the plurality of the plurality of second terminals. The second terminal is provided between any two terminals.

  According to the above configuration, in the display device according to the present invention, the storage capacitor driving signal is supplied to the storage capacitor wiring from the first terminal provided in the scanning line driving device. The auxiliary capacitance provided in the auxiliary capacitance wiring can be driven.

  Here, the scanning line driving device is provided with a plurality of first terminals. For this reason, in the scanning line driving device, it is possible to supply an auxiliary capacity driving signal to a plurality of auxiliary capacity lines by connecting an auxiliary capacity line to each of the plurality of first terminals. In the case of a display device driven by multi-picture element driving, one display picture element is divided into a plurality of sub-picture elements, and each of the plurality of sub-picture elements has different auxiliary capacitance lines. The scanning line driving device is provided with first terminals corresponding to the number of the auxiliary capacitance lines, and the auxiliary capacitance lines and the first terminals are connected to each other, so that the auxiliary capacitance is used by using the scanning line driving device. It is possible to supply a storage capacitor driving signal to each of the wirings. In the case where a plurality of first terminals are provided in the scanning line driving device, it is not necessary to provide a main wiring for supplying the auxiliary capacitance driving signal to the auxiliary capacitance wiring outside the scanning line driving device. For this reason, increasing the number of types of waveform of the CS voltage to be used in order to reduce the influence of waveform dullness and reduce display luminance unevenness in the wiring that makes up the main wiring. It can suppress that it becomes difficult to narrow a frame resulting from that.

  In the scanning line driving device, at least one of the plurality of first terminals is provided to supply a scanning line driving signal to each of the plurality of scanning lines. The second terminal is provided between any two terminals. That is, in the scanning line driving device, the first terminal is provided between the plurality of second terminals. For this reason, the scanning line driving device can easily supply the auxiliary capacitance driving signal to the auxiliary capacitance wiring provided in the vicinity of the second terminal. That is, in the display device according to the present invention, the storage capacitor driving signal can be easily supplied to the storage capacitor lines by the scanning line driving device.

  From the above, in the display device according to the present invention, it is possible to reduce the area other than the display pixels.

  Therefore, in the display device driven by multi-picture element driving, there is an effect that the frame can be narrowed.

  In the display device according to the present invention, the scanning line driving device further includes a third terminal to which an auxiliary capacitance driving signal to be supplied to each auxiliary capacitance wiring from the outside thereof is input. The terminal is connected to the first terminal.

  According to the above configuration, it is possible to input an auxiliary capacitance driving signal from the third terminal to the scanning line driving device and supply it to each auxiliary capacitance wiring from the first terminal.

  In the display device according to the present invention, the scanning line driving device receives the first terminal, the second terminal, and auxiliary capacitance driving signals to be supplied to the auxiliary capacitance lines from the outside of the scanning line driving device. And a substrate provided with a third terminal, and an integrated circuit that generates the scanning line driving signal and supplies the scanning line driving signal to the second terminal. Good.

  In the display device according to the present invention, an auxiliary capacitance drive signal to be supplied from the third terminal to each auxiliary capacitance line is input between the third terminal and the first terminal. The storage device further includes a buffer that shapes the waveform of the auxiliary capacitor driving signal and outputs the waveform to the first terminal. Further, in the display device according to the present invention, the integrated circuit has a buffer that inputs an auxiliary capacitance driving signal to be supplied to each auxiliary capacitance wiring and shapes and outputs a waveform of the input auxiliary capacitance driving signal. The buffer has an input terminal connected to the third terminal and an output terminal connected to the first terminal. In the display device according to the present invention, the substrate includes a buffer that inputs an auxiliary capacitance driving signal to be supplied to each auxiliary capacitance wiring and shapes and outputs the waveform of the input auxiliary capacitance driving signal. The buffer has an input terminal connected to the third terminal and an output terminal connected to the first terminal.

  According to the above configuration, the storage capacitor driving signal input from the third terminal to the scanning line driving device is input to the buffer. Then, the buffer can shape the waveform of the storage capacitor drive signal input to itself and supply it to each storage capacitor line from the first terminal.

  Here, the process of “shaping the waveform of the auxiliary capacity drive signal” is a process of suitably driving the auxiliary capacity by the auxiliary capacity drive signal, such as a process of reducing dullness generated in the auxiliary capacity drive signal, This means a process for improving the driving capacity of the auxiliary capacitor. In general, the buffer has a Schmitt trigger function, and such a process can be easily performed in the buffer having the Schmitt trigger function.

  Thus, in the display device according to the present invention, the auxiliary capacitance driving signal is supplied to each auxiliary capacitance wiring via the buffer, so that the auxiliary capacitance driving signal with reduced waveform dullness is supplied to each auxiliary capacitance wiring. It becomes possible to supply, that is, the driving capacity of the auxiliary capacitor can be improved. For this reason, in the display device according to the present invention, even when the line width is narrowed in the auxiliary capacitance wiring, it is possible to suppress the influence caused by the occurrence of waveform dullness, display luminance unevenness, and the like.

  From the above, in the display device according to the present invention, it is possible to further reduce the area other than the display pixels.

  Therefore, in the display device driven by multi-picture element driving, there is an effect that the frame can be further narrowed.

  In the display device according to the present invention, the buffer outputs an auxiliary capacitance drive signal input to the buffer by overshoot drive.

  According to the above configuration, the buffer outputs the auxiliary capacitance driving signal by overshoot driving. As a result, it is possible to shorten the time for which the auxiliary capacitor connected to each auxiliary capacitor line to which the auxiliary capacitor drive signal is supplied can be charged, so that the plurality of sub-picture elements can be driven quickly. Thus, in the display device according to the present invention, even when the driving time is shortened due to an increase in scanning lines, unevenness in display luminance can be reduced and display variations can be reduced.

  As described above, the display device according to the present invention scans each scanning line based on a plurality of scanning lines and a scanning line drive signal supplied to each scanning line constituting the plurality of scanning lines. Each display pixel is divided into a plurality of sub-picture elements, and each of the plurality of sub-picture elements has an auxiliary capacity connected to a different auxiliary capacity wiring. The plurality of sub-picture elements are driven by driving the auxiliary capacitors connected to the auxiliary capacitor lines based on the auxiliary capacitor driving signals supplied to the auxiliary capacitor lines constituting the different auxiliary capacitor lines. A display device capable of displaying at different luminances, wherein the scanning line driving device includes a first terminal for supplying an auxiliary capacitance driving signal to be supplied to each auxiliary capacitance wiring to each auxiliary capacitance wiring; Scan to be supplied to each of the scan lines A plurality of second terminals for supplying drive signals to the scanning lines, and at least one of the plurality of first terminals is the plurality of second terminals. It is the structure provided between any two terminals.

  Therefore, in the display device driven by multi-picture element driving, there is an effect that the frame can be narrowed.

  An embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those already described with reference to the drawings are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a block diagram showing a schematic configuration of a scanning line driving device provided in a display device according to the present invention.

  A gate driver mounting substrate (scanning line driving device) 1 shown in FIG. 1 is configured by mounting a gate driver (integrated circuit) 2 on an interposer substrate (substrate) 3.

  The gate driver 2 includes control logics 11A and 11B, a bidirectional shift register 12, a level shifter 13, an output circuit 14, and a buffer 21.

  From here, the function of the terminal provided in the gate driver mounting board | substrate 1 is demonstrated. Here, the terminals provided on the gate driver mounting substrate 1 are illustrated as circular members in FIG. Further, the reference numerals (characters) attached to the circular members are the terminal names of the terminals provided on the gate driver mounting substrate 1. All the terminals provided on the gate driver mounting substrate 1 are provided on the gate driver 2 and the interposer substrate 3, and terminals having the same terminal name are connected to each other. As a result, the gate driver mounting substrate 1 can supply an input signal or an applied voltage from the outside to the gate driver 2 via the interposer substrate 3. This also allows the gate driver mounting substrate 1 to supply an output signal or an applied voltage from the gate driver 2 to the outside via the interposer substrate 3. Therefore, here, description of each terminal provided on the gate driver mounting substrate 1 regardless of whether it is a terminal provided on the gate driver 2 or a terminal provided on the interposer substrate 3, Repeat for each terminal with a different name.

  The terminal “LBR” is an input terminal to which a control signal indicating the shift direction of the bidirectional shift register 12 is input. The terminal “LBR” has a state “H” and a state “L”. By switching between the state “H” and the state “L” according to the control signal, the terminal “LBR” Control the shift direction. Thus, the scanning direction of the scanning line driving signal output from the output circuit 14 is determined. The output circuit 14 is a circuit provided to output the scanning line drive signal to terminals “OG1” to “OG272” to be described later.

  Terminals “GSPOI” and “GSPIO” are IO (Input / Output) terminals having a function of switching between an input terminal and an output terminal in accordance with a control signal input to the terminal “LBR”. When the terminal “LBR” is in the state “H”, the terminal “GSPOI” is an input terminal, and the terminal “GSPIO” is an output terminal. On the other hand, when the terminal “LBR” is in the state “L”, the terminal “GSPOI” is an output terminal and the terminal “GSPIO” is an input terminal. Of the terminals “GSPOI” and “GSPIO”, a terminal having the function of an input terminal inputs a signal for starting the operation of the bidirectional shift register 12 (hereinafter referred to as “scanning start signal”) to the gate driver 2. It becomes a terminal to do. Of the terminals “GSPOI” and “GSPIO”, a terminal having the function of an output terminal is a terminal for outputting the scan start signal to a gate driver (not shown) cascade-connected to the gate driver 2. It becomes.

  Similarly to the terminals “GSPOI” and “GSPIO”, the terminals “GCKOI” and “GCKIO” are IO terminals having a function of switching between an input terminal and an output terminal in accordance with a control signal input to the terminal “LBR”. It is. That is, when the terminal “LBR” is in the state “H”, the terminal “GCKOI” is an input terminal and the terminal “GCKIO” is an output terminal. When the terminal “LBR” is in the state “L”, the terminal “GCKOI” is an output terminal, and the terminal “GCKIO” is an input terminal. Of the terminals “GCKOI” and “GCKIO”, a terminal having the function of an input terminal is a terminal for inputting a driving clock signal of the bidirectional shift register 12 to the gate driver 2. Of the terminals “GCKOI” and “GCKIO”, a terminal having a function of an output terminal is a terminal for outputting the drive clock signal to the gate driver of the next stage.

  Terminals “VGL” and “VGH” are power supply terminals to which a power supply (not shown) for operating the output circuit 14 is connected. When the power supply voltage applied to the terminal “VGL” is vgl and the power supply voltage applied to the terminal “VGH” is vgh, vgl is smaller than vgh. In this case, the output circuit 14 outputs the scanning line drive signal to the terminals “OG1” to “OG272” as a signal having an amplitude from vgl to vgh.

  The terminal “VCC” is a power supply terminal to which a power supply (not shown) for operating the gate driver 2 is connected. The terminal “GND” is a ground terminal.

  Terminals “OG1” to “OG272” (second terminals) are output terminals for scanning line driving signals for outputting the scanning line driving signals from the output circuit 14 to the outside of the gate driver mounting substrate 1. A scanning line provided in the display device is directly connected to the terminals “OG1” to “OG272”, or the scanning line and the terminals “OG1” to “OG272” are connected through wirings or the like. The scanning line drive signals output from the terminals “OG1” to “OG272” can be supplied to the scanning lines. The scanning line is driven based on the scanning line driving signal supplied to the scanning line. The terminals “OG1” to “OG272” can be connected to one scanning line per terminal. That is, the terminals “OG1” to “OG272” can supply a scanning line driving signal to one scanning line per terminal. In this embodiment, an example in which a total of 272 scanning lines connected to each of the terminals “OG1” to “OG272” are driven in the gate driver mounting substrate 1 will be described, but the present invention is not limited to this. That is, in the scanning line driving device according to the present invention, the scanning line is not connected to at least one terminal of the terminals “OG1” to “OG272” (that is, a total of 271 or fewer scannings in the scanning line driving device). It may be configured to drive a line).

  In addition, in this drawing, illustration is abbreviate | omitted about some terminals among terminals "OG1"-"OG272" for convenience.

  Terminals “CSVtypeA1R” to “CSVtypeA4R” (third terminal) and “CSVtypeA1L” to “CSVtypeA4L” are auxiliary capacity drive signal input terminals to which an external capacity drive signal is input from the outside. Terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” (first terminal) are connected directly to an auxiliary capacity wiring (for example, an auxiliary capacity wiring 51 in FIG. 7 described later), or the auxiliary capacity via a wiring or the like. An auxiliary capacitance drive signal output terminal that can supply an auxiliary capacitance drive signal to the auxiliary capacitance wiring by being connected to the wiring.

Terminals “VCSH” and “VCSL” are power supply terminals to which a power supply (not shown) for operating the buffer 21 is connected. The power supply voltage from the power supply applied to the terminals “VCSH” and “VCSL” is
The power supply voltage of the terminal “VCSH”> the power supply voltage of the terminal “VCSL”.

  The terminals “OVCSH” and “OVCSL” are power supply terminals to which a power supply (not shown) for operating the buffer 21 is connected. Here, the power supply voltage from the power supply applied to the terminal “OVCSH” is several V higher than the power supply voltage of the terminal “VCSH”, and the power supply from the power supply applied to the terminal “OVCSL”. The voltage is set several V lower than the power supply voltage of the terminal “VCSL”.

  Terminals “CSVtypeA1R” to “CSVtypeA4R” provided on the gate driver 2 are connected to terminals “CSVtypeA1L” to “CSVtypeA4L” provided on the gate driver 2. The input terminal of the buffer 21 is connected between the terminals “CSVtypeA1R” to “CSVtypeA4R” provided in the gate driver 2 and the terminals “CSVtypeA1L” to “CSVtypeA4L” provided in the gate driver 2. Has been. The output terminal of the buffer 21 is connected to terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided in the gate driver 2.

  The auxiliary capacitance driving signal input to the gate driver mounting substrate 1 shown in FIG. 1 is input to the buffer 21 from the terminals “CSVtypeA1R” to “CSVtypeA4R” (or the terminals “CSVtypeA1L” to “CSVtypeA4L”). The buffer 21 shapes the waveform of the input auxiliary capacitance driving signal, and outputs the auxiliary capacitance driving signal whose waveform has been shaped to the auxiliary capacitance wiring via the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′”. In the gate driver mounting substrate 1, the auxiliary capacitance driving signal with reduced waveform dullness is thus supplied to the auxiliary capacitance wiring, and the auxiliary capacitance connected to the auxiliary capacitance wiring is driven. Note that the buffer used as the buffer 21 is used for adjusting the number of input fan-ins, improving the output drive capability, and the like. Many of the buffers used for input have a Schmitt trigger function, and perform noise removal and waveform shaping of the input signal. Further, here, the process of “shaping the waveform of the auxiliary capacity drive signal” means the process of reducing the dullness generated in the auxiliary capacity drive signal and the process of amplifying the amplitude of the auxiliary capacity drive signal. It means a process for suitably driving the auxiliary capacity by the drive signal, that is, a process for improving the drive capacity of the auxiliary capacity. In general, the buffer as described above has the Schmitt trigger function, and the Schmitt trigger function can easily perform the process of “shaping the waveform of the auxiliary capacitance drive signal”. .

  However, since the buffer 21 is not an essential component in the display device according to the present invention, it can be omitted. When the buffer 21 is omitted, the gate driver mounting substrate 1 includes terminals “CSVtypeA1R” to “CSVtypeA4R” provided on the gate driver 2 and terminals “CSVtypeA1L” to “CSVtypeA4L” provided on the gate driver 2. , Terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided in the gate driver 2 are connected.

  The terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided on the interposer substrate 3 each have a plurality of terminals.

  Further, as shown in FIG. 1, the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided on the interposer substrate 3 are appropriately connected between the terminals “OG1” and “OG272” provided on the interposer substrate 3. Is provided. Further, as shown in FIG. 1, the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided on the interposer substrate 3 exclude the portion between the terminals “OG1” and “OG272” provided on the interposer substrate 3. You may provide suitably in the part. That is, at least one of the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided on the interposer substrate 3 is between the terminals “OG1” and “OG272” provided on the interposer substrate 3 ( That is, it is provided between any two terminals of the plurality of terminals “OG1” to “OG272”. The terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” provided on the gate driver 2 are all connected to the terminals “CSVtypeA1 ′” provided on the interposer substrate 3 by the wiring 4 provided on the interposer substrate 3. To “CSVtypeA4 ′”.

  FIG. 2 is a diagram illustrating a circuit configuration of the buffer 21.

  The buffer 21A shown in FIG. 2 has a configuration in which an input terminal 211, two inverters 212A and 212B, and an output terminal 213 are connected in series in this order.

  In each of the two inverters 212A and 212B provided in the buffer 21A shown in FIG. 2, the power supply line VCSH is connected to the terminal “VCSH” provided in the gate driver 2 shown in FIG. The VCSL is connected to a terminal “VCSL” provided in the gate driver 2 shown in FIG.

  The inverter 212A includes a p-channel MOS (Metal Oxide Semiconductor) field effect transistor 212AP to which the voltage from the terminal “VCSH” is applied to the source terminal, and an n-channel to which the voltage from the terminal “VCSL” is applied to the source terminal. Type MOS field effect transistor 212AN. The inverter 212B includes a p-channel MOS field effect transistor 212BP to which the voltage from the terminal “VCSH” is applied to the source terminal, and an n-channel MOS to which the voltage from the terminal “VCSL” is applied to the source terminal. An inverter circuit including a field effect transistor 212BN.

  The buffer 21A shown in FIG. 2 is configured by connecting the inverters 212A and 212B having the above configuration in two stages.

  FIG. 3 is a diagram illustrating another circuit configuration of the buffer 21.

  A buffer 21B illustrated in FIG. 3 includes an inverter circuit 212C instead of the inverter 212B in the configuration of the buffer 21A illustrated in FIG. In the configuration of the inverter 212B, the inverter circuit 212C further includes a switch SW1 connected to the source terminal of the transistor 212BP and a power supply line OVCSH connected to the terminal “OVCSH” provided in the gate driver 2 shown in FIG. The power supply line OVCSL is further connected to the switch SW2 connected to the source terminal of the transistor 212BN and the terminal “OVCSL” provided in the gate driver 2 shown in FIG.

  Both the switches SW1 and SW2 are constituted by, for example, a single-pole changeover switch that performs a c-contact operation. The switch SW1 switches between a state in which the source terminal of the transistor 212BP is connected to the terminal “VCSH” and a state in which the source terminal of the transistor 212BP is connected to the terminal “OVCSH” by switching on and off. The switch SW2 switches between a state where the source terminal of the transistor 212BN is connected to the terminal “VCSL” and a state where the source terminal of the transistor 212BN is connected to the terminal “OVCSL” by switching on and off.

  Here, the switch SW1 is in a state in which the source terminal of the transistor 212BP is connected to the terminal “OVCSH” for a predetermined time from the moment when the storage capacitor drive signal input from the input terminal 211 rises, and other times. , The source terminal of the transistor 212BP is connected to the terminal “VCSH”. Similarly, the switch SW2 is in a state in which the source terminal of the transistor 212BN is connected to the terminal “OVCSL” for a predetermined time from the moment when the auxiliary capacitance drive signal falls, and at other times, the transistor 212BN Are connected to the terminal “VCSL”.

  When the switching operation of the switches SW1 and SW2 is controlled as described above in the buffer 21B shown in FIG. 3, the auxiliary capacitance drive signal output from the buffer has the waveform shown in FIG.

  FIG. 4 is a graph showing the waveform of the storage capacitor drive signal after the so-called overshoot process is performed by the buffer 21B. In the graph shown in FIG. 4, the vertical axis represents the level of the auxiliary capacity drive signal, and the horizontal axis represents time.

  The switch SW1 is connected between the source terminal of the transistor 212BP and the terminal “VCSH” during a period T3 from the rising instant T1 of the auxiliary capacity drive signal whose waveform is shown in FIG. 4 to T2 after a lapse of a predetermined time from the rising instant T1. Is connected to a terminal “OVCSH” having a potential several V higher than the potential of “”. At a time other than T3, the switch SW1 connects the source terminal of the transistor 212BP and the terminal “VCSH”.

  Similarly, the switch SW2 is connected to the source terminal of the transistor 212BN at the time T6 from the falling instant T4 of the auxiliary capacitance drive signal whose waveform is shown in FIG. 4 to T5 after the falling time T4. Are connected to a terminal “OVCSL” having a potential several V lower than the potential of the terminal “VCSL”. At a time other than T6, the switch SW2 connects the source terminal of the transistor 212BN and the terminal “VCSL”.

  By using the buffer 21B as the buffer 21 of the gate driver 2 shown in FIG. 1, the above-described overshoot process shown in FIG. 4 is performed on the auxiliary capacitance drive signal. As a result, the gate driver 2 shown in FIG. 1 temporarily outputs a potential higher than the voltage to be output at the rising edge of the storage capacitor drive signal by the overshoot process, and then outputs the target potential. Similarly, the gate driver 2 shown in FIG. 1 once outputs a potential lower than the voltage to be output when the storage capacitor drive signal falls due to the overshoot process, and then outputs a target potential. . Thereby, the charging time of the auxiliary capacitor and the liquid crystal capacitor can be advanced, and the time required to reach the target voltage can be shortened. As a result, the gate driver 2 shown in FIG. 1 can cope with a case where the driving time of the auxiliary capacitor is shortened due to an increase in scanning lines. In other words, the gate driver 2 shown in FIG. 1 can appropriately drive the auxiliary capacitor even when the driving time of the auxiliary capacitor is shortened due to an increase in scanning lines. And display variations can be reduced.

  Here, an outline of the principle of generating the scanning line driving signal in the gate driver 2 will be described.

  A control signal for setting the terminal “LBR” to the “H” state or the “L” state is supplied to the terminal “LBR” of the gate driver 2 shown in FIG. Thereby, in the gate driver 2, the shift direction of the bidirectional shift register 12 is determined, and thereby the scanning direction of the scanning line driving signal is determined. Here, the above outline will be described on the assumption that the terminal “LBR” is in the “H” state. In this case, the scanning direction of the scanning line driving signal output from the output circuit 14, that is, the order of the scanning lines to which the scanning line driving signal is supplied, is connected to the scanning line connected to the terminal “OG1” and the terminal “OG2”. ,..., A scanning line connected to the terminal “OG272”.

  When the scan start signal generated based on the vertical synchronization signal is input from the terminal “GSPOI” of the gate driver 2, the bidirectional shift register 12 outputs the drive clock signal input from the terminal “GCKOI” of the gate driver 2. The shift operation is started in synchronization with the first pulse, and a first pulse that is a pulse signal is generated by the shift operation. As the driving clock signal, a signal generated based on the horizontal synchronizing signal is used.

  The first pulse is level-converted by the level shifter 13 from the voltage vgl to a signal having the amplitude of the voltage vgh, and is scanned as a scanning line drive signal from the output circuit 14 to the terminal “OG1”. Output to line. Next, the bidirectional shift register 12 generates a second pulse, which is a pulse signal different from the first pulse, by the above shift operation. The second pulse is level-converted by the level shifter 13 from the voltage vgl to a signal having the amplitude of the voltage vgh, and the scanning line connected to the terminal “OG2” from the output circuit 14 as a scanning line driving signal. Is output.

  That is, the bidirectional shift register 12 generates the (n + 1) th pulse, which is a pulse signal different from the nth pulse, by the above shift operation. The (n + 1) th pulse is level-converted by the level shifter 13 from the voltage vgl to a signal having the amplitude of the voltage vgh, and is connected from the output circuit 14 to the terminal “OG (n + 1)” as a scanning line drive signal. Is output to the scanning line. Next, the bidirectional shift register 12 generates an (n + 2) th pulse, which is a pulse signal different from the (n + 1) th pulse, by the above-described shift operation. It repeats until the scanning line drive signal produced | generated based on the pulse (272nd pulse) is output to the scanning line connected to "." In the case of the bidirectional shift register 12, “n” is an arbitrary natural number between 1 and 270.

  In the shift operation in the bidirectional shift register 12 described above, a signal synchronized with the horizontal synchronization signal is used. For this reason, the scanning line driving signals output from the terminals “OG1” to “OG272” drive one scanning line for each period of the horizontal synchronization signal.

  When the above-described shift operation is completed, that is, when a scanning line driving signal is output to the scanning line connected to the terminal “OG272”, the gate driver 2 outputs a scanning start signal from the terminal “GSPIO” and also outputs the terminal “ A drive clock signal is output from “GCKIO”. The scanning start signal and the driving clock signal are input to the next-stage gate driver. As a result, the next-stage gate driver starts the scanning line driving signal generation operation in the scanning line driving device, similar to the gate driver 2. For example, when the gate driver 2 drives 272 scanning lines, in the gate driver in the next stage, from the 273th scanning line to the 274th scanning line, the 275th scanning line, and so on. In addition, a scanning line driving signal is given to the scanning line.

  FIG. 5 is a view showing the outer shape of the scanning line driving device package on which the gate driver mounting substrate 1 is mounted. When an auxiliary capacitor driving signal is supplied to an auxiliary capacitor wiring provided in a display device (for example, a liquid crystal display panel 40 shown in FIG. 7 described later) driven by multi-pixel driving by the gate driver mounting substrate 1, and When the gate driver mounting substrate 1 supplies a scanning line driving signal to the scanning lines provided in the display device, the gate driver mounting substrate 1 is applied to the display device in the form of the scanning line driving device package 30 shown in FIG. It may be provided.

  In order to more clearly illustrate the feature points according to the present invention, the scanning line driving device package 30 shown in FIG. 5 is illustrated in a state where the member through which the auxiliary capacitance driving signal passes is seen through.

  The scanning line drive device package 30 shown in FIG. 5 has a configuration in which the gate driver mounting substrate 1 is mounted on a tape 31.

  In the scanning line driving device package 30 shown in FIG. 5, terminals of the display device corresponding to the terminals of the gate driver mounting substrate 1 are provided in the terminal portion. Note that the term “terminal portion” refers to a member having the same symbol (character) as the terminal name of the terminal provided on the gate driver mounting substrate 1 in the scanning line driver package 30. 30 is a member provided at the right end portion of 30. All the terminals provided in the scanning line driving device package 30 shown in FIG. 5 are connected to terminals provided on the gate driver mounting substrate 1 and terminals having the same terminal name. As a result, in the scanning line driving device package 30 shown in FIG. 5, it is possible to output a signal or voltage output from the gate driver mounting substrate 1 to the outside of the scanning line driving device package 30. For convenience, in FIG. 5, a plurality of wirings through which the storage capacitor driving signal passes (for example, wirings 34 connecting the terminals “CSVtypeA1R” and “CSVtypeA1L”) and wirings around the wirings are shown by one thick line. It is shown.

  In the scanning line driver package 30, terminals “OG1” to “OG272” are arranged near the center of the terminal portion, and between the terminals “OG1” to “OG272” (and to the terminals “OG1” to “OG272”). Terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” are appropriately arranged on both sides. The other terminals are arranged near the ends of the terminal portions, rather than the terminals “OG1” to “OG272”. The terminals “CSVtypeA1R” to “CSVtypeA4R” in the terminal portion are connected to the terminals “CSVtypeA1L” to “CSVtypeA4L” in the terminal portion by the wiring 31 provided on the tape 31 and the gate driver mounting substrate 1. In addition, although not shown, each terminal has two terminals, “VGL”, terminal “VGH”, terminal “GND”, terminal “LBR”, terminal “VCC”, terminal “VCSH”, The terminal “VCSL”, the terminal “OVCSH”, and the terminal “OVCSL” are all connected via a terminal in which one terminal and the other terminal of the two terminals have the same terminal name in the gate driver mounting substrate 1. It is connected. The terminals “GSPOI” and “GSPIO” have an input / output relationship in which when one becomes an input terminal, the other becomes an output terminal. That is, the terminals “GSPOI” and “GSPIO” output a signal input from one terminal from the other terminal. The terminals “GSPOI” and “GSPIO” are preferably arranged at both ends of the terminal portion. Similarly, the terminals “GCKOI” and “GCKIO” are also preferably arranged at both ends of the terminal portion.

  FIG. 6 is a diagram showing an overview of the gate driver mounting substrate 1. FIG. 6A is a perspective view showing a state in which the gate driver 2 is mounted on the interposer substrate 3, and FIG. 6B is a diagram showing a state in which the gate driver 2 is mounted on the interposer substrate 3. .

  As shown in FIG. 6A, the interposer substrate 3 is provided with a terminal-substrate bump 35 connected to a film terminal (not shown) and an on-substrate wiring 36. By the on-substrate wiring 36, a gate driver is provided. 2 and the terminal-substrate bump 35 are connected.

  The terminal-to-substrate bump 35a on the input side is an input terminal for an auxiliary capacitance drive signal on the gate driver mounting substrate 1 (that is, terminals “CSVtypeA1R” to “CSVtypeA4R”, “CSVtypeA1L” to “CSVtypeA4L”) of the interposer substrate 3. . A wiring 34 (see FIG. 5) is connected to the terminal-substrate bump 35a on the input side, and an auxiliary capacitance drive signal input terminal in the gate driver 2 (that is, the terminal “CSVtypeA1R of the gate driver 2) by the substrate wiring 36a. To “CSVtypeA4R”, “CSVtypeA1L” to “CSVtypeA4L”) (see FIG. 6B). Here, for the sake of convenience, only one auxiliary capacitor drive signal input terminal in the gate driver mounting substrate 1 is shown, and the auxiliary capacitor drive signal input terminal in the gate driver 2 is not shown. However, these input terminals are provided on the gate driver 2 or the interposer substrate 3 by the total number of terminals “CSVtypeA1R” to “CSVtypeA4R” and “CSVtypeA1L” to “CSVtypeA4L” provided on the gate driver 2 or the interposer substrate 3. Needless to say, it is.

  The input terminal of the auxiliary capacity drive signal in the gate driver 2 is connected to the input terminal of the buffer 21 in the gate driver 2, and the output terminals of the buffer 21 are the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” of the gate driver 2 (not shown). (See FIG. 6B). The terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” of the gate driver 2 and the bumps 35b on the output side of the interposer substrate 3 are connected by the on-substrate wirings 36b, but the scanning lines drive signals pass through the bumps 35b. Therefore, the on-substrate wiring 36b through which the auxiliary capacitance driving signal passes needs to intersect the on-substrate wiring 36c through which the scanning line driving signal passes. For this reason, the on-substrate wiring 36 b through which the auxiliary capacitance driving signal passes and the on-substrate wiring 36 c through which the scanning line driving signal passes are formed in different layers so as to intersect on the interposer substrate 3.

  Note that the buffer 21 for driving the auxiliary capacitance drive signal may be provided on the interposer substrate 3 as shown in FIG.

  Since the interposer substrate 3 is manufactured in the same manufacturing process as that for manufacturing the integrated circuit, it is possible to make the wiring layer into two layers and to provide a buffer.

  FIG. 7 is a diagram showing a state in which the scanning line driving device package 30 is mounted on the substrate of the display device.

  In order to more clearly illustrate the feature points according to the present invention, the liquid crystal display panel (display device) 40 shown in FIG. 7 is illustrated in a state where a member through which an auxiliary capacitance drive signal passes is seen through.

  FIG. 7 illustrates a liquid crystal display panel 40 in which two scanning line driving device packages 30 are mounted on a display device as a display device according to the present invention, but the present invention is not limited to this. That is, only one scanning line driving device package 30 may be mounted on the substrate of the liquid crystal display panel 40, or three or more scanning line driving device packages 30 may be mounted.

  Hereinafter, the configuration and operation principle of the display device according to the present invention will be described with reference to FIG.

  As shown in FIG. 7, in the liquid crystal display panel 40, one display picture element 41 is divided into a plurality of sub picture elements 42 and 43. The sub-picture element 42 is connected to the scanning line Gn and the signal line (data line) Sm via the TFT 44. The sub picture element 43 is connected to the scanning line Gn and the signal line Sm via the TFT 45. That is, the gate electrodes of the TFTs 44 and 45 are connected to the common (same) scanning line Gn. The source electrodes of the TFTs 44 and 45 are connected to a common (same) signal line Sm.

  The sub-picture elements 42 and 43 have a liquid crystal capacity and an auxiliary capacity. In both the liquid crystal capacitor and the auxiliary capacitor, one electrode is connected to the drain electrodes of the TFTs 44 and 45. The other electrode of the liquid crystal capacitor is connected to a counter voltage. The other electrode of the auxiliary capacitance is connected to auxiliary capacitance wirings 46 and 47. Accordingly, the CS voltage can be applied from the auxiliary capacitance lines 46 and 47 to the auxiliary capacitance in the sub-picture elements 42 and 43. That is, the sub-picture elements 42 and 43 have the same connection relationship as the sub-picture elements 121 and 122 shown in FIG. Therefore, the CS voltage applied to the auxiliary capacitor in the sub-picture element 42 and the CS voltage applied to the auxiliary capacitor in the sub-picture element 43 can be different from each other.

  That is, the display picture element 41 shown in FIG. 7 has the same configuration as the display picture element 120 shown in FIG.

  In the liquid crystal display panel 40, first, an auxiliary capacitor drive signal and a gate driver control signal as a basis of the scan line drive signal are transferred from a controller (not shown) to the scan line drive device package 30A having the same configuration as the scan line drive device package 30. (Scanning start signal and driving clock signal) and various power supply voltages are input. Here, the terminal “LBR” is connected to the terminal “VCC”, whereby the terminal “LBR” is fixed to the “H” state. Note that the storage capacitor driving signal is input to the scanning line driving device package 30A from terminals “CSVtypeA1R” to “CSVtypeA4R”. Further, since the terminal “LBR” is in the “H” state, the control signal of the gate driver is input from the terminals “GSPOI” and “GCKOI”. Further, various power supply voltages are input from terminals “VGL”, “VGH”, “GND”, “VCC”, “VCSL”, “VCSH”, “OVCSL”, and “OVCSH”.

  Here, in FIG. 7, the terminals “LBR”, “VGL”, “VGH”, “GND”, “VCC”, “VCSL”, “VCSH”, “OVCSL”, and “OVCSH” are the same terminals. Named terminals are connected to each other. Further, as illustrated in FIG. 7, the terminal “GSPOI” is connected to the terminal “GSPIO”, and the terminal “GCKOI” is connected to the terminal “GCKIO”.

  Similarly, as shown in FIG. 7, the terminals “CSVtypeA1R” to “CSVtypeA4R” are connected to the terminals “CSVtypeA1L” to “CSVtypeA4L”, respectively.

  Therefore, the terminals “CSVtypeA1L” to “CSVtypeA4L” provided in the scanning line driving device package 30A and the terminal “CSVtypeA1R” provided in the scanning line driving device package 30B having the same configuration as the scanning line driving device package 30A. By connecting to “CSVtypeA4R”, the liquid crystal display panel 40 receives the auxiliary capacity drive signal, the gate driver control signal, and various power supply voltages that are input to the scan line drive device package 30A. The scan line driver package 30B can be supplied from the package 30A.

  Next, in the liquid crystal display panel 40, the scanning line driving device package 30 </ b> A generates a scanning line driving signal based on the above-described principle using a signal that is a basis of the scanning line driving signal input from the controller. The terminals “OG1” to “OG272” of the scanning line driver package 30A are connected to the scanning lines Gn of the liquid crystal display panel 40, respectively. Then, the scanning line driving device package 30A gives a scanning line driving signal to each scanning line Gn connected to the terminals “OG1” to “OG272”.

  On the other hand, the auxiliary capacitance drive signals input to the terminals “CSVtypeA1R” to “CSVtypeA4R” from the controller are connected to the terminal “CSVtypeA1 ′” via the buffer 21 provided on the gate driver mounting substrate 1 of the scanning line driver package 30A. To “CSVtypeA4 ′”. The storage capacitor line 51 is connected to the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” of the scanning line driver package 30A. The auxiliary capacitance drive signal with reduced waveform dullness output from the buffer 21 is applied to all the auxiliary capacitance lines 51 connected to the terminals “CSVtypeA1 ′” to “CSVtypeA4 ′” of the scanning line driving device package 30A. As a result, the auxiliary capacitance connected to the auxiliary capacitance wiring 51 is driven.

  In the display device according to the present invention, it is not necessary to provide the main wiring on the entire liquid crystal display panel unlike the display device according to the prior art. Therefore, the display device according to the present invention has an effect that the frame can be narrowed.

  Note that the display device according to the present invention may have a configuration in which an auxiliary capacitance driving signal is generated inside the scanning line driving device and is supplied from the scanning line driving device to each auxiliary capacitance wiring.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for display devices used in, for example, word processors, personal computers, television broadcast receivers, and the like. Further, the present invention can be suitably used for a display device such as an active matrix liquid crystal display device and a scanning line driving device for driving a scanning line provided in the display device.

It is a block diagram which shows schematic structure of the scanning line drive device with which the display apparatus which concerns on this invention is equipped. It is a figure which shows the circuit structure of the buffer provided in the said scanning line drive device. It is a figure which shows another circuit structure of the buffer provided in the said scanning line drive device. FIG. 4 is a graph showing a waveform of an auxiliary capacitance drive signal after an overshoot process is performed by the buffer shown in FIG. 3. It is a figure which shows the external shape of the scanning line drive device package in which the said scanning line drive device was mounted. FIG. 6A is a perspective view showing a state after an integrated circuit is mounted on a substrate, and FIG. 6B is a view in which the buffer is provided. FIG. 6C is a diagram illustrating a state where the integrated circuit is mounted on the substrate, and FIG. 6C is a diagram illustrating a state where the integrated circuit is mounted on the substrate provided with the buffer. It is a figure which shows the display apparatus which concerns on this invention, and is a figure which shows the state which mounted the said scanning line drive device package on the board | substrate of the display apparatus. It is a graph which shows the (gamma) characteristic in the liquid crystal display panel of a liquid crystal display device. It is a figure which shows the structural example of the display picture element of the liquid crystal display device driven by multi picture element drive. In the said display picture element, it is a figure which shows an example of the waveform of the source voltage applied to each of a sub picture element, and CS voltage. FIGS. 11A and 11B are graphs showing an example in which the waveform of the auxiliary capacitor counter voltage is inverted every two frames. It is a figure which shows typically the equivalent circuit of the said liquid crystal display device. It is a figure which shows the wiring of the auxiliary capacity drive signal in the glass substrate of a liquid crystal display panel. FIG. 14A is a top view of an IC chip mounting package according to the prior art, and FIG. 14B is a cross-sectional view taken along line GG in FIG. FIG. 15A is a perspective view showing a state in which a liquid crystal driver which is an integrated circuit is mounted on a driver socket, and FIG. 15B is a cross-sectional view taken along line I1-I1 in FIG. It is. It is a figure which shows the said driver socket, and is a figure which shows a mode that the said liquid crystal driver is mounted in this driver socket.

Explanation of symbols

1 Gate driver mounting board
2 Gate driver (integrated circuit)
3 Interposer substrate (substrate)
21, 21A, 21B Buffer 30, 30A, 30B Scanning line drive device package 40 Liquid crystal display panel (display device)

Claims (5)

A plurality of scanning lines, and a plurality of scanning line driving devices that drive each scanning line based on a scanning line driving signal supplied to each scanning line constituting the plurality of scanning lines,
One display picture element is divided into a plurality of sub picture elements,
Each of the plurality of sub-picture elements has an auxiliary capacity connected to a different auxiliary capacity wiring,
The plurality of sub-pixels are respectively driven by driving the auxiliary capacitors connected to the auxiliary capacitor lines based on the auxiliary capacitor drive signals supplied to the auxiliary capacitor lines constituting the different auxiliary capacitor lines. A display device capable of displaying with different brightness,
The plurality of said scanning line driving device,
A first terminal for supplying a storage capacitor drive signal to be supplied to each storage capacitor line to each storage capacitor line and a scan line drive signal to be supplied to each scan line are supplied to each scan line. A substrate having a plurality of second terminals, respectively,
An integrated circuit including a smaller number of the first terminals than the substrate,
The first terminal of one of the integrated circuits is connected to the first terminals of the plurality of substrates, and each auxiliary capacitance line is connected to each first terminal of the one substrate. Connected to
The substrate has at least any one terminal of the plurality of first terminals provided between any two terminals of the plurality of second terminals ;
A plurality of the scanning line driving devices are provided on each of the substrate and the integrated circuit.
A third terminal to which an auxiliary capacity drive signal to be supplied to each of the auxiliary capacity lines is input from the outside thereof;
A fourth terminal for supplying the auxiliary capacitance driving signal to the scanning line driving device different from the own device;
At least one of the scanning line driving devices includes:
A third terminal of the substrate of the own device and a third terminal of the integrated circuit of the own device are connected to each other;
A third terminal of the integrated circuit of the own device, a first terminal of the integrated circuit of the own device, and a fourth terminal of the integrated circuit of the own device are connected to each other;
A fourth terminal of the integrated circuit of the own device and a fourth terminal of the substrate of the own device are connected to each other; and
A display device, wherein a fourth terminal of the substrate of the device itself is connected to a third terminal of the substrate of the other scanning line driving device. The display device according to claim 1 , wherein the integrated circuit generates the scanning line driving signal and supplies the scanning line driving signal to the second terminal . Between the third terminal of the integrated circuit and the first terminal of the integrated circuit, an auxiliary capacitor driving signal to be supplied from the third terminal of the integrated circuit to each auxiliary capacitor line is input and input. a display device according to claim 1, by shaping the waveform of the storage capacitor driving signals, characterized by further comprising a buffer for output to the first terminal of the integrated circuit. The display device according to claim 3 , wherein the buffer is provided on one of the substrate and the integrated circuit . The display device according to claim 3, wherein the buffer outputs an auxiliary capacitance driving signal input thereto by overshoot driving .

Images