KR20190081479A - Display Device and Driving Method thereof - Google Patents

Abstract

The present invention relates to a display device for removing a consumption current in a black pixel part by selectively providing a scan signal to a part corresponding to some areas in a gate driver and not providing a scan signal to the other areas if some areas of a surface are displayed. The display device of the present invention comprises: a display panel on which a plurality of pixels connected to a plurality of data lines and a plurality of gate lines are arranged; a data driver providing a data voltage to the data lines; a gate driver providing a scan signal to the gate lines; and a timing controller providing a start signal to a start signal line corresponding to a partial display area displayed on the display panel based on image data inputted from the outside.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF

The present invention relates to a display apparatus and a driving method thereof. More specifically, the present invention relates to a display device and a driving method thereof for dividing and driving only a specific area of a display panel using a multi-VST signal.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various kinds of display devices such as a liquid crystal display (LCD) and an organic light emitting display (OLED) have been used.

Such a display device includes a display panel in which data lines and gate lines are arranged and in which pixels connected to a data line and a gate line are arranged, a data driver for supplying data voltages to the data lines, a gate driver for driving the gate lines, , A timing controller for controlling the driving timing of the data driver and the gate driver, and the like.

Here, the gate driver generates a scan signal for driving each gate line, and sequentially provides the generated scan signal to the display panel.

The conventional gate driver is configured such that the start signal VST provided from the timing controller is input only to the first gate line. When the start signal VST is input to the first gate line, the scan signal generated in the first gate line is input to the start signal VST of the next gate line. In this way, when the start signal is input to the first gate line, the gate driver is always driven continuously to the last gate line.

Accordingly, even when an image is displayed only in a partial area of the display panel, the gate driver outputs a scan signal to all gate lines as in the case where an image is displayed in the entire area. This causes a logic consumption current for GIP (Gate in Panel) driving in a black driving pixel area which does not require driving.

Therefore, there is a problem that unnecessary power consumption occurs.

In the present invention, when only a partial area of the screen is displayed, only the portion corresponding to the partial display area in the gate driver is selectively supplied with the scan signal, while the other non-display areas are not provided with the scan signal, A display device for eliminating a consumed current and a driving method thereof.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned can be understood by the following description and more clearly understood by the embodiments of the present invention. It will also be readily apparent that the objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

According to an aspect of the present invention, there is provided a display device including a display panel including a plurality of data lines and a plurality of pixels connected to a plurality of gate lines, a data driver for providing a data voltage to the data lines, And a timing controller for providing a start signal to the start signal line corresponding to a partial display region displayed on the display panel based on image data input from the outside.

The gate driver may include a first stage unit including a start signal line to which a start signal VST provided from the timing controller is applied and a scan signal line to which a scan signal provided from a stage unit at a previous stage is applied, And a second stage portion including a scan signal line to which a scan signal provided from a stage portion positioned at a previous stage is applied.

The first stage unit may include a start signal line to which the start signal supplied from the timing controller is applied, a scan signal line to which a scan signal provided from a stage unit located at a previous stage is applied, And a logic unit for outputting to a stage unit positioned at the next stage according to a start signal applied from the signal line.

The timing controller may include a first stage portion connected to a first gate line among the gate lines arranged in the partial display region or a first stage portion connected to a gate line located before a first gate line, to provide.

In addition, the timing controller provides an off clock signal (GCLK) to a stage portion corresponding to a gate line positioned next to the gate line corresponding to the last gate line among the gate lines arranged in the partial display region .

When the start signal is provided, the first stage unit sequentially provides scan signals from a gate line corresponding to the first stage unit provided with the start signal.

In addition, the first stage unit changes the scan signal provided to the gate line to an off signal when the off clock signal is provided.

In addition, the timing controller provides a plurality of start signals to the gate driver for one frame.

According to an aspect of the present invention, there is provided a method of driving a display device including receiving image data input from the outside, detecting a partial display area to be displayed on the display panel in the input image data, And providing a first start signal to a first stage corresponding to a specific gate line corresponding to the detected partial display area.

Further, an off clock signal (GCLK) is provided to the first or second stage portion corresponding to the gate line next to the gate line corresponding to the last gate line among the gate lines arranged in the partial display region .

The step of providing the first start signal may correspond to a first stage portion corresponding to a first gate line among the gate lines arranged in the partial display region or a gate line positioned before the first gate line through the timing controller The first start signal VST is supplied to the first stage unit.

Providing a second start signal to a first stage portion corresponding to a gate line corresponding to the detected partial display region during one frame; A step of sequentially providing scan signals from a gate line corresponding to a first stage portion of the first display region and a second gate line corresponding to a gate line positioned next to the last gate line among the gate lines arranged in the partial display region, And providing an off clock signal to the second stage portion.

According to an embodiment of the present invention, when only a partial display region of a screen is displayed, such as a clock, the display apparatus and the driving method thereof according to the present invention can selectively provide only a portion corresponding to the partial display region in the gate driver And the other non-display areas are not provided with a scan signal, thereby eliminating the consumption current in the non-display area.

Particularly, the gate driver can provide a scan signal by dividing all the partial display regions even when the partial display region is not one but a plurality of start signals VST during one frame.

This can reduce the logic consumption current due to GIP (Gate in Panel) driving.

1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention;
Fig. 2 is a block diagram showing the configuration of the gate driver in detail in Fig.
FIG. 3 is a cross-sectional view of the gate driver shown in FIG.
4 is a timing chart showing driving timings of the gate driver according to the present invention

The above and other objects, features, and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, which are not intended to limit the scope of the present invention. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements.

Hereinafter, a display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention.

1, the display device of the present invention includes a display panel 100 having a plurality of data lines DL1 to DLm and a plurality of pixels P connected to a plurality of gate lines GL1 to GLn, A data driver 200 for supplying a data voltage to the data lines DL1 to DLm, a gate driver 300 for providing a scan signal to the gate lines GL1 to GLn, (T) for determining a partial display region on which the image data is to be displayed on the display panel 100 and providing a start signal VST to a stage portion corresponding to a specific gate line of the gate driver 300, -CON) < / RTI >

The display region display panel 100 is formed by intersecting a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. The pixels P connected to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm constitute a driving transistor TFT. The driving transistor TFT provides a data voltage from the data lines DL1 to DLm to the light emitting element in response to a scan signal from the gate lines GL1 to GLn. To this end, the gate electrode of the driving transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode thereof is connected to the data lines DL1 to DLm. The drain electrode of the driving transistor TFT is connected to the pixel electrode of the light emitting element.

The data driver 200 provides data voltages to the plurality of data lines DL1 to DLm on the display panel 100 in response to the data control signal DCS. The data control signal DCS is provided from the timing controller 400. The data voltages supplied to the data lines DL1 to DLm are generated as data lines DL1 to DLm whenever one of the plurality of gate lines GL1 to GLn is enabled.

In response to the start signal VST, the gate driver 300 sequentially supplies the scan signals to the gate line, starting from the stage portion to which the start signal VST is applied. The start signal VST is supplied from the timing controller 400. [ Then, the scan signals are sequentially enabled for one period of the horizontal synchronous signal starting from the gate line to be started.

The timing controller 400 receives synchronization signals (Vsync, Hsync) and a start signal (VST) from an external system (for example, a graphics module of a computer system or a video demodulation module of a television receiving system, , A data enable (DE) signal, and a clock signal (CLK) to control the data driver 200 and the gate driver 300. The timing controller 400 aligns image data input from an external system and provides the aligned image data to the data driver 200. [ The timing controller 400 determines a partial display area on which the image data is to be displayed on the display panel 100 based on the image data and outputs a start signal VST). The timing controller 400 provides an off clock signal GCLK to a stage portion corresponding to the next gate line of the last gate line among the gate lines corresponding to the partial display region. The gate driver 300 changes the scan signal supplied to the gate line to an off signal (low potential signal) when the off clock signal GCLK is input.

The timing controller 400 may provide a plurality of start signals to the gate driver 300 for one frame.

Accordingly, the gate driver 300 provides scan signals to the gate line GL starting from a stage portion to which at least one start signal VST is applied. When the off-clock signal GCLK is supplied from the timing controller 400, the gate driver 300 changes the scan signal supplied to the gate line to an off signal.

The gate driver 300 sequentially supplies scan signals from the gate line corresponding to the stage portion to which the start signal VST is applied to the gate line. At this time, an on signal is applied to the gate clock signal GCLK applied from the timing controller 400. When the off clock signal GCLK is applied from the timing controller 400, the gate driver 300 changes the scan signal supplied to the gate line to an off signal. Accordingly, the gate driver 300 can provide a scan signal only in a partial display region requiring driving, and can drive the specific region of the display panel 100 in a divided manner. The gate driver 300 may receive a plurality of start signals VST1, VST2, VST3, and VST4 from the timing controller 400 and may divide and drive a plurality of partial display regions during one frame.

The gate driver 300 may be located on one side or both sides of the display panel 100 according to the driving method. The gate driver 300 may output one scan signal to one gate line GL in a single feeding manner or one scan line GL in a double feeding manner according to a driving method. Two scan signals may be output. The gate driver 300 may include one or more gate driver integrated circuits.

Each gate driving integrated circuit may be connected to a bonding pad of the display panel 100 by a tape automation bonding (TAB) method or a chip on glass (COG) method, or may be connected to a bonding pad of a GIP (Gate In Panel) type And may be disposed directly on the display panel 100. In addition, they may be integrated in the display panel 100 or may be implemented in a chip-on-film (COF) mode in which they are mounted on a film connected to the display panel 100.

FIG. 2 is a block diagram showing the configuration of the gate driver in FIG. 1 in detail.

As shown in FIG. 2, the gate driver 300 receives a start signal supplied with the start signal VST provided from the timing controller 400 and a scan signal supplied from the stage unit located at the previous stage A first stage unit 301, 302, 303, 304 including a scan signal line, and a second stage unit 305, 306 including a scan signal line to which a scan signal supplied from a stage unit located at a previous stage is applied.

The first stage units 301, 302, 303, and 304 may receive the start signal VST from the timing controller 400 through the start signal line. Therefore, the first stage units 301, 302, 303, and 304 are connected to both the scan signal line and the start signal line, from which the scan signal is supplied from the previous stage unit. At least two first stage units 301, 302, 303 and 304 are formed, and each of the first stage units 301, 302, 303 and 304 includes a plurality of gate lines therebetween.

The second stage units 305 and 306 include only a scan signal line to which a scan signal is supplied from the previous single stage unit. At least two of the second stage units 305 and 306 are configured.

In the display panel 100, an image is displayed in only a part of the first and second partial display areas 110 and 120, not the entire frame, such as a clock, corresponding to the image data input from the timing controller 400, It is assumed that a black image is displayed in the area.

The first and second stage units 301, 302, 303 and 304 (305 and 306) are connected to a plurality of gate lines GL1 to GLn formed on the display panel 100, respectively. At this time, the first stage units 301, 302, 303, and 304 may be connected to one of the plurality of gate lines GL1 to GLn. The first stage units 301, 302, 303, and 304 are positioned such that at least one gate line is located between each first stage unit. The second stage units 305 and 306 may be connected to one of the plurality of gate lines GL1 to GLn. The second stage units 305 and 306 may be positioned in a plurality of positions between the first stage units 301, 302, 303 and 304.

The timing controller 400 provides a start signal VST to the first stage units 301, 302, 303, and 304 corresponding to the first gate line among the gate lines arranged in the first display region 110. [

Referring to FIG. 2, the first gate line among the gate lines GLa to GLb arranged in the first display region 110 is the a-th gate line GLa. The a-th gate line GLa is connected to the first stage unit 302. Thus, the timing controller 400 provides the second start signal VST2 to the first stage unit 302. [

In addition, the first gate line among the gate lines GLc to GLd arranged in the second partial display region 120 is the c-th gate line GLc. The c-th gate line GLc is connected to the first stage unit 304. Accordingly, the timing controller 400 provides the first start signal VST4 to the first stage unit 304. [

On the other hand, the stage portion connected to the first gate line among the gate lines arranged in the partial display region may be a second stage portion not including the start signal line. In FIG. 2, the first gate line among the gate lines arranged in the first and second partial display regions 110 and 120 is connected to the first stage units 301, 302, 303, and 304. However, since the first stage units 301, 302, 303, and 304 are not connected to all the gate lines GL, the first stage units 301, 302, 303, and 304 may not be connected to the first gate line corresponding to the partial display region.

Therefore, when the first gate line of the gate lines arranged in the partial display region is connected to the second stage units 305 and 306, the timing controller 400 controls the gate lines positioned before the first gate line corresponding to the partial display region The start signal VST is provided to the first stage units 301, 302, 303, and 304 connected thereto.

Accordingly, the first stage units 301, 302, 303, and 304 provided with the start signal VST sequentially provide the scan signals from the gate line corresponding to the first stage unit provided with the start signal VST.

Also, even when the first gate line corresponding to the partial display region among the gate lines arranged in the partial display region is connected to the second stage units 305 and 306, the gate driver 300 is connected to the first stage units 301, 302, 303 and 304 The scan signal may be sequentially supplied from the gate line connected to the scan line. Accordingly, while the gate driver 300 conventionally provides a scan signal from the first gate line of the display panel irrespective of the partial display area, the present invention is not limited to the case where the first gate line corresponding to the partial display area A scan signal can be provided.

The timing controller 400 provides the gate clock signal GCLK to each stage portion of the gate driver 300. The gate clock signal GCLK is a control signal for providing a scan signal to each gate line GL in the gate driver 300. The clock signal GCLK may have phases such as two-phase, four-phase, or eight-phase. The clock signal GCLK can be generated by the level shifter using the clock information input from the timing controller 400.

The timing controller 400 generates an off clock signal GCLK (GCLK) to the stage portion corresponding to the gate line positioned next to the last gate line among the gate lines arranged in the partial display region corresponding to the image data input from the external system, ).

Referring to FIG. 2, the timing controller 400 corresponds to a gate line positioned next to the b-th gate line GLb corresponding to the last gate line among the gate lines arranged in the first partial display region 110 And provides a clock signal (GCLK) off (off) signal to the stage portion. In addition, the timing controller 400 supplies a clock signal (a gate signal) to the stage portion corresponding to the gate line positioned next to the d-th gate line GLd corresponding to the last gate line among the gate lines arranged in the second partial display region 120 GCLK < / RTI > off signal.

The timing controller 400 switches according to the signal format used in correspondence with the input image data and provides the clock signal GCLK to the gate driver 300.

Accordingly, the gate driver 300 sequentially supplies the scan signal to the gate line GL corresponding to the stage portion provided with the start signal VST, starting with the stage portion provided with the start signal VST. The gate driver 300 provides the scan signal changed to the OFF signal to the gate line GL corresponding to the stage portion to which the off clock signal GCLK is provided.

Accordingly, the gate driver 300 sequentially supplies a scan signal from the a-th gate line GLa corresponding to the a-th stage 302 to which the second start signal VST2 is applied to the b-th gate line GLb do. Then, the gate driver 300 changes the scan signal to an off signal after the b < th > gate line GLb.

Next, the gate driver 300 sequentially supplies a scan signal from the c-th gate line GLc corresponding to the c-th stage unit 304 to which the fourth start signal VST4 is applied to the d-th gate line GLd do. And a scan signal which is changed to an off signal after the d < th > gate line GLd.

At this time, the timing controller 400 provides a data driving signal to the data driver 120 at a proper time in accordance with the scan signal corresponding to the input image data input from the outside. Then, the display panel 100 displays the input image in the partial display area.

When the image is displayed only in the partial display area and the black image is displayed in the remaining non-display area, the gate driver 300 provides the scan signal only to the partial display area requiring driving, and in the other non- The consumption current generated in the non-display area can be removed.

FIG. 3 is an embodiment showing the configuration of the gate driver in FIG.

3, the gate driver 300 includes a first stage portion 308 and a second stage portion 307,

The first stage unit 308 includes a start signal line 310 to which the second start signal VST2 provided from the timing controller 400 is applied and a scan signal line 310 provided from the stage unit 307 located at the previous stage. The scan signal line 320 to which the scan signal line SCANi-2 is applied and the stage unit 309 positioned at the next stage according to the second start signal VST2 applied from the scan signal line 320 and the start signal line 310, To the logic unit NOR gate.

At this time, the logic unit is composed of a NOR gate. That is, when either the second start signal VST2 or the scan signal SCANi-2 provided from the stage unit 307 located at the previous stage is inputted, on the other hand, And provides the scan signal SCANi-1 to the stage unit 309 positioned therein. However, the elements constituting the logic section depending on whether the start signal and the scan signal are the high signal or the low signal in the on signal will be changeable.

The second stage units 307 and 309 are connected to the scan signal line 320 to which the scan signal SCANi-2 supplied from the stage unit 307 positioned at the previous stage is applied.

The scan signal SCANi-1 is supplied to the gate line GL. The scan signal SCANi-1 is transmitted to the stage unit 309 positioned at the next stage and serves as a start signal VST of the stage unit 309. [

The start signal VST is provided to the first stage portion 308 connected to the first gate line among the gate lines corresponding to the partial display region. On the other hand, when there is no first stage portion 308 corresponding to the partial display region, the start signal VST is provided to the first stage portion (not shown) located before.

The first and second stage units 308 and 307 and 309 receive the clock signal GCLK from the timing controller 400. 3 shows a case where the clock signal GCLK has a phase of four phases.

The first and second stage units 308 and 309 and 309 control the timing of supplying the scan signal to the gate line GL corresponding to the input clock signal GCLK. In other words, the first and second stage units 308 and 307 and 309 sequentially receive the scan signal generated when the on signal is inputted as the clock signal GCLK, and the gate line GL corresponding to the single stage, (309). When the off signal is inputted as the clock signal GCLK, the first and second stage units 308 and 309 and 309 change the generated scan signal to the off signal and output the off signal to the gate lines GL and And provided to the stage unit 309 at the next stage.

At this time, the stage unit 309 at the next stage uses the scan signal input from the stage unit 307 at the previous stage as its own start signal VST.

4 is a timing chart showing the driving timing of the gate driver according to the present invention. When the display panel 100 is divided into the first and second partial display regions 110 and 120 and the non-display region, the gate driver 300 In the figure).

4, the timing controller 400 provides the clock signals GCLK1, GCLK2, GCLK4, and GCLK4 to the gate driver 300. [ The clock signal GCLK is a control signal for providing a scan signal from the gate driver 300 to the gate line GL. The clock signal GCLK may have a phase of two-phase, four-phase, or eight-phase, and the embodiment of FIG. 4 has a four-phase phase.

The timing controller 400 provides the start signal VST to the first stage unit connected to the gate line corresponding to the partial display area corresponding to the image data input from the external system. 2, the timing controller 400 includes a first stage unit (not shown) connected to the a-th gate line GLa corresponding to the first gate line among the gate lines arranged in the first partial display region 110 302 to the second start signal VST2.

The first stage unit 302 provided with the second start signal VST2 sequentially provides a scan signal from the a-th gate line GLa corresponding to the first stage unit 302. [

In response to the image data input from the external system, the timing controller 400 supplies an off clock signal GCLK (or an on-off clock signal) to the first or second stage portion corresponding to the next gate line of the last gate line of the partial display region ). Referring to FIG. 2, the timing controller 400 includes a timing controller 400 and a timing controller 400. The timing controller 400 includes a timing controller 400, Off clock signal GCLK.

Accordingly, the gate driver 300 provides the scan signal only in the first partial display region 110 and provides the scan signal changed to the OFF signal after the region where the first partial display region 110 ends.

On the other hand, when there are a plurality of partial display areas on the display panel 100, the above-described driving method is repeated. 2, the timing controller 400 includes a first stage part 120 connected to the c-th gate line GLc corresponding to the first gate line among the gate lines arranged in the second partial display area 120, And provides the fourth start signal VST4 to the second comparator 304. [

The first stage unit 304 sequentially provides a scan signal from the c-th gate line GLc corresponding to the first stage unit 304 provided with the fourth start signal VST4.

The timing controller 400 is connected to the first or second stage portion corresponding to the next gate line of the d-th gate line GLd corresponding to the last gate line among the gate lines arranged in the second partial display region 120. Then, Off clock signal GCLK.

Accordingly, the gate driver 300 provides a scan signal only to the second partial display region 120, and provides a scan signal changed to an OFF signal after the region where the second partial display region 120 ends.

Through this driving method, the gate driver 300 does not provide a scan signal to all the gate lines of the display panel 100, but provides a scan signal only to some gate lines corresponding to the partial display region. Accordingly. A scan signal is not provided to the gate line corresponding to the non-display region other than the partial display region in which the image is displayed. Therefore, it is possible to eliminate the consumption current generated in the non-display area and to reduce the logic consumption current due to driving of GIP (Gate in Panel).

When a plurality of start signals VST1, VST2, VST3, and VST4 are used for one frame, if only a part of the entire area of the display panel 100 is displayed instead of one partial display area The gate driver 300 can divide the partial display region and provide a scan signal.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, But the present invention is not limited thereto.

100: display panel 110, 120: partial display area
200: Data driver 300: Gate driver
301 to 306: stage unit 310: start signal line
320: scan signal line 400: timing controller (T-CON)

Claims (12)

A display panel having a plurality of data lines and a plurality of pixels connected to the plurality of gate lines;
A data driver for providing a data voltage to the data line;
A gate driver including a stage unit for providing a scan signal to the gate line, the stage driver including a stage unit connected to a plurality of start signal lines to which a start signal is applied; And
And a timing controller for providing a start signal to the start signal line corresponding to a partial display region displayed on the display panel based on image data input from the outside
Display device.
The method according to claim 1,
The gate driver
A first stage unit including a start signal line to which a start signal VST provided by the timing controller is applied and a scan signal line to which a scan signal provided from a stage unit at a previous stage is applied,
And a second stage portion including a scan signal line to which a scan signal provided from a stage portion located at a previous stage is applied.
3. The method of claim 2,
The first stage part
A start signal line to which the start signal supplied from the timing controller is applied,
A scan signal line to which a scan signal provided from a stage portion located at a previous stage is applied,
And a logic unit for outputting to the stage unit positioned at the next stage in accordance with the start signals applied from the gate line and the start signal line.
3. The method of claim 2,
The timing controller
And a start signal (VST) is provided to a first stage part connected to a first gate line of the gate lines arranged in the partial display area or to a first stage part connected to a gate line located before the first gate line.
3. The method of claim 2,
The timing controller
And provides an off clock signal (GCLK) to a stage portion corresponding to a gate line positioned next to the gate line corresponding to the last gate line among the gate lines arranged in the partial display region.
3. The method of claim 2,
The first stage part
And sequentially provides scan signals from a gate line corresponding to the first stage section provided with the start signal, when the start signal is provided.
The method according to claim 6,
The first stage part
And changes the scan signal supplied to the gate line to an off signal when the off clock signal is provided.
The method according to claim 1,
Wherein the timing controller provides the gate driver with a plurality of start signals having different timings during one frame.
Receiving image data input from outside;
Detecting a partial display area to be displayed on the display panel from the input image data; And
And providing a first start signal to a first stage portion corresponding to a specific gate line corresponding to the detected partial display region
A method of driving a display device.
10. The method of claim 9,
Providing an off clock signal (GCLK) to a first or second stage portion corresponding to a gate line next to a gate line corresponding to a last gate line among the gate lines arranged in the partial display region And a driving circuit for driving the display device.
10. The method of claim 9,
The step of providing the first start signal
The first stage signal corresponding to the first gate line among the gate lines arranged in the partial display region through the timing controller or the first stage signal corresponding to the gate line positioned before the first gate line, To the display device.
10. The method of claim 9,
Providing a second start signal to a first stage portion corresponding to a gate line corresponding to the detected partial display region during one frame,
Sequentially providing scan signals from a gate line corresponding to a first stage portion provided with the second start signal in a gate driver,
And providing an off clock signal to the first or second stage portion corresponding to the gate line positioned next to the last gate line of the gate lines arranged in the partial display region in the gate driver A method of driving a display device.

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