JP4517758B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a plasma display panel.

A plasma display panel (hereinafter abbreviated as “panel”) is a self-luminous display device by discharge characterized by a large screen, a thin shape, and a light weight. However, it has been pointed out that the video display device using the panel consumes a large amount of power. Accordingly, various studies for improving the light emission efficiency have been made for the panel, and a power recovery circuit for reducing reactive power in the drive circuit has also been studied. Among them, a method for improving the power recovery efficiency by setting the resonance frequency of the fall time of the drive pulse for causing the panel to emit light lower than the resonance frequency of the rise time has been proposed (see Patent Document 1). .
JP 2003-15595 A

  However, if the resonance frequency of the fall time of the drive pulse is set low while keeping the drive pulse period constant, the discharge itself becomes unstable, and the video display quality may be deteriorated.

  The panel driving method of the present invention has been made in view of these problems, and aims to improve the efficiency of power recovery without deteriorating the video display quality.

In the panel driving method of the present invention, a sustain pulse is alternately applied to the scan electrode and the sustain electrode to a plasma display panel in which a discharge cell is formed at the intersection of the scan electrode, the sustain electrode and the data electrode. A driving method of a plasma display panel for displaying an image by providing a sustaining period, the driving having power recovery means for alternately applying the sustaining pulse to the scan electrode and the sustaining electrode of the plasma display panel And a sustain pulse applied to the scan electrode and the sustain electrode during the sustain period is inserted between the first sustain pulse and the first sustain pulse, and the sustain pulse voltage Vs is greater than the first sustain pulse. A second sustain pulse having a long period of clamping to the scan electrode and the sustain period with respect to the scan electrode or the sustain electrode. The first sustain pulse is alternately applied, the first sustain pulse is continuously applied a predetermined number of times, and then the second sustain pulse is inserted and applied, and the first sustain pulse is further applied. The waveform of the rising period of the sustain pulse is a half cycle of the waveform caused by resonance between the capacitance of the plasma display panel and the inductance element of the power recovery means, and the waveform of the falling period of the first sustain pulse. The waveform is a waveform of a half period of the waveform caused by resonance between the capacitance of the plasma display panel and the inductance element of the power recovery means, and the waveform of the rising period of the second sustain pulse is the plasma display panel And a waveform of a half cycle of the waveform due to resonance between the capacitance of the power recovery means and the inductance element of the power recovery means, and the second Waveform falling period of the sustain pulses is characterized in that the waveforms of less than half the period of the waveform due to the resonance of the plasma display panel capacitance between the inductance element of the power recovery means. With this method, it is possible to improve the efficiency of power recovery without degrading the video display quality.

  According to the present invention, it is possible to improve the efficiency of power recovery without degrading the video display quality.

  Hereinafter, an image display apparatus using a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of a panel used in a video display apparatus according to an embodiment of the present invention. The panel 1 is configured such that a glass front substrate 2 and a rear substrate 3 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. A plurality of data electrodes 9 covered with an insulator layer 8 are formed on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulator layer 8 between the data electrodes 9. Yes. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. Further, the front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrode 4 and the sustain electrode 5 and the data electrode 9 intersect, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon.

  FIG. 2 is an electrode array diagram of the panel. In the row direction, n scan electrodes Y1 to Yn (scan electrode 4 in FIG. 1) and n sustain electrodes X1 to Xn (sustain electrode 5 in FIG. 1) are alternately arranged, and m data electrodes in the column direction. A1 to Am (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode Yi and sustain electrode Xi (i = 1 to n) and one data electrode Aj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, since the scan electrode 4 and the sustain electrode 5 are formed in parallel with each other, a large interelectrode capacitance is formed between the scan electrode 4 and the sustain electrode 5. Exists.

  FIG. 3 is a circuit block diagram of the video display apparatus according to the embodiment of the present invention. This video display device includes a panel 1, a data driver 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield conversion unit. 20 and a power supply circuit (not shown).

  The video signal sig is converted into video data of a digital signal by the AD converter 18 and output to the scanning number conversion unit 19. The scanning number conversion unit 19 converts the video data into video data corresponding to the number of pixels of the panel 1 and outputs the video data to the subfield conversion unit 20. The subfield conversion unit 20 divides the video data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the video data for each subfield to the data driver 12. The data driver 12 converts the video data for each subfield into signals corresponding to the data electrodes A1 to Am, and drives the data electrodes A1 to Am.

  Further, the horizontal synchronization signal H and the vertical synchronization signal V are input to the timing generation circuit 15. The timing generation circuit 15 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V and supplies them to each circuit block. Scan electrode drive circuit 13 supplies a drive voltage waveform to scan electrodes Y1 to Yn based on a timing signal, and sustain electrode drive circuit 14 supplies a drive voltage waveform to sustain electrodes X1 to Xn based on a timing signal. Here, scan electrode drive circuit 13 includes sustain pulse generator 23 for generating a sustain pulse, which will be described later, and sustain electrode drive circuit 14 also includes sustain pulse generator 24. As will be described in detail later, the sustain pulse generators 23 and 24 are provided with power recovery means in order to recover the electric power associated with the charge / discharge of the interelectrode capacitance between the scan electrode 4 and the sustain electrode 5.

  Next, a driving waveform for driving the panel and its operation will be described. In the embodiment of the present invention, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period. FIG. 4 is a drive waveform diagram applied to each electrode of the panel in the embodiment of the present invention.

  In the initializing period of the first subfield, the data electrodes A1 to Am and the sustain electrodes X1 to Xn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes Y1 to Yn. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are accumulated on the scan electrodes Y1 to Yn, and positive walls on the sustain electrodes X1 to Xn and the data electrodes A1 to Am. The voltage is stored. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode. Thereafter, sustain electrodes X1 to Xn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes Y1 to Yn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage on the scan electrodes Y1 to Yn and the wall voltage on the sustain electrodes X1 to Xn are weakened, and the wall voltage on the data electrodes A1 to Am. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, the scan electrodes Y1 to Yn are temporarily held at Vr (V). Next, a positive address pulse voltage Va (V) is applied to the data electrode Ak (k = 1 to m) of the discharge cell to be displayed in the first row among the data electrodes A1 to Am, and the first row is scanned. A scan pulse voltage Vy (V) is applied to the electrode Y1. At this time, the voltage at the intersection of the data electrode Ak and the scan electrode Y1 is obtained by adding the wall voltage on the data electrode Ak and the wall voltage on the scan electrode Y1 to the externally applied voltage (Va−Vy) (V). Exceeding the discharge start voltage. An address discharge is generated between data electrode Ak and scan electrode Y1 and between sustain electrode X1 and scan electrode Y1, and a positive wall voltage is accumulated on scan electrode Y1 of the discharge cell. And a negative wall voltage is also accumulated on the data electrode Ak. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode to which the positive address pulse voltage Va (V) is not applied and the scan electrode Y1 does not exceed the discharge start voltage, no address discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, sustain electrodes X1 to Xn are returned to 0 (V), and positive sustain pulse voltage Vs (V) is applied to scan electrodes Y1 to Yn. In the discharge cell in which the address discharge has occurred at this time, the voltage between scan electrode Yi and sustain electrode Xi is the sustain pulse voltage Vs (V), and the magnitude of the wall voltage on scan electrode Yi and sustain electrode Xi. Exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode Yi and sustain electrode Xi, a negative wall voltage is accumulated on scan electrode Yi, and a positive wall voltage is accumulated on sustain electrode Xi. At this time, a positive wall voltage is also accumulated on the data electrode Ak. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage state at the end of the initialization period is maintained. Subsequently, scan electrodes Y1 to Yn are returned to 0 (V), and positive sustain pulse voltage Vs (V) is applied to sustain electrodes X1 to Xn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between the sustain electrode Xi and the scan electrode Yi exceeds the discharge start voltage, the sustain discharge occurs again between the sustain electrode Xi and the scan electrode Yi, and the sustain cell is maintained. A negative wall voltage is accumulated on the electrode Xi, and a positive wall voltage is accumulated on the scan electrode Yi. Thereafter, similarly, by applying sustain pulses corresponding to the luminance weights alternately to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn, the sustain discharge is continuously performed in the discharge cells in which the address discharge has occurred in the address period. Is called. Note that at the end of the sustain period, a so-called narrow pulse is applied between the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn to leave the positive wall charges on the data electrodes Ak and to leave the scan electrodes Y1 to Yn. The wall voltages on Yn and sustain electrodes X1 to Xn are erased. Thus, the maintenance operation in the maintenance period is completed.

  The operations in the initialization period, address period, and sustain period in the subsequent subfield are the same as those in the first subfield, and thus description thereof is omitted.

  Here, sustain pulse generators 23 and 24 of scan electrode drive circuit 13 and sustain electrode drive circuit 14 generate the sustain pulses described above during the sustain period and apply them to scan electrode 4 and sustain electrode 5, respectively. And the electric power accompanying a sustain discharge is supplied to the panel 1. FIG. However, the sustain pulse generators 23 and 24 are provided with power recovery means to recover the power associated with charge / discharge of the interelectrode capacitance between the scan electrode 4 and the sustain electrode 5 as follows.

  FIG. 5 is a circuit diagram of sustain pulse generators 23 and 24 of the video display device according to the embodiment of the present invention. Since sustain pulse generator 23 and sustain pulse generator 24 have the same configuration, sustain pulse generator 24 will be described below. The sustain pulse generator 24 includes a power recovery circuit 34 and a voltage clamp circuit 44. The power recovery circuit 34 includes a power recovery capacitor C, switching elements FET1 and FET2, backflow prevention diodes D1 and D2, and power recovery coils L1 and L2 as inductance elements. The voltage clamp circuit 44 includes a power supply VS having a voltage value of Vs (V), switching elements FET3 and FET4. The power recovery circuit 34 and the voltage clamp circuit 44 are connected to the interelectrode capacitance Cp of the panel 1, here, the sustain electrodes X1 to Xn.

  FIG. 6 is a timing chart for explaining the operation of sustain pulse generators 23 and 24 of the video display apparatus according to the embodiment of the present invention. Although FIG. 6 shows three sustain pulses, the first two are first sustain pulses, and the third sustain pulse is a second sustain pulse having a longer pulse duration than the first sustain pulse. Is shown. In the initial state of the sustain period, that is, the period T0, the output voltage of the sustain pulse generator 24 is 0 (V). At this time, the power recovery capacitor C is charged to a voltage value Vs / 2 (V) which is ½ of the power supply VS.

  First, the first sustain pulse will be described. In the rising period T1, the switching element FET1 is turned on and the switching elements FET2 to FET4 are turned off. Then, current starts to flow from the power recovery capacitor C to the interelectrode capacitance Cp through the power recovery coil L1. A resonance phenomenon occurs between the power recovery coil L1 and the interelectrode capacitance Cp, and the voltage value of the interelectrode capacitance Cp is approximately twice the voltage value Vs / 2 (V) of the power recovery capacitor C. That is, the current continues to flow until it becomes approximately Vs (V). When the half period ta (s) of this resonance waveform has elapsed, the switching element FET3 is turned on. Then, the voltage Vs (V) is applied from the power source VS to the interelectrode capacitance Cp, and the output of the sustain pulse generator 24 is clamped to Vs (V). In FIG. 6, the clamping period is indicated by a clamping period T2. In the next falling period T3, the switching elements FET1 and FET3 are turned off and the switching element FET2 is turned on. Then, a current starts to flow from the interelectrode capacitance Cp to the power recovery capacitor C via the power recovery coil L2. Then, a resonance phenomenon occurs again between the power recovery coil L2 and the interelectrode capacitance Cp, and current continues to flow until the voltage value of the interelectrode capacitance Cp becomes substantially 0 (V). When the half period tb (s) of this resonance waveform has elapsed, the switching element FET4 is turned on. Then, the interelectrode capacitance Cp is grounded, and the output of the sustain pulse generator is clamped to 0 (V). In FIG. 6, this period is indicated by a clamp period T4. The half period ta (s) and tb (s) of the resonance waveform is respectively

It is represented by

  In this way, during the period in which the interelectrode capacitor Cp is charged, that is, in the rising period T1 and the falling period T3 of the output waveform of the sustain pulse generator 24, the resonance phenomenon between the interelectrode capacitor Cp and the coil L1 or coil L2 is caused. By using this, the output waveform of the sustain pulse generator 24 is generated with almost no power consumption. Then, by setting the inductance of the coil L2 to be larger than the inductance of the coil L1, the frequency of the resonance waveform in the falling period of the first sustain pulse is lower than the frequency of the resonance waveform in the rising period of the first sustain pulse. It is set.

  Here, the reason why the period of the resonance waveform in the fall period T3 of the first sustain pulse is set longer than the period of the resonance waveform in the rise period T1 of the first sustain pulse is as follows. It is known that if the period of resonance is set long in power recovery, the power recovery efficiency associated with charging / discharging of the interelectrode capacitance Cp is improved. However, since it is necessary to generate a sustain discharge after raising the sustain pulse and applying a sufficient voltage between the scan electrode 4 and the sustain electrode 5, the rise period T1 cannot be set too long. On the other hand, since the falling period T3 is not directly related to the sustain discharge, it can be set as long as the first sustain pulse, so that the power recovery efficiency in the charge / discharge of the interelectrode capacitance Cp can be achieved. Can be raised.

  However, if the period T1 is set to be long, the period T2 for generating the sustain discharge is shortened. Then, the falling period T3 starts before the wall charges are sufficiently formed, and as a result, the wall charges necessary for continuing the subsequent sustain discharge are insufficient, and the sustain discharge is stopped and the video display quality is improved. May be damaged. Therefore, in the present embodiment, not all the sustain pulses are set as the first sustain pulse, but when the first sustain pulse is continuously applied at most a predetermined number of times, the following sustain pulse will be described. By inserting the second sustain pulse, the deterioration of the image display quality is prevented.

Next, the second sustain pulse shown in FIG. 6 will be described. The period T5 and the period T6 are the same as the first sustain pulse. That is, in the rising period T5, the switching element FET1 is turned on and the switching elements FET2 to FET4 are turned off. Then, a resonance phenomenon occurs between the power recovery coil L1 and the interelectrode capacitance Cp, and a current flows until the voltage value of the interelectrode capacitance Cp becomes approximately Vs (V). The time of the period T5 is the 1/2 period ta (s) of the resonance waveform as in the first sustain pulse. In the subsequent clamp period T6, the switching element FET3 is turned on. Then, similarly to the first sustain pulse, the voltage Vs (V) is applied from the power source VS to the interelectrode capacitance Cp, and the output of the sustain pulse generator 24 is clamped to Vs (V). However, the clamp period T6, which is the duration of the second sustain pulse , is set longer than the clamp period T2 of the first sustain pulse. This is because the period of the falling period T7 described next is set shorter than the period T3, and thus the period T6 can be set longer.

  In the next falling period T7, the switching elements FET1 and FET3 are turned off and the switching element FET2 is turned on. Then, current begins to flow from the interelectrode capacitance Cp to the power recovery capacitor C via the power recovery coil L2, and a resonance phenomenon occurs again between the power recovery coil L2 and the interelectrode capacitance Cp. However, the period T7 is different from the period T3 because the falling period T7 is not continued until the voltage value of the interelectrode capacitance Cp becomes substantially 0 (V), but the half period tb (s) of this resonance waveform. ) The switching element FET4 was previously turned on to end the period T7. That is, the waveform of the falling period T7 is created as a waveform that is less than ½ period of the resonance waveform of the interelectrode capacitance Cp and the inductance element.

  In this way, by inserting the second sustain pulse having a long pulse duration, there is no possibility that the sustain discharge stops. That is, even if the wall charge is reduced due to the continuous sustain discharge of the first sustain pulse with good power recovery efficiency, sufficient wall charge can be obtained by inserting the second sustain pulse before the sustain discharge stops. Therefore, it is possible to continue the stable sustain discharge. As described above, when the first sustain pulse is continuously applied a predetermined number of times, the second sustain pulse is inserted as the next sustain pulse, thereby efficiently recovering the power without deteriorating the video display quality. Is possible. Note that if the predetermined number of times is too large, the sustain discharge may stop, and if it is too small, the power recovery efficiency decreases. Therefore, it is desirable to set the number appropriately according to the panel characteristics and driving conditions. In the present embodiment, the predetermined number of times is set to 3 to 5 times.

  Also, when the time of the falling period T3 of the first sustain pulse cannot be set longer than the time of the rising period T1 due to an increase in the number of subfields, an increase in the writing time accompanying an increase in the number of pixels, or other reasons. Even if it exists, it is possible to apply this invention. That is, the waveform of the falling period is less than ½ period of the resonance waveform of the inter-electrode capacitance of the panel and the inductance element, the second sustain pulse having a long pulse duration is created, and the first sustain pulse is increased. In both cases, the second sustain pulse may be inserted as the next sustain pulse when applied a predetermined number of times.

  Thus, according to the present invention, the efficiency of power recovery can be improved without degrading the video display quality.

  The panel driving method of the present invention can improve the efficiency of power recovery without degrading the video display quality, and is useful as a video display device or the like.

1 is an exploded perspective view showing a structure of a panel used in a video display device according to an embodiment of the present invention. Electrode arrangement of the panel Circuit block diagram of the video display device Drive waveform diagram applied to each electrode of the panel Circuit diagram of sustain pulse generator of the video display device Timing chart for explaining the operation of the sustain pulse generator of the video display device

Explanation of symbols

1 Panel 4 Scan Electrode 5 Sustain Electrode 9 Data Electrode 13 Scan Electrode Drive Circuit 14 Sustain Electrode Drive Circuit 23, 24 Sustain Pulse Generator C Capacitor Cp Interelectrode Capacitance FET1-FET4 Switching Element L1, L2 Coil

Claims (1)

A plasma display panel having discharge cells formed at intersections of scan electrodes, sustain electrodes, and data electrodes is provided with a sustain period in which sustain pulses are alternately applied to the scan electrodes and the sustain electrodes to display an image. A method for driving a plasma display panel, comprising: a drive circuit having power recovery means for alternately applying the sustain pulse to the scan electrode and the sustain electrode of the plasma display panel, and scanning in the sustain period The sustain pulse applied to the electrode and the sustain electrode is a second sustain pulse and a second period inserted between the first sustain pulse and clamped to the sustain pulse voltage Vs longer than the first sustain pulse. And the first sustain pulse is alternately applied to the scan electrode or the sustain electrode during the sustain period. In addition, the first sustain pulse is continuously applied a predetermined number of times, and then the second sustain pulse is inserted and applied, and the waveform of the rising period of the first sustain pulse is The waveform of the period of the first sustain pulse is a half cycle of the waveform due to resonance between the capacitance of the plasma display panel and the inductance element of the power recovery means, and the waveform of the falling period of the first sustain pulse is The waveform of a half cycle of the waveform due to resonance between the capacitance and the inductance element of the power recovery means, and the waveform of the rising period of the second sustain pulse is the capacitance of the plasma display panel and the power recovery means. The waveform is a half cycle of the waveform due to resonance with the inductance element, and the falling period of the second sustain pulse is Form, a method of driving a plasma display panel, wherein the waveforms of less than half the period of the waveform due to the resonance of the inductance element of the plasma display panel capacitance to the power recovery means.

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