JP3628195B2 - Plasma display panel device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display panel device, and more particularly to a plasma display panel device capable of increasing the number of gradations of luminance by shortening an address discharge period and increasing the number of subframes in one frame and driving thereof. Regarding the method.
[0002]
[Prior art]
Plasma display panel devices (hereinafter referred to as PDP devices) are attracting attention as flat displays having a large screen and a wide viewing angle. In particular, recently developed three-electrode, surface discharge, AC drive type PDP devices are capable of full-color display, and are expected to be widely used in television receivers, computer display devices, and the like.
[0003]
FIG. 12 is a diagram illustrating a driving waveform of a conventional PDP. The three-electrode / surface discharge / AC type PDP has an address electrode A on one substrate, and an X electrode and a Y electrode arranged on the other substrate in a direction perpendicular to the address electrode. The Y electrode is also referred to as a scan electrode because a scan pulse is applied. As shown in the figure, the driving method of the PDP generally includes a reset period RST for performing full writing and full erasing, an address period ADD for selectively discharging according to display data, and a cell lit in the address period. It consists of a sustain discharge period SUS in which sustain discharge is performed.
[0004]
In the reset period RST, all the Y electrodes are kept at the ground potential, and a high voltage write pulse Vs + Vw is applied to all the X electrodes. By applying the write pulse, all cells are turned on. Then, at the fall when the application of the write pulse ends, the entire surface discharge occurs again due to the electric field generated by the charges accumulated by the entire surface discharge, and the accumulation of wall charges in all the cells is eliminated.
[0005]
In the subsequent address period ADD, a negative scan pulse -Vy is sequentially applied to the Y electrode, and a positive address pulse Va is selectively applied to the address electrode A in accordance with display data in synchronization therewith. As a result, the combined voltage of both pulses -Vy and Va is applied between the address electrode and the Y electrode, and an address discharge is generated. As a result, wall charges are accumulated in the lit cells. In the sustain discharge period SUS, a sustain discharge pulse Vs is alternately applied to the X electrode and the Y electrode, thereby generating a plurality of sustain discharges for the cells in which the wall charges are accumulated. The brightness of the cell is controlled by the number of times of sustain discharge.
[0006]
FIG. 12 shows a reset period, an address period, and a sustain period, and one subfield is configured by these periods. In one frame, the sustain discharge period is composed of a plurality of subfields weighted at a predetermined ratio, and the luminance according to the display data can be displayed by selectively lighting the subfields. Therefore, as the number of subfields existing in one frame period increases, the number of luminance gradations can be increased, and the change in brightness can be displayed with higher quality.
[0007]
[Problems to be solved by the invention]
For example, in the case of 60 Hz, one frame period is limited to about 16.5 ms. Therefore, the number of subframes that can be executed within the one frame period is also limited. As shown in FIG. 12, the subframe period includes a reset period, an address period, and a sustain discharge period. In the sustain discharge period, the total number of sustain discharges in one frame period corresponds to the maximum luminance value. It has been decided. Also, the reset period must be performed once at the beginning or end of each subfield. In the address period, a scan pulse -Vy is sequentially or randomly applied to the Y electrode, which is a scan electrode, and an address pulse Va for each display line is applied in synchronization therewith, thereby lighting a predetermined cell. .
[0008]
In the conventional example, since the scan pulse -Vy is applied to the Y electrode in a time-division manner without overlapping, when there are 480 scan lines, the address period in one subframe is equal to the scan pulse. Time (3 μs) × 480 time is required. Therefore, when there are 8 subframes in one frame, the total address period reaches 11.52 ms.
[0009]
As described above, in the conventional driving method, the address period is relatively long, and the number of subframes that can be executed in one frame is limited, and it is difficult to increase the number of luminance gradations.
[0010]
Accordingly, an object of the present invention is to provide a plasma display panel apparatus in which the address period in a subframe is shortened and the number of subframes in one frame is increased.
[0011]
It is another object of the present invention to provide a plasma display panel device that shortens an address period in a sub-frame and reduces discharge interference during address discharge.
[0012]
[Means for Solving the Problems]
The present invention is characterized in that when the address electrodes are driven in accordance with the display data, a scan pulse is applied to the scan electrodes, and when the cells at the intersections of the two electrodes are turned on, the continuous scan pulses are partially overlapped. To do. As a result, the address period for driving a plurality of scan electrodes can be shortened, the time required for subframes can be shortened, and the number of subframes in one frame can be increased.
[0013]
Furthermore, the present invention comprises a scan pulse that is partially overlapped with a first period having a dischargeable voltage and a second period having a lower voltage or a high impedance state. With respect to the scan pulse, at least the temporal overlap between the first periods is eliminated, and the second period and the subsequent scan pulse are overlapped. Discharging is completed within the first period, and wall charges are drawn onto the scan electrodes in the second period, so that the operation in the address period is not hindered.
[0014]
To achieve the above object, the present invention provides a plurality of address electrodes provided in parallel, a plurality of scan electrodes provided in parallel in a direction intersecting with the address electrodes, the address electrodes and the scan electrodes, In the plasma display panel device having a discharge space between,
An address driver for driving the address electrodes in accordance with display data;
And a scanning driver for applying the continuous scanning pulses to the plurality of scanning electrodes in a predetermined order at a timing of overlapping each other.
[0015]
According to the above invention, the address period can be shortened, the subframe period can be shortened, the number of subframes in one frame can be increased, and the number of luminance gradations can be increased.
[0016]
Furthermore, in the above invention, the scan pulse is between a first period in which a first voltage is applied between the address electrodes and the address electrode after the first period. A second period of applying a second voltage lower than the first voltage,
The continuous scan pulses do not overlap at least during the first period.
[0017]
Furthermore, in the above invention, the scan pulse is in a high impedance state after a first period in which a first voltage is applied to the address electrode and after the first period. And a second period of time
The continuous scan pulses do not overlap at least during the first period.
[0018]
In the above invention, the scan pulse is sequentially applied to the scan electrodes arranged in an odd-numbered or even-numbered manner, or a single-phase drive method in which the scan pulses are sequentially applied to the arranged scan electrodes, Thereafter, the scan electrodes arranged in an even or odd number are applied in a two-phase drive system in which they are sequentially applied. Or it applies by a random drive system. In particular, in the case of the two-phase driving method or the random driving method, it is possible to prevent interference between scan electrodes that are successively scanned.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention. In the following embodiments, a three-electrode surface discharge AC type PDP device will be described as an example, but the present invention can be applied to PDP devices having various configurations.
[0020]
FIG. 1 is a plan view of a three-electrode / surface discharge / AC type PDP panel according to an embodiment. The PDP shown in FIG. 1 is provided with a plurality of address electrodes 12 arranged in a vertical direction on the rear glass substrate 10, ribs (partition walls) 20 are provided between the address electrodes 12, and the front glass substrate 14 is horizontal. X electrodes 16 and Y electrodes 18 arranged alternately in the direction are provided. The X electrode 16 is normally connected to a plurality of electrodes in common and is driven by an X common driver described later. The Y electrode has a function of a scan electrode to which a scan pulse (scan pulse) is applied one after another in the address period, and a function of a display electrode or a sustain discharge electrode to which a sustain discharge pulse is commonly applied in the sustain discharge period.
[0021]
2 and 3 are cross-sectional views of the PDP of FIG. 2 shows a cross-sectional structure along the X or Y electrode, and FIG. 3 shows a cross-sectional structure along the address electrode. Address electrodes 12 are provided on the back glass substrate 10, and a dielectric layer 22 and ribs (partition walls) 20 are provided thereon. A phosphor 24 is provided on the dielectric layer 22 and between the ribs 20. The front glass substrate 14 is provided so as to separate the rear glass substrate 10 from the discharge space. An X electrode 16 and a Y electrode 18 are provided on the front glass substrate 14, and a dielectric layer 22 is provided thereon. A protective layer made of MgO is provided on the dielectric layer 22 of the front glass substrate. As shown in FIG. 2, a counter electrode capacitance Cg is parasitically formed between the address electrode 12 and the Y electrode 18, and between the X electrode 16 and the Y electrode 18, A similar interelectrode capacitance Ca is formed parasitically.
[0022]
FIG. 4 is a block diagram of the driving circuit of the PDP shown in FIGS. The address electrode provided on the panel 1 is driven by the address driver 2, the X electrode is driven by the X electrode common driver 4, the Y electrode is driven by the scan driver 6 during the address period, and the Y electrode is common during the sustain discharge period. It is driven by the driver 8. Each driver is supplied with a control signal from the control circuit 30 and controlled in its driving operation.
[0023]
The control circuit 30 includes a display data control unit 32, a scan driver control unit 34, a common driver control unit 36, and the like. From a computer, a tuner, etc., a clock CLK, display data DATA, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync. Supplied etc. The display data control unit 32 receives the display data DATA, performs necessary A / D conversion, gradation adjustment, data conversion, and the like, and supplies a display data signal to the address driver 2. Further, the scan driver control unit 34 supplies a scan control signal to the scan driver 6 in synchronization with the synchronization signal. Further, the common driver control unit 36 generates a control signal for applying a write pulse and an erase pulse during the reset period and for applying a sustain pulse during the sustain discharge period, and supplies the control signals to the drivers 4 and 8.
[0024]
FIG. 5 is a diagram for explaining the discharge phenomenon. The example of FIG. 5 shows the discharge and the formation of wall charges when the scan pulse -Vy is continuously applied to the scan electrodes Y1, Y2. While applying the address pulse Va to the address electrode A, the scan pulse -Vy is applied to the Y electrode which is the scan electrode. At that time, a high potential Va is applied to the X electrode. As a result, at time t1, voltage Va + Vy is applied between the address electrode and the Y electrode. In response to the application of the pulse from the drive circuit, the parasitic capacitance of the electrode is charged, and at time t2 after a certain delay time, the discharge start voltage is exceeded between the address electrode and the Y electrode of the cell, and the discharge starts. To do. At time t3, charges in the discharge space generated by the discharge are started to be drawn to the address electrode, the X electrode, and the Y electrode, respectively. At time t4, the wall charges of each polarity are attracted and adsorbed according to the potential of each electrode. At that time, the potential difference between the electrodes in the panel does not occur due to the attracted wall charges, and the discharge ends. Then, the application of the scan pulse -Vy is completed at time t5.
[0025]
As shown in FIG. 5, when the scan pulse applied to the Y electrode is set to a low pulse as shown by a broken line, the voltage applied between the address electrode and the Y electrode is lowered, and the discharge and generation of wall charges are generated as shown by the broken line. Become slow. In other words, if the scanning pulse −Vy and the address electrode Va of the address electrode are appropriately selected, the discharge is terminated in the first half of the period from the time t1 to the time t5 when the scanning pulse is applied, It means that the charge generated by the discharge in the latter half can be drawn to the electrode and terminated. The present invention has been made based on such findings.
[0026]
FIG. 6 is a diagram for explaining the discharge phenomenon of the present invention. As shown in FIG. 5, discharge occurs in the first half of the scanning pulse application period, and positive and negative charges generated by the discharge are attracted to the respective electrodes in the second half. As shown by the electrodes Y1 and Y2, the scan pulse is divided into a first period T1 having a voltage −Vy1 necessary for discharging, and a second period having a slightly lower voltage −Vy2 necessary for attracting generated charges. Consists of. In the first period T1, the scan pulses are not overlapped with each other, and the second period T2 of the scan pulse and the first period T1 of the subsequent scan pulse are overlapped.
[0027]
When the scan pulse is applied to the Y electrodes Y1 and Y2 in this manner, a discharge is generated in the period T1 with respect to the application of the scan pulse to the Y electrode Y1, and the positive charge generated in the period T2 is a dielectric on the Y electrode Y1. It is attracted to the surface of the body layer or MgO layer and left as a wall charge. Then, during the period T2, while the voltage −Vy2 is applied to the Y electrode Y1 and the charge is being attracted, the voltage −Vy1 is applied to the Y electrode Y2, and the voltage between the address electrode and the Y electrode Y2 is increased. A discharge occurs. Further, although not shown, while the next discharge is generated by the subsequent scanning pulse, positive charge is attracted to the Y electrode Y2 by the voltage −Vy2 in the period T2.
[0028]
As described above, the second period of the preceding scan pulse and the subsequent scan pulse are temporally overlapped in the first period in which the discharge of the scan pulse is generated and the second period in which the generated charge is attracted. The application period of the address pulse Va to one scan electrode can be shortened without repeating the discharge phenomenon at each scan electrode. However, the respective first periods are prevented from overlapping each other to prevent erroneous discharge.
[0029]
An example of another scanning pulse is shown on the Y electrodes Y3 and Y4 in FIG. In the first half period T1, this scan pulse is a pulse having the voltage −Vy1 necessary for the discharge in the same manner as described above, and in the second half period T2, the Y electrodes Y3 and Y4 are brought into a high impedance or open state. . In this second half T2, since the Y electrode is in a high impedance state, no discharge current flows, and positive charges generated by the first half of the discharge are attracted to the Y electrode, and the potential gradually approaches the ground potential GND. .
[0030]
As in the case of the Y electrodes Y1 and Y2, the address pulse for one scan electrode is overlapped by overlapping the scan pulse period T2 to the Y electrode Y3 and the subsequent scan pulse period T1 to the Y electrode Y4. The application period of Va can be shortened.
[0031]
In the method shown in FIG. 6, it is necessary to generate a discharge between the next scan electrode and the address electrode while the electric charge due to the previously generated discharge exists in the discharge space. Therefore, it is desirable that the positions of the scan electrodes to which the preceding and following scan pulses are applied are as far apart as possible. For this purpose, for example, a sequential scanning pulse is applied to odd-numbered Y electrodes, and then a sequential scanning pulse is applied to even-numbered Y electrodes, or scanning pulses are applied to Y electrodes in a random order. A random scanning method is preferable. If the positions of successive discharge cells are sufficiently separated from each other, they will not interfere with each other, and no malfunction will occur even if scanning pulses are partially overlapped in time.
[0032]
FIG. 7 is a diagram showing drive waveforms in the first embodiment. In this embodiment, the scan pulse applied to the Y electrode includes a period having a voltage −Vy1 that is large enough to generate a discharge, and a period having a lower voltage −Vy2 for attracting charges generated by the discharge thereafter. And the period of the voltage −Vy2 and the next scan pulse overlap in time. However, the periods of the voltage −Vy1 are not overlapped with each other. Further, the scanning pulse is applied by a single-phase driving method in which the scanning pulse is sequentially applied to the Y electrode.
[0033]
The reset period RST and the sustain period SUS in this embodiment have the same drive waveforms as in the conventional example of FIG. Then, in the address period ADD, the scan pulses preceding and following a part of the scan pulse are temporally overlapped to shorten the period of the address pulse Va for one scan.
[0034]
In the example of FIG. 7, the application period of the voltage −Vy1 for discharging is 3/2 μs = 1.5 μs. Therefore, in the case of 480 lines, the total of the address periods is 1. 5 μs × 480 × 8 = 5.76 ms, which is shorter than the conventional example. That is, if the sustain period SUS requires 400 sustain discharges in one frame, the time is 6 μs × 400 = 2.4 ms, and the reset period RST requires 0.3 ms × 8 = 2.4 ms, 1 The total frame time is reduced to 10.56 ms. In the case of 60 Hz, since the time for one frame is about 16.5 ms, the number of subframes can be further increased according to the driving method of FIG. By increasing the number of subframes, the number of luminance gradations can be increased, and the image quality can be improved. That is, as shown in FIG. 8 showing the number of subframes for comparing the conventional example and the present invention, one frame can be changed from the conventional 8 subframes to, for example, 10 subframes.
[0035]
FIG. 9 is a diagram illustrating a drive circuit according to the present embodiment. FIG. 9 shows the Y scanning driver 6, the Y common driver 8, and the X common driver 4. In order to realize the drive waveform shown in FIG. 7, on the Y driver side, CMOS transistors Q1, Q2 for scanning, diodes D1, D2, a transistor Q3 for applying a voltage Vs for sustain discharge, Transistors Q4 and Q5 for applying scan pulse voltages -Vy1 and -Vy2 and a transistor Q6 for applying a ground potential GND are further provided. Scanning transistors Q1 and Q2 and transistors Q4 and Q5 for applying scanning pulse voltages -Vy1 and -Vy2 are provided for each Y electrode, and other transistors are provided in common for the Y electrodes.
[0036]
Further, the X driver 4 is supplied with the transistor Q7 for applying the voltage Vax in the address period, the transistor Q8 for applying the sustain discharge voltage Vs in the sustain period, the transistor Q9 connected to the ground potential, and the full write voltage Vs + Vw. Transistor Q10. The conduction and non-conduction of these transistors are controlled by a control signal from the control circuit 30.
[0037]
In the reset period RST, the transistor Q10 is turned on, the full write voltage Vs + Vw is applied to all the X electrodes, the transistor Q6 is turned on, and all the Y electrodes are set to the ground potential via the diode D2.
[0038]
In the address period ADD, the transistor Q7 is turned on to apply the voltage Va to the X electrode. On the other hand, on the Y electrode side, the transistor Q6 is turned on to supply the ground potential to the transistor Q1, and the scanning driver transistor Q1 is turned on to bring the Y electrode to the ground potential. For the Y electrode to be scanned, the transistor Q2 is turned on instead of the transistor Q1, and the first scan pulse voltage -Vy1 is applied to the Y electrode while the transistor Q5 is turned on. Then, while the transistor Q2 is conducting, the transistor Q5 is turned off and then the transistor Q4 is turned on, and the voltage -Vy2 of the second half scan pulse is supplied to the Y electrode. At this time, the diodes D1 and D2 are reversely biased.
[0039]
Next, in the sustain period, the conduction of the transistor Q3 in the Y common driver circuit 8 and the conduction of the transistor Q9 in the X common driver circuit 4 are simultaneously performed. Thereby, the sustain discharge pulse Vs is applied to all Y electrodes via the diode D1. Thereafter, the transistor Q8 in the X common driver circuit 4 and the transistor Q6 in the Y common driver circuit 8 are simultaneously turned on. Thereby, the sustain discharge pulse Vs is applied to all the X electrodes. By alternately performing the above operation, the sustain discharge pulse Vs is alternately applied to the Y electrode and the X electrode.
[0040]
FIG. 10 is a diagram showing drive waveforms in the second embodiment. Also in this example, the scan pulse applied to the Y electrode has a discharge voltage -Vy1 and a charge drawing voltage -Vy2, and a part of the scan pulse is temporally similar to the first embodiment. Overlap. However, in this example, in the address period ADD, the scan pulse is sequentially applied to the odd-numbered Y electrodes, and then the scan pulse is sequentially applied to the even-numbered Y electrodes. Therefore, in the address period ADD, the voltage Va is applied to the odd-numbered X electrodes in the first half, and the voltage Va is applied to the even-numbered X electrodes in the second half. The order of the odd number and the even number may be reversed.
[0041]
Since a part of the scan pulse is temporally overlapped to shorten the address period, in the subsequent address discharge, in the cell region between the previous scan electrode (Y electrode) and the address electrode, The electric charge is being attracted. Therefore, it is necessary to prevent this uncharged charge from being drawn to the Y electrode that has been scanned next by mistake. As in the second embodiment, when the two-phase driving method is adopted, the scanning electrodes (Y electrodes) that move forward and backward are at positions that are sufficiently separated from each other, and there is no interference with each other. Can be prevented.
[0042]
In the case of the second embodiment, the odd-numbered X electrodes and the even-numbered Y electrodes are connected in common and driven by the respective common drivers. In addition, the scanning of the Y electrode is supplied in rapid succession by a control signal from the control circuit 30. It should be noted that the same effect can be expected even in a three-phase drive system that sequentially scans the 3n + 1th Y electrode, the 3n + 2th Y electrode, and the 3n + 3rd Y electrode. Further, a random driving method in which the Y electrodes are randomly driven may be used.
[0043]
FIG. 11 is a diagram showing drive waveforms in the third embodiment. This example is an example in which the scanning pulse given to the Y electrodes Y3 and Y4 in FIG. 6 is given by the single-phase driving method. In this example, as described with reference to FIG. 6, the voltage -Vy1 necessary for the discharge is supplied to the Y electrode in the first half of the scan pulse, and the Y electrode is set to a high impedance state or an open state in the second half. The second half and the first half of successive scanning pulses overlap in time. For this purpose, in the drive circuit shown in FIG. 9, the transistor Q4 is turned on in the first half of the scanning period in which the transistor Q2 is turned on, and the transistor Q4 is turned off in the second half to bring the Y electrode into a high impedance state. The Y electrode is in an open state where it is not connected anywhere, and the potential gradually approaches the ground level while attracting positive charges in the gas space. At the end of the scanning period, the transistor Q2 is turned off and the transistor Q1 is turned on to raise the Y electrode to the ground potential.
[0044]
The scan pulse of the third embodiment can be applied to the Y electrode by the two-phase driving method as in the second embodiment. In such a case, since continuous scanning pulses are applied to the Y electrodes that are spaced apart from each other, mutual interference can be reduced. Of course, a three-phase driving method or a random driving method may be used.
[0045]
【The invention's effect】
As described above, according to the present invention, in the address period, a part of the scan pulse is temporally overlapped and applied to the scan electrode, so that the entire address period can be shortened. Therefore, the time required for one subframe can be shortened, the number of subframes in one frame period can be increased, and the number of luminance gradations can be increased.
[Brief description of the drawings]
FIG. 1 is a plan view of a three-electrode, surface discharge, AC type PDP panel in an embodiment.
FIG. 2 is a cross-sectional view of the PDP in FIG.
FIG. 3 is a cross-sectional view of the PDP in FIG.
4 is a block diagram of a driving circuit for the PDP shown in FIGS.
FIG. 5 is a diagram for explaining a discharge phenomenon.
FIG. 6 is a diagram for explaining a discharge phenomenon of the present invention.
FIG. 7 is a diagram showing drive waveforms in the first embodiment.
FIG. 8 is a diagram showing the number of subframes for comparing a conventional example with the present invention.
FIG. 9 is a diagram illustrating a drive circuit according to the present embodiment.
FIG. 10 is a diagram showing drive waveforms in the second embodiment.
FIG. 11 is a diagram showing drive waveforms in the third embodiment.
FIG. 12 is a diagram showing a driving waveform of a conventional PDP.
[Explanation of symbols]
12 Address electrode 16 X electrode 18 Y electrode, Scan electrodes 4, 6, 8 Electrode driver 30 Control circuit

Claims (10)

In a plasma display panel device having a plurality of address electrodes provided in parallel, a plurality of scan electrodes provided in parallel in a direction intersecting the address electrodes, and a discharge space between the address electrodes and the scan electrodes,
An address driver for driving the address electrodes in accordance with display data;
Wherein the plurality of scan electrodes, possess a scanning driver for applying a predetermined order, and at the timing overlap each other said scanning successive pulses,
The scan pulse is after the first period in which a first voltage required for discharge is applied to the address electrode and after the first period and between the address electrode. the plasma display panel device, characterized by chromatic and a second period for applying a lower than voltage second voltage. 2. The plasma display panel apparatus according to claim 1, wherein the continuous scanning pulses do not overlap at least in the first period. 3. The plasma display panel device according to claim 2, wherein the second voltage is a voltage that does not cause a discharge between the address electrode and the scan electrode. In a plasma display panel device having a plurality of address electrodes provided in parallel, a plurality of scan electrodes provided in parallel in a direction intersecting the address electrodes, and a discharge space between the address electrodes and the scan electrodes,
An address driver for driving the address electrodes in accordance with display data;
A scanning driver that applies the scan pulses to the plurality of scan electrodes in a predetermined order and at a timing at which the scan pulses overlap with each other;
The scan pulse includes a first period in which a first voltage is applied to the address electrode, and a second period in which the scan electrode is in a high impedance state after the first period. The plasma display panel device is characterized in that the continuous scanning pulses do not overlap at least in the first period. 5. The plasma display panel device according to claim 4, wherein the first voltage is a voltage at which a discharge is generated between the address electrode and the scan electrode. 6. The plasma display panel device according to claim 1, wherein the scan pulse is sequentially applied to the arrayed scan electrodes. 6. The plasma display panel device according to claim 1, wherein the scan pulse is randomly applied to the arranged scan electrodes. In a plasma display panel device having a plurality of address electrodes provided in parallel, a plurality of scan electrodes provided in parallel in a direction intersecting the address electrodes, and a discharge space between the address electrodes and the scan electrodes,
An address driver for driving the address electrodes in accordance with display data;
A scanning driver that applies the scan pulses to the plurality of scan electrodes in a predetermined order and at a timing at which the scan pulses overlap with each other;
The scan pulse is sequentially applied to the scan electrodes arranged in an odd number or an even number, and then sequentially applied to the scan electrodes arranged in an even number or an odd number. Plasma display panel device. 9. The address period in which the scan pulse is applied to the scan electrode to generate a discharge in accordance with the display data, and the sustain discharge for a predetermined period with respect to the cells discharged during the address period. A plasma display panel device characterized in that a gradation display of luminance based on the sustain discharge period is performed by repeating a subframe having a sustain discharge period for generating a plurality of times. Driving method of plasma display panel having a plurality of address electrodes provided in parallel, a plurality of scan electrodes provided in parallel in a direction intersecting with the address electrodes, and a discharge space between the address electrodes and the scan electrodes In
The address electrodes are driven in accordance with display data, and the scan electrodes are applied to the plurality of scan electrodes in a predetermined order and at a timing that overlaps each other ,
The scan pulse is after the first period in which a first voltage required for discharge is applied to the address electrode and after the first period and between the address electrode. the driving method of a plasma display panel, which comprises organic and a second period for applying a lower than voltage second voltage.

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