JP4501509B2

JP4501509B2 - FET driving device and method for controlling FET driving voltage

Info

Publication number: JP4501509B2
Application number: JP2004114665A
Authority: JP
Inventors: 和重横田; 栄二鶴田
Original assignee: Nissan Motor Co Ltd
Current assignee: Nissan Motor Co Ltd
Priority date: 2004-04-08
Filing date: 2004-04-08
Publication date: 2010-07-14
Anticipated expiration: 2024-04-08
Also published as: JP2005304144A

Description

本発明は、ＮチャンネルＦＥＴをハイサイドにて駆動するＦＥＴ駆動装置およびＦＥＴ駆動電圧の制御方法に関する。 The present invention relates to an FET drive device for driving an N-channel FET on the high side and a method for controlling an FET drive voltage.

従来、負荷を、負荷の上流側に設けられたＮチャンネルＦＥＴ（以下、ＦＥＴと称する）でオン、オフするいわゆるハイサイドスイッチに関し、電源電圧をスイッチングレギュレータによって昇圧するとともに一定電圧に変換した上で、ＦＥＴのゲート端子に印加するよう構成したＦＥＴ駆動装置が知られている。
特開２００２−２３８２５１号公報特開２００３−１８００７２号公報 Conventionally, with respect to a so-called high side switch in which a load is turned on and off by an N-channel FET (hereinafter referred to as FET) provided on the upstream side of the load, the power supply voltage is boosted by a switching regulator and converted to a constant voltage. An FET driving device configured to be applied to the gate terminal of an FET is known.
JP 2002-238251 A JP 2003-180072 A

しかしながらこのような従来のＦＥＴ駆動装置においては、ＦＥＴのゲート端子にはスイッチングレギュレータによって電源電圧の変動によらず常に一定の電圧が印加されている。これによりスイッチングレギュレータの制御端子への入力電圧が何かしらの要因で変動し高くなった場合には、ＦＥＴがオンされたときに、ＦＥＴのソース端子の電位が電源電圧に伴って高くなるので、ＦＥＴのゲート、ソース端子間の電圧が所定値未満となってしまい、ＦＥＴのオン状態を維持できなかったり、あるいは完全なオン状態とならずに熱を発生したり、安定性に欠けてしまうという問題があった。 However, in such a conventional FET driving device, a constant voltage is always applied to the gate terminal of the FET by the switching regulator regardless of fluctuations in the power supply voltage. As a result, when the input voltage to the control terminal of the switching regulator fluctuates and becomes high for some reason, when the FET is turned on, the potential of the source terminal of the FET increases with the power supply voltage. The voltage between the gate and source terminals of the FET becomes less than a predetermined value, and the FET cannot be kept on, generate heat without being completely turned on, or lack stability. was there.

本発明は、上記の問題点を解決するために、スイッチングレギュレータの制御端子への入力電圧の変動によらず安定してＦＥＴを駆動するＦＥＴ駆動装置を提供することを目的とする。 In order to solve the above-described problems, an object of the present invention is to provide an FET drive device that stably drives an FET regardless of fluctuations in an input voltage to a control terminal of a switching regulator.

電源と負荷の間であって負荷の上流側に接続されたＮチャンネルＦＥＴを駆動するＦＥＴ駆動装置において、前記電源の基準電位と同一の基準電位を有し前記電源の電源電圧を昇圧して前記ＦＥＴを駆動するためのＦＥＴ駆動電圧を生成するスイッチングレギュレータと、ゲートオンオフ信号に従って前記ＦＥＴのゲートに前記ＦＥＴ駆動電圧を供給するか否かを切り換えるスイッチと、電源電圧とスイッチングレギュレータの出力電圧との電圧差が、所定の第１の閾値を下回ったことを検出した場合、スイッチングレギュレータの出力電圧を増加させるようにスイッチングレギュレータを制御するスイッチングレギュレータ制御手段と、を備えるものとした。 In an FET driving apparatus for driving an N-channel FET connected between a power source and a load and connected to the upstream side of the load, the power source voltage of the power source is boosted by having the same reference potential as the reference potential of the power source. A switching regulator for generating an FET driving voltage for driving the FET , a switch for switching whether to supply the FET driving voltage to the gate of the FET according to a gate on / off signal, a power supply voltage and an output voltage of the switching regulator voltage difference, when it is detected that falls below a predetermined first threshold value, and shall be provided with a switching regulator controller for controlling the switching regulator to increase the output voltage of the switching regulator.

本発明では、スイッチングレギュレータの制御端子への入力電圧が何らかの要因で変動して高くなり、スイッチングレギュレータが出力電圧を低下させるように制御したとき、スイッチングレギュレータ制御手段が、電源電圧とスイッチングレギュレータの出力電圧との電圧差が所定の第１の閾値を下回ったことを検出し、スイッチングレギュレータの出力電圧を増加させるようにスイッチングレギュレータを制御するので、ＦＥＴのゲート、ソース端子間の電圧を所定値以上に保つことができる。 In the present invention, when the input voltage to the control terminal of the switching regulator fluctuates and increases for some reason and the switching regulator is controlled to decrease the output voltage, the switching regulator control means provides the power supply voltage and the output of the switching regulator. Since it detects that the voltage difference from the voltage has fallen below the predetermined first threshold and increases the output voltage of the switching regulator, the voltage between the gate and source terminals of the FET exceeds the predetermined value. Can be kept in.

以下本発明の実施の形態を説明する。
図１にＦＥＴを駆動するＦＥＴ駆動装置を示す。
ＦＥＴ２のドレイン端子Ｄに電源１が接続され、ソース端子Ｓに負荷３が接続される。電源１の電圧がスイッチングレギュレータ（以下、ＳＷ−ＲＧと称する）５によって調圧される。該調圧された電圧が、ゲートオンオフ信号に応じてオン、オフ動作を行うスイッチ６と、保護回路８とを介して、ＦＥＴ２のゲート端子Ｇに印加される。
電源１には、差動増幅回路４が接続され、その出力端はＳＷ−ＲＧ５の制御端子ｆに接続される。
さらに、電源１の電圧（点ａ電圧）とＳＷ−ＲＧ５の出力電圧（点ｂ電圧）が所定の第１の閾値以上であるかどうかを検出し、ＳＷ−ＲＧ５の制御端子ｆの電位を制御する検出制御回路７が接続されている。 Embodiments of the present invention will be described below.
FIG. 1 shows an FET driving apparatus for driving an FET.
A power source 1 is connected to the drain terminal D of the FET 2, and a load 3 is connected to the source terminal S. The voltage of the power supply 1 is regulated by a switching regulator (hereinafter referred to as SW-RG) 5. The regulated voltage is applied to the gate terminal G of the FET 2 via the switch 6 that performs an on / off operation according to the gate on / off signal and the protection circuit 8.
A differential amplifier circuit 4 is connected to the power supply 1, and an output terminal thereof is connected to a control terminal f of the SW-RG 5.
Further, it detects whether the voltage of the power source 1 (voltage at point a) and the output voltage of SW-RG5 (voltage at point b) are equal to or higher than a predetermined first threshold value, and controls the potential of the control terminal f of SW-RG5. A detection control circuit 7 is connected.

差動増幅回路４は、内部に備えた差動増幅器１０によって電源１の電圧（点ａ電圧）値とＳＷ−ＲＧ５の出力電圧値との差を検出するものである。
電源１は抵抗１１を介して差動増幅器１０のマイナス側の入力端子に接続される。ＳＷ−ＲＧ５の出力端（点ｂ）は、抵抗１２を介して差動増幅器１０のプラス側の入力端子に接続される。
差動増幅器１０のプラス側入力端子は、抵抗１４を介して接地され、差動増幅器１０のマイナス側の入力端子は、抵抗１３を介して、差動増幅器１０の出力端子ｃに接続される。
さらに、差動増幅器１０の出力端子ｃは、抵抗１５および抵抗１６を介して接地される。抵抗１５と抵抗１６との接続点を点ｄとし、ＳＷ−ＲＧ５の制御端子ｆと点ｄ間が接続される。 The differential amplifier circuit 4 detects a difference between the voltage (point a voltage) value of the power source 1 and the output voltage value of the SW-RG 5 by a differential amplifier 10 provided therein.
The power source 1 is connected to the negative input terminal of the differential amplifier 10 via a resistor 11. The output terminal (point b) of the SW-RG 5 is connected to the positive input terminal of the differential amplifier 10 via the resistor 12.
The positive input terminal of the differential amplifier 10 is grounded via the resistor 14, and the negative input terminal of the differential amplifier 10 is connected to the output terminal c of the differential amplifier 10 via the resistor 13.
Further, the output terminal c of the differential amplifier 10 is grounded via the resistor 15 and the resistor 16. A connection point between the resistor 15 and the resistor 16 is a point d, and the control terminal f of the SW-RG 5 and the point d are connected.

検出制御回路７は、電源１の電圧値とＳＷ−ＲＧ５の出力電圧値との差が、第１の閾値電圧、例えば８．２Ｖを下回ったとき、それを検出してＳＷ−ＲＧ５の制御端子ｆを接地して電位をグラウンド（以下、ＧＮＤと称する）レベルにするものである。
ＳＷ−ＲＧ５の出力端側は、ＰＮＰ型のトランジスタ２７のエミッタ端子と接続され、そのコレクタ端子は抵抗２２を介して接地される。トランジスタ２７のベース端子は、ツェナーダイオード２６のカソード端子側に接続し、さらにツェナーダイオード２６のアノード端子側が抵抗２１を介して、電源１のプラス側と接続する。 The detection control circuit 7 detects when the difference between the voltage value of the power source 1 and the output voltage value of the SW-RG 5 is lower than a first threshold voltage, for example, 8.2 V, and detects it to control the SW-RG 5 f is grounded to bring the potential to the ground (hereinafter referred to as GND) level.
The output end side of the SW-RG 5 is connected to the emitter terminal of the PNP transistor 27, and its collector terminal is grounded via the resistor 22. The base terminal of the transistor 27 is connected to the cathode terminal side of the Zener diode 26, and the anode terminal side of the Zener diode 26 is connected to the positive side of the power supply 1 through the resistor 21.

ここで、トランジスタ２７のエミッタ端子から電源１のプラス側に電圧が加わり、ツェナーダイオード２６に、第１の閾値、例えば８．２Ｖ以上の逆方向バイアスが印加されるとブレークダウンが生じるように設定されている。ツェナーダイオード２６がブレークダウン状態のとき、トランジスタ２７はオン状態となる。
ツェナーダイオード２６に、印加される逆方向バイアスが８．２Ｖ未満の場合は、ブレークダウン状態とはならず、トランジスタ２７はオフ状態となる。
なお、抵抗２２の抵抗値は、ツェナーダイオード２６およびトランジスタ２７がオン状態のときエミッタ側電位が２０Ｖ程度になるような抵抗値を選定する。
このようにツェナーダイオード２６に印加される電圧によって動作状態が変化するツェナーダイオード２６およびトランジスタ２７と、抵抗２１、２２は検出制御回路７の検出回路の部分を構成する。 Here, when a voltage is applied from the emitter terminal of the transistor 27 to the positive side of the power supply 1 and a reverse bias of, for example, 8.2 V or more is applied to the Zener diode 26, a breakdown is generated. Has been. When the Zener diode 26 is in the breakdown state, the transistor 27 is turned on.
When the reverse bias applied to the Zener diode 26 is less than 8.2 V, the breakdown state does not occur and the transistor 27 is turned off.
The resistance value of the resistor 22 is selected such that the emitter-side potential is about 20 V when the Zener diode 26 and the transistor 27 are on.
Thus, the Zener diode 26 and the transistor 27 whose operation state changes depending on the voltage applied to the Zener diode 26, and the resistors 21 and 22 form a detection circuit portion of the detection control circuit 7.

トランジスタ２７のコレクタ端子は抵抗２３を介して、ＮＰＮ型のトランジスタ２８のベース端子に接続する。トランジスタ２８のエミッタ端子は接地しており、コレクタ端子は、抵抗２４を介して電源１のプラス側と接続している。トランジスタ２８のコレクタ端子は、抵抗２５を介してトランジスタ２９のベース端子に接続する。
トランジスタ２９のエミッタ端子は接地されており、コレクタ端子はＳＷ−ＲＧ５の入力端ｆと接続される。 The collector terminal of the transistor 27 is connected to the base terminal of the NPN transistor 28 via the resistor 23. The emitter terminal of the transistor 28 is grounded, and the collector terminal is connected to the positive side of the power source 1 via the resistor 24. The collector terminal of the transistor 28 is connected to the base terminal of the transistor 29 through the resistor 25.
The emitter terminal of the transistor 29 is grounded, and the collector terminal is connected to the input terminal f of the SW-RG 5.

トランジスタ２７がオン状態のとき、コレクタ電流が抵抗２２を経て接地側に流れる。その結果トランジスタ２７のコレクタ端子は正の電位となり、トランジスタ２８のベース端子の電位が正となり、トランジスタ２８がオン状態となる。トランジスタ２８がオン状態となると、トランジスタ２８のコレクタ端子の電圧はＧＮＤレベルとなり、コレクタ端子と抵抗２５を介して接続されているトランジスタ２９のベース端子の電位もＧＮＤレベルの電位となる。その結果トランジスタ２９はオフ状態となり、ＳＷ−ＲＧ５の制御端子ｆは非接地状態となる。 When the transistor 27 is on, the collector current flows through the resistor 22 to the ground side. As a result, the collector terminal of the transistor 27 becomes a positive potential, the potential of the base terminal of the transistor 28 becomes positive, and the transistor 28 is turned on. When the transistor 28 is turned on, the voltage at the collector terminal of the transistor 28 is at the GND level, and the potential at the base terminal of the transistor 29 connected to the collector terminal via the resistor 25 is also at the GND level. As a result, the transistor 29 is turned off, and the control terminal f of the SW-RG 5 is not grounded.

トランジスタ２７がオフ状態のとき、トランジスタ２７のコレクタ端子はＧＮＤレベルとなり、トランジスタ２８のベース端子の電位もＧＮＤレベルとなる。その結果、トランジスタ２８はオフ状態となる。トランジスタ２８がオフ状態となると、トランジスタ２８のコレクタ端子の電圧は電源１により正電位となり、コレクタ端子と抵抗２５を介して接続されているトランジスタ２９のベース端子の電位も正電位となる。その結果トランジスタ２９はオン状態となり、ＳＷ−ＲＧ５の制御端子ｆは接地状態となる。
このようにトランジスタ２７オン／オフ状態に応じて変化するトランジスタ２７のコレクタ端子電位により、トランジスタ２９をオフ／オン状態にして制御端子ｆを非接地／接地状態とするトランジスタ２８、２９および抵抗２３、２４、２５は、検出制御回路７の接地スイッチ回路の部分を構成している。 When the transistor 27 is off, the collector terminal of the transistor 27 is at the GND level, and the potential of the base terminal of the transistor 28 is also at the GND level. As a result, the transistor 28 is turned off. When the transistor 28 is turned off, the voltage at the collector terminal of the transistor 28 becomes a positive potential by the power source 1 and the potential at the base terminal of the transistor 29 connected to the collector terminal via the resistor 25 also becomes a positive potential. As a result, the transistor 29 is turned on, and the control terminal f of the SW-RG 5 is grounded.
In this way, the collector terminal potential of the transistor 27 that changes according to the on / off state of the transistor 27 causes the transistor 29 to be turned off / on and the control terminal f to be ungrounded / grounded. Reference numerals 24 and 25 constitute a ground switch circuit portion of the detection control circuit 7.

保護回路８は、次のように構成されている。
ＦＥＴ２のゲート端子Ｇは、抵抗３０を介してスイッチ６と接続され、またそのゲート端子Ｇは抵抗３１を介して接地される。またゲート端子Ｇは、ツェナーダイオード３２を介してＦＥＴ２のソース端子Ｓ側と接続されている。
ここで、ツェナーダイオード３２のカソード端子側がＦＥＴ２のゲート端子Ｇと、ツェナーダイオード３２のアノード端子側がＦＥＴ２のソース端子Ｓ側と接続し、ＦＥＴ２のゲート端子Ｇからソース端子Ｓ側に電圧が加わり、ツェナーダイオード３２に所定の第２の閾値、例えば１８Ｖ以上の逆方向バイアスが掛かるとブレークダウンが生じるように設定されている。 The protection circuit 8 is configured as follows.
The gate terminal G of the FET 2 is connected to the switch 6 through a resistor 30, and the gate terminal G is grounded through a resistor 31. The gate terminal G is connected to the source terminal S side of the FET 2 through the Zener diode 32.
Here, the cathode terminal side of the Zener diode 32 is connected to the gate terminal G of the FET 2, the anode terminal side of the Zener diode 32 is connected to the source terminal S side of the FET 2, and a voltage is applied from the gate terminal G of the FET 2 to the source terminal S side. The diode 32 is set so that breakdown occurs when a reverse bias of a predetermined second threshold, for example, 18 V or more is applied.

本実施の形態の作用を以下に説明する。
抵抗１１、１２、１３、１４の抵抗値を同一とすると、差動増幅器１０の出力端子ｃの電圧Ｅｏｕｔは次式によって求められる。
Ｅｏｕｔ＝（点ｂ電圧値−点ａ電圧値）×（抵抗１３の抵抗値）／（抵抗１１の抵抗値）・・・・（１） The operation of this embodiment will be described below.
When the resistance values of the resistors 11, 12, 13, and 14 are the same, the voltage Eout of the output terminal c of the differential amplifier 10 is obtained by the following equation.
Eout = (point b voltage value−point a voltage value) × (resistance value of resistor 13) / (resistance value of resistor 11) (1)

ＳＷ−ＲＧ５は、プラス入力側に入力される基準電圧βと、制御端子ｆのマイナス入力側に入力される点ｄ電圧とが等しくなるように、電源１の電圧を調圧して出力する。点ｄ電圧が基準電圧βよりよりも高くなると、出力電圧を下げる方向に制御し、点ｄ電圧が基準電圧βよりも低くなると、出力電圧を上げる方向に制御する。 The SW-RG 5 regulates and outputs the voltage of the power supply 1 so that the reference voltage β input to the positive input side is equal to the point d voltage input to the negative input side of the control terminal f. When the point d voltage becomes higher than the reference voltage β, the output voltage is controlled to decrease, and when the point d voltage becomes lower than the reference voltage β, the output voltage is controlled to increase.

出力端子ｃの電圧Ｅｏｕｔを抵抗１５、１６によって分圧した点ｄ電圧がＳＷ−ＲＧ５の基準電圧βと等しくなるように、抵抗１５、１６を設定すると、ＳＷ−ＲＧ５の出力は、電源１の電圧が変動しても常に電源１の電圧よりもＥｏｕｔだけ高い電圧を出力するように制御される。
したがって、電源１の電圧が変化しても、常にＦＥＴ２のゲート端子Ｇにドレイン端子ＤよりもＥｏｕｔだけ高い電圧を印加でき、所望のゲート−ソース端子間電圧を保ってＦＥＴ２を駆動することができる。 When the resistors 15 and 16 are set so that the point d voltage obtained by dividing the voltage Eout of the output terminal c by the resistors 15 and 16 is equal to the reference voltage β of the SW-RG 5, the output of the SW-RG 5 Control is performed so that a voltage Eout higher than the voltage of the power supply 1 is always output even if the voltage fluctuates.
Therefore, even when the voltage of the power supply 1 changes, a voltage higher than Eout than the drain terminal D can always be applied to the gate terminal G of the FET 2, and the FET 2 can be driven while maintaining a desired gate-source terminal voltage. .

ここで、図１に示すＦＥＴ駆動回路において、電源１の電圧を１０Ｖ、ＳＷ−ＲＧ５の出力電圧を２０Ｖ、ＳＷ−ＲＧ５の基準電圧βを１Ｖ、抵抗１１、１２、１３、１４の抵抗値を、例えば２０ｋΩの同一値とし、抵抗１５の抵抗値を９ｋΩ、抵抗１６の抵抗値を１ｋΩとし、ＦＥＴ２のゲート−ソース端子間電圧を１０Ｖで制御する。 Here, in the FET drive circuit shown in FIG. 1, the voltage of the power source 1 is 10 V, the output voltage of the SW-RG 5 is 20 V, the reference voltage β of the SW-RG 5 is 1 V, and the resistance values of the resistors 11, 12, 13, and 14 are set. For example, the resistance value of the resistor 15 is set to 9 kΩ, the resistance value of the resistor 16 is set to 1 kΩ, and the gate-source terminal voltage of the FET 2 is controlled to 10 V.

この場合、差動増幅器１０の出力端子ｃの電圧Ｅｏｕｔは式（１）により、式（２）のように１０Ｖとなり、点ｄ電圧は式（３）によって得られる。
Ｅｏｕｔ＝（２０Ｖ−１０Ｖ）×２０ｋΩ／２０ｋΩ ・・・・（２）
＝１０Ｖ
点ｄ電圧＝１ｋΩ／（９ｋΩ＋１ｋΩ）×１０Ｖ・・・・（３）
＝１Ｖ In this case, the voltage Eout at the output terminal c of the differential amplifier 10 is 10 V as shown in the equation (2) according to the equation (1), and the voltage at the point d is obtained according to the equation (3).
Eout = (20V-10V) × 20 kΩ / 20 kΩ (2)
= 10V
Point d voltage = 1 kΩ / (9 kΩ + 1 kΩ) × 10 V (3)
= 1V

ここで、電源１の電圧値が１０Ｖから１２Ｖに上昇した場合のＳＷ−ＲＧ５の出力電圧制御を説明する。
差動増幅器１０の出力端子ｃの電圧Ｅｏｕｔは式（１）により、式（４）のように８Ｖとなり、点ｄ電圧は式（５）によって得られる。
Ｅｏｕｔ＝（２０Ｖ−１２Ｖ）×２０ｋΩ／２０ｋΩ ・・・・（４）
＝８Ｖ
点ｄ電圧＝１ｋΩ／（９ｋΩ＋１ｋΩ）×８Ｖ・・・・（５）
＝０．８Ｖ Here, the output voltage control of the SW-RG 5 when the voltage value of the power supply 1 is increased from 10V to 12V will be described.
The voltage Eout at the output terminal c of the differential amplifier 10 is 8V as shown in the equation (4) according to the equation (1), and the voltage at the point d is obtained as the equation (5).
Eout = (20V-12V) × 20 kΩ / 20 kΩ (4)
= 8V
Point d voltage = 1 kΩ / (9 kΩ + 1 kΩ) × 8 V (5)
= 0.8V

ＳＷ−ＲＧ５の基準電圧βは１Ｖであり、制御端子ｆの入力電圧（点ｄ電圧）よりも基準電圧βの方が高いので、ＳＷ−ＲＧ５は入力電圧が基準電圧βと一致するまで、出力電圧（点ｂ電圧）を上昇させる。よって、点ｄ電圧が１Ｖとなるのは、点ｂ電圧が２２Ｖの場合であり、ＳＷ−ＲＧ５はその出力電圧を２２Ｖまで上昇させる。
その結果、ＦＥＴ２のゲート端子Ｇに２２Ｖの電圧が印加され、ＦＥＴ２は以前の場合と同様にゲート−ソース端子間電圧を１０Ｖに維持して駆動される。 Since the reference voltage β of the SW-RG 5 is 1V and the reference voltage β is higher than the input voltage (point d voltage) of the control terminal f, the SW-RG 5 outputs until the input voltage matches the reference voltage β. Increase the voltage (voltage at point b). Therefore, the point d voltage becomes 1V when the point b voltage is 22V, and the SW-RG 5 increases its output voltage to 22V.
As a result, a voltage of 22V is applied to the gate terminal G of the FET2, and the FET2 is driven with the gate-source terminal voltage maintained at 10V as in the previous case.

次に、検出制御回路７の作用を説明する。
差動増幅回路４が、上記のように正常に動作して電源１の出力電圧より１０Ｖ高いゲート−ソース端子間電圧をＳＷ−ＲＧ５の出力電圧として制御している場合、トランジスタ２７のエミッタ端子からベース端子を介して、ツェナーダイオード２６に８．２Ｖ以上の逆バイアスが加わることになり、ツェナーダイオード２６ではブレーク電流が流れる。
その結果、トランジスタ２７はオン状態、つまり検出制御回路７の検出回路はオン状態となり、接地スイッチ回路のトランジスタ２９をオフ状態とする。
ＳＷ−ＲＧ５の制御端子ｆは、トランジスタ２９のコレクタ端子と接続しているが、接地スイッチ回路のトランジスタ２９がオフ状態なので、その電位は抵抗１５、１６の分圧で決まる電位が設定される。 Next, the operation of the detection control circuit 7 will be described.
When the differential amplifier circuit 4 operates normally as described above and controls the gate-source terminal voltage 10V higher than the output voltage of the power supply 1 as the output voltage of the SW-RG 5, the emitter terminal of the transistor 27 A reverse bias of 8.2 V or more is applied to the Zener diode 26 via the base terminal, and a break current flows in the Zener diode 26.
As a result, the transistor 27 is turned on, that is, the detection circuit of the detection control circuit 7 is turned on, and the transistor 29 of the ground switch circuit is turned off.
Although the control terminal f of the SW-RG 5 is connected to the collector terminal of the transistor 29, the potential determined by the divided voltage of the resistors 15 and 16 is set since the transistor 29 of the ground switch circuit is in an OFF state.

これに対し、差動増幅回路４が正常に動作している最中に、その出力電圧（点ｄ電圧）が高くなるような故障、例えば抵抗１６の断線を生じた場合、検出制御回路７は以下の（１）〜（５）の経過を経る。
（１）ＳＷ−ＲＧ５の制御端子ｆには点ｃの電圧がそのまま掛かるので、基準電圧β（１Ｖ）よりも大きい入力電圧であり、ＳＷ−ＲＧ５は出力電圧を低下させるように動作する。
その結果、ＳＷ−ＲＧ５で発生される電圧、即ちゲート電圧を発生させる回路の出力と、電源１のプラス側端子との電位差が、ツェナーダイオード２６で規定される所定の電圧８．２Ｖを下回ることになる。
（２）検出制御回路７の検出回路は、電源電圧とＳＷ−ＲＧ５の出力電圧との電圧差が８．２Ｖ未満であることを検出して、トランジスタ２７のコレクタ端子が検出信号を接地スイッチ回路に出力する。
（３）検出回路からの出力信号により、接地スイッチ回路のトランジスタ２９がオン状態になり、ＳＷ−ＲＧ５の制御端子ｆの電位はＧＮＤレベルとなる。
（４）ＳＷ−ＲＧ５は制御端子ｆの入力電圧（ここでは０Ｖ）が基準電圧β（１Ｖ）より低いので、入力電圧が基準電圧βと一致するように出力電圧（点ｂ電圧）を上昇させる。
（５）出力電圧（点ｂ電圧）が上昇し、電源１のプラス側端子との電位差が８．２Ｖを上回れば、検出制御回路７の検出回路のトランジスタ２７がオン状態になり、接地スイッチ回路のトランジスタ２９がオフ状態となる。その結果ＳＷ−ＲＧ５の制御端子ｆは非接地となり、点ｄの電位が入力される。
以降、上記（１）〜（５）の経過を繰り返す。 On the other hand, in the case where the differential amplifier circuit 4 is operating normally, a failure such as an increase in the output voltage (voltage at point d), for example, disconnection of the resistor 16, causes the detection control circuit 7 to The following (1) to (5) are passed.
(1) Since the voltage at the point c is applied to the control terminal f of the SW-RG 5 as it is, the input voltage is higher than the reference voltage β (1 V), and the SW-RG 5 operates so as to lower the output voltage.
As a result, the potential difference between the voltage generated by the SW-RG 5, that is, the output of the circuit that generates the gate voltage, and the positive terminal of the power supply 1 is less than the predetermined voltage 8.2 V defined by the Zener diode 26. become.
(2) The detection circuit of the detection control circuit 7 detects that the voltage difference between the power supply voltage and the output voltage of the SW-RG 5 is less than 8.2 V, and the collector terminal of the transistor 27 outputs the detection signal to the ground switch circuit. Output to.
(3) The output signal from the detection circuit turns on the transistor 29 of the ground switch circuit, and the potential of the control terminal f of the SW-RG 5 becomes the GND level.
(4) Since the input voltage (0 V here) of the control terminal f is lower than the reference voltage β (1 V), the SW-RG 5 increases the output voltage (point b voltage) so that the input voltage matches the reference voltage β. .
(5) When the output voltage (voltage at point b) rises and the potential difference from the positive terminal of the power supply 1 exceeds 8.2 V, the transistor 27 of the detection circuit of the detection control circuit 7 is turned on, and the ground switch circuit The transistor 29 is turned off. As a result, the control terminal f of the SW-RG 5 is not grounded, and the potential at the point d is input.
Thereafter, the above steps (1) to (5) are repeated.

次に、保護回路８の作用を説明する。
差動増幅回路４が正常に動作している最中に、その出力電圧（点ｄ電圧）が低くなるような故障、例えば抵抗１５側の断線を生じた場合、ＳＷ−ＲＧ５はその出力を上昇させるように動作する。その結果、出力電圧（点ｂ電圧）がＦＥＴ２のゲート耐圧を越えてしまう可能性があるが、スイッチ６がゲートオンオフ信号によってオン状態となったとき、抵抗３０を介して、ゲート端子ＧにＳＷ−ＲＧ５の出力電圧が印加される。ＦＥＴ２のソース側には電源１の電圧が加わる。
ツェナーダイオード３２に逆バイアスが加わり、ツェナーダイオード３２の設定電圧１８Ｖ以上の電圧が、ゲート端子Ｇとソース端子Ｓ間に加わったとき、ツェナーダイオード３２にブレークが発生し、ゲート−ソース端子電圧を１８Ｖに規制する。 Next, the operation of the protection circuit 8 will be described.
When the differential amplifier circuit 4 is operating normally, if a failure occurs such that the output voltage (voltage at point d) becomes low, for example, a disconnection occurs on the resistor 15 side, the SW-RG 5 increases its output. Works to let you. As a result, the output voltage (voltage at the point b) may exceed the gate breakdown voltage of the FET 2, but when the switch 6 is turned on by the gate on / off signal, the SW 30 is connected to the gate terminal G via the resistor 30. -The output voltage of RG5 is applied. The voltage of the power source 1 is applied to the source side of the FET 2.
When a reverse bias is applied to the Zener diode 32 and a voltage higher than the set voltage 18V of the Zener diode 32 is applied between the gate terminal G and the source terminal S, a break occurs in the Zener diode 32, and the gate-source terminal voltage is set to 18V. To regulate.

なお、差動増幅回路４の出力電圧（点ｄ電圧）が高くなるような故障、例えば抵抗１６の断線を生じた場合に、検出制御回路７によりＳＷ−ＲＧ５の制御端子ｆの電位がＧＮＤレベルとなったとき、ＳＷ−ＲＧ５の出力電圧増加の動作時に、スイッチ６がオンになると、ＦＥＴ２にゲート耐圧より高い電圧が加わる可能性があるが、上記ツェナーダイオード３２の動作により、１８Ｖ以上の電圧が、ゲート端子Ｇとソース端子Ｓ間に加わることはない。
本実施の形態の検出制御回路７は本発明のスイッチングレギュレータ制御手段を構成する。特にトランジスタ２７は本発明の第1のトランジスタに、トランジスタ２９は第2のトランジスタに対応する。 Note that when the output voltage (voltage at point d) of the differential amplifier circuit 4 becomes high, for example, when the resistor 16 is disconnected, the potential of the control terminal f of the SW-RG 5 is set to the GND level by the detection control circuit 7. When the switch 6 is turned on during the operation of increasing the output voltage of the SW-RG 5, there is a possibility that a voltage higher than the gate breakdown voltage is applied to the FET 2. However, it is not added between the gate terminal G and the source terminal S.
The detection control circuit 7 of the present embodiment constitutes the switching regulator control means of the present invention. In particular, the transistor 27 corresponds to the first transistor of the present invention, and the transistor 29 corresponds to the second transistor.

以上のように本実施の形態によれば、電源電圧とＳＷ−ＲＧ５の出力電圧との間に検出制御回路７を設け、該電圧差が所定の第１の閾値以上の場合は、ＳＷ−ＲＧ５の制御端子ｆを接地せず、該電圧差が所定の第１の閾値未満の場合は、ＳＷ−ＲＧ５の制御端子ｆを接地する。
その結果何らかの理由で、制御端子ｆの入力が高くなり、ＳＷ−ＲＧ５が出力電圧と電源電圧との電圧差が第1の閾値未満になるまで降下させた場合、検出制御回路７が強制的にＳＷ−ＲＧ５の制御端子ｆの電位をＧＮＤレベルにまで下げて、出力電圧を電源電圧より第1の閾値分昇圧する。その結果、ＦＥＴ２をオン状態に制御できないとか、オン状態にできてもオン抵抗が増加して、正常状態以上に発熱することが防止できる。 As described above, according to the present embodiment, the detection control circuit 7 is provided between the power supply voltage and the output voltage of the SW-RG 5, and when the voltage difference is equal to or greater than the predetermined first threshold, the SW-RG 5 When the control terminal f is not grounded and the voltage difference is less than the predetermined first threshold value, the control terminal f of the SW-RG 5 is grounded.
As a result, when the input of the control terminal f becomes high for some reason and the SW-RG 5 is lowered until the voltage difference between the output voltage and the power supply voltage becomes less than the first threshold, the detection control circuit 7 is forced to The potential of the control terminal f of the SW-RG 5 is lowered to the GND level, and the output voltage is boosted from the power supply voltage by the first threshold value. As a result, it is possible to prevent the FET 2 from being controlled to the on state, or even if the FET 2 can be turned on, the on-resistance increases and heat generation beyond the normal state can be prevented.

また、差動増幅回路４によって電源１の電圧値とＳＷ−ＲＧ５の出力電圧値との電圧差を検出し、該電圧差を抵抗１５，１６によって分圧してＳＷ−ＲＧ５の制御端子ｆに入力する。ＳＷ−ＲＧ５は、差動増幅回路４から入力された電圧値と基準電圧βとを比較して電源１の電圧を制御してＦＥＴ２のゲート端子Ｇに印加する。
差動増幅回路４の出力電圧（点ｄ電圧）が正常な場合は、ＳＷ−ＲＧ５の出力電圧は、電源１の電圧の変動に応じて、自動的に電源電圧よりも１０Ｖ高い電圧となるように、差動増幅回路とＳＷ−ＲＧ５の動作によって制御される。 Further, the voltage difference between the voltage value of the power source 1 and the output voltage value of the SW-RG 5 is detected by the differential amplifier circuit 4, and the voltage difference is divided by the resistors 15 and 16 and input to the control terminal f of the SW-RG 5. To do. The SW-RG 5 compares the voltage value input from the differential amplifier circuit 4 with the reference voltage β, controls the voltage of the power supply 1 and applies it to the gate terminal G of the FET 2.
When the output voltage (voltage at point d) of the differential amplifier circuit 4 is normal, the output voltage of the SW-RG 5 is automatically 10V higher than the power supply voltage in accordance with the fluctuation of the voltage of the power supply 1. Further, the operation is controlled by the differential amplifier circuit and the operation of the SW-RG 5.

さらに、差動増幅回路４に異常が生じて、出力電圧（点ｄ電圧）が高くなり、ＳＷ−ＲＧ５の出力電圧が電源電圧より１０Ｖ高い値に制御できない場合でも、検出制御回路７の動作により、少なくとも電源電圧よりツェナーダイオード２６で規定される、例えば８．２Ｖ高い電圧に制御されるので、ＦＥＴ２をオン状態に制御可能とする。
その結果、ＦＥＴ２をオン状態に制御できないとか、オン状態にできてもオン抵抗が増加して、正常状態以上に発熱することが防止できる。 Furthermore, even when an abnormality occurs in the differential amplifier circuit 4 and the output voltage (voltage at point d) becomes high, and the output voltage of the SW-RG 5 cannot be controlled to a value 10 V higher than the power supply voltage, the operation of the detection control circuit 7 Since the voltage is controlled to at least 8.2 V, for example, which is defined by the Zener diode 26 from the power supply voltage, the FET 2 can be controlled to be in the ON state.
As a result, it is possible to prevent the FET 2 from being controlled to the on state, or even if the FET 2 can be turned on, the on-resistance increases and heat generation beyond the normal state can be prevented.

さらに、ＦＥＴ２のゲート端子Ｇには保護回路８を設け、ゲート−ソース端子間に所定の第２の閾値以上の電圧が加わった場合、ツェナーダイオード３２にブレークが生じてそれ以上の電圧としないので、差動増幅回路４に異常が生じて、出力電圧（点ｄ電圧）が低くなり、ＳＷ−ＲＧ５の出力電圧が電源電圧より１０Ｖを大きく越えて高い値に制御されてしまう場合でも、保護回路８の動作によりゲート−ソース端子間電圧が抑制され、ＦＥＴを破損させることがない。 Further, the protection circuit 8 is provided at the gate terminal G of the FET 2, and when a voltage higher than a predetermined second threshold is applied between the gate and source terminals, a break occurs in the Zener diode 32 and the voltage is not increased. Even if an abnormality occurs in the differential amplifier circuit 4 and the output voltage (voltage at point d) becomes low, and the output voltage of the SW-RG 5 is controlled to a value higher than 10 V more than the power supply voltage, the protection circuit By the operation of 8, the gate-source terminal voltage is suppressed and the FET is not damaged.

本実施の形態におけるＦＥＴ駆動回路を示す図である。It is a figure which shows the FET drive circuit in this Embodiment.

Explanation of symbols

１電源
２ＦＥＴ
３負荷
４差動増幅回路
５スイッチングレギュレータ
６スイッチ
７検出制御回路
８保護回路
１０差動増幅器
１１、１２、１３、１４、１５、１６抵抗
２１、２２、２３、２４、２５、３０、３１抵抗
２６、３２ツェナーダイオード
２７、２８、２９トランジスタ 1 Power supply 2 FET
DESCRIPTION OF SYMBOLS 3 Load 4 Differential amplifier circuit 5 Switching regulator 6 Switch 7 Detection control circuit 8 Protection circuit 10 Differential amplifier 11, 12, 13, 14, 15, 16 Resistance 21, 22, 23, 24, 25, 30, 31 Resistance 26 , 32 Zener diode 27, 28, 29 Transistors

Claims

In an FET drive device for driving an N-channel FET connected between a power source and a load and upstream of the load,
A switching regulator having the same reference potential as the reference potential of the power supply and generating an FET drive voltage for boosting the power supply voltage of the power supply to drive the FET ;
A switch for switching whether to supply the FET drive voltage to the gate of the FET according to a gate on / off signal;
A switching regulator that controls the switching regulator to increase the output voltage of the switching regulator when it is detected that the voltage difference between the power supply voltage and the output voltage of the switching regulator has fallen below a predetermined first threshold. FET driving apparatus characterized by comprising: a control means.

When the voltage difference between the power supply voltage and the output voltage of the switching regulator is equal to or greater than a predetermined first threshold, the switching regulator control means sets the potential of the control terminal of the switching regulator to a value corresponding to the power supply voltage. 2. The FET drive device according to claim 1, wherein when it is detected that the voltage difference falls below the first threshold, the potential of the control terminal of the switching regulator is lowered to a reference potential .

A differential amplifier circuit that detects a voltage difference between the power supply voltage and the output voltage of the switching regulator, the detected voltage difference as an input to the control terminal of the switching regulator,
The switching regulator adjusts a power supply voltage based on a detection result from the differential amplifier circuit to generate an FET drive voltage when the detected voltage difference is equal to or greater than the first threshold value. 3. The FET drive device according to 1 or 2.

The differential amplifier circuit includes a differential amplifier and a resistor, detects a voltage difference between the power supply voltage and the output voltage of the switching regulator by the differential amplifier, and steps down the detected voltage difference by the resistor. To the control terminal of the switching regulator,
The switching regulator controls the FET drive voltage in a decreasing direction when the voltage difference is greater than or equal to the first threshold and increases, and the voltage difference is greater than or equal to the first threshold and decreases. 4. The FET driving device according to claim 3, wherein the FET driving voltage is controlled in an increasing direction.

The switching regulator control means includes
A detection circuit that detects whether a voltage difference between the power supply voltage and the output voltage of the switching regulator is less than the first threshold and outputs a detection signal;
5. The FET drive according to claim 2, further comprising: a ground switch circuit that is on / off controlled according to a detection signal of the detection circuit and grounds a control terminal of the switching regulator. 6. apparatus.

The detection circuit includes:
Emitter terminal connected to the output side of the switching regulator, a first transistor collector terminal is grounded via a resistor,
A Zener diode having a cathode terminal connected to the base terminal of the first transistor and an anode terminal connected to the power source;
When the voltage difference between the power supply voltage and the output voltage of the switching regulator applies a reverse bias voltage equal to or higher than the predetermined first threshold to the Zener diode, the first transistor is turned on,
When the voltage difference applies a reverse bias voltage less than the predetermined first threshold to the Zener diode, the first transistor is turned off;
The detection signal is output from the collector terminal of the first transistor according to the on / off state of the first transistor,
The ground switch circuit is
A second terminal having a collector terminal connected to the control terminal of the switching regulator and an emitter terminal grounded;
When the detection signal from the detection circuit indicates that the voltage difference between the power supply voltage and the output voltage of the switching regulator is less than the first threshold, the second transistor is turned on,
The second transistor is configured to be turned off when the detection signal from the detection circuit indicates that the voltage difference between the power supply voltage and the output voltage of the switching regulator is equal to or greater than the first threshold. The FET drive device according to claim 5, wherein:

And a protection circuit that suppresses a voltage applied to the gate of the FET to be equal to or lower than the FET withstand voltage when a voltage difference between the power supply voltage and the output voltage of the switching regulator exceeds a predetermined second threshold. The FET drive device according to any one of claims 1 to 6.

The protection circuit has a Zener diode,
8. The FET drive device according to claim 7, wherein a cathode side of the Zener diode is connected to a gate terminal side of the FET, and an anode side of the Zener diode is connected to a source terminal side of the FET.

A method for controlling an FET drive voltage of an FET drive device for driving an N-channel FET connected between a power source and a load and connected to the upstream side of the load,
The FET driver is
A switching regulator having the same reference potential as the reference potential of the power supply and generating an FET drive voltage for driving the FET by boosting the power supply voltage of the power supply, and driving the FET to the gate of the FET according to a gate on / off signal comprising a switch for switching whether to supply a voltage, and a differential amplifier circuit for detecting a voltage difference between the output voltage of the power supply voltage and the switching regulator,
The switching regulator, wherein the generating the FET drive voltage based on the detection result of said differential amplifier circuit,
When it is detected that the voltage difference between the power supply voltage and the output voltage of the switching regulator has fallen below a predetermined first threshold, the switching regulator control terminal is configured to increase the output voltage of the switching regulator. A method for controlling an FET drive voltage, wherein the potential is lowered to a reference potential .

According the voltage difference between the pre-Symbol power supply voltage and the output voltage of the switching regulator, when it exceeds a predetermined second threshold value, characterized in that to suppress the voltage applied to the gate of the FET below FET breakdown voltage Item 12. The method for controlling the FET drive voltage according to Item 9 .