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JP4470465B2 - Electrode for connecting via holes with through holes - Google Patents

Electrode for connecting via holes with through holes Download PDF

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JP4470465B2
JP4470465B2 JP2003398605A JP2003398605A JP4470465B2 JP 4470465 B2 JP4470465 B2 JP 4470465B2 JP 2003398605 A JP2003398605 A JP 2003398605A JP 2003398605 A JP2003398605 A JP 2003398605A JP 4470465 B2 JP4470465 B2 JP 4470465B2
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substrate
electrode
hole
plating
transfer
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JP2005159202A (en
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博光 高下
大三 馬場
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Panasonic Corp
Panasonic Electric Works Co Ltd
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Panasonic Corp
Matsushita Electric Works Ltd
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Description

本発明は、配線基板の層間接続用電極に関し、特に基板内の電極が貫通孔を有するビアホール接続用の電極に関する。   The present invention relates to an interlayer connection electrode of a wiring board, and more particularly to an electrode for via hole connection in which an electrode in the board has a through hole.

近年の電子機器の小型、軽量、高機能化の急速な進展の下、配線基板も全層インナービア(via、「バイア」とも言われている)ホール構造の、樹脂を基材とする多層基板が実用化されている。以下、この基板の製造方法について概略説明する。
(1)アラミド基材エポキシ樹脂等のプリプレグよりなる樹脂製絶縁性基板の両面に、離型剤層が絶縁層側にのみ形成された離型性力バーフィルムをラミネートし、所定位置にレーザーにて貫通孔を開ける。
(2)貫通孔内に、樹脂中に金属フィラを混入した導電性ペーストをスキージ法等で充填する。その後両面の離型性カバーフィルムをプリプレグ表面から剥がす。
(3)プリプレグの両面に銅箔を配置し、離型性カバーフィルムの厚さの分だけプリプレグの表面から突出した導電性ペーストをプリプレグの貫通孔内へ押し込んだ状態で加圧し、更に加熱してプリプレグ、導電ペーストを硬化させ、併せて銅箔をプリプレグ表面に固着させ銅箔張り積層板とする。
(4)銅箔にフォットリソグラフィー等を使用して所定のエッチングをし、積層板表面に配線パターンを形成する。
(5)更に(4)の処理の済んだ基板の両面、若しくは片面に上記(2)の処理後のプリプレグと銅箔をこの順に配置し、再度(3)の処理をし、その後上記(4)の処理をする。
(6)必要に応じて、以上の処理を繰り返す。
ただし、これらは以下の特許文献1で開示されている技術である。このため、これ以上の説明は省略する。
In recent years, with the rapid development of small, light, and highly functional electronic devices, the wiring board is also a multilayer board based on resin with an all-layer inner via (also referred to as “via”) hole structure. Has been put to practical use. Hereafter, the manufacturing method of this board | substrate is demonstrated roughly.
(1) A release force bar film having a release agent layer formed only on the insulating layer side is laminated on both sides of a resin insulating substrate made of a prepreg such as an aramid base epoxy resin, and a laser is applied to a predetermined position. Open a through hole.
(2) A conductive paste in which a metal filler is mixed in a resin is filled in the through hole by a squeegee method or the like. Thereafter, the releasable cover films on both sides are peeled off from the prepreg surface.
(3) Copper foils are arranged on both sides of the prepreg, and the conductive paste protruding from the surface of the prepreg by the thickness of the releasable cover film is pressed into the through-hole of the prepreg and further heated. Then, the prepreg and the conductive paste are cured, and the copper foil is fixed to the prepreg surface to obtain a copper foil-clad laminate.
(4) The copper foil is subjected to predetermined etching using photolithography or the like to form a wiring pattern on the surface of the laminate.
(5) Further, the prepreg and copper foil after the processing of (2) above are arranged in this order on both sides or one side of the substrate after the processing of (4), the processing of (3) is performed again, and then the above (4) ).
(6) The above processing is repeated as necessary.
However, these are techniques disclosed in Patent Document 1 below. For this reason, further explanation is omitted.

特開2002−118338号公報 以上の他多層基板には、コストの削減等の他に各部の、特にビアホール部の電気的接続性を改良する目的で、以下の特許文献2から特許文献8に示すように様々な発明がなされている。JP, 2002-118338, A The above other multilayer boards are shown in the following patent documents 2-patent documents 8 for the purpose of improving the electrical connection nature of each part, especially a via hole part besides cost reduction etc. Various inventions have been made. 特表平10−507315号公報Japanese National Patent Publication No. 10-507315 特開2000−315867号公報JP 2000-315867 A 特開2001−203459号公報JP 2001-203459 A 特開2003−188533号公報JP 2003-188533 A 特開2003−258013号公報Japanese Patent Laid-Open No. 2003-258013 特開2003−298240号公報JP 2003-298240 A 特開2003−318546号公報JP 2003-318546 A

ところで、多層基板はその製造に際して何度も加圧下で加熱される。一方、導電ペーストは、多くの場合金属体(微粒子、ファイバー状等)の混入した樹脂である。このため、上述の背景技術欄の(4)の状態後の後工程での加熱やあるいは製造後の使用時の発熱、放冷の繰り返しにより収縮を起し、その結果ビア抵抗が増加することがある。この収縮の様子を図1に示す。
図1の(1)は製造直後のビアホール断面を示し、(2)は加速テストのため製造後加熱下で数百時間経過して導電ペーストが収縮した状態のビアホールの断面を示す。なお、図の10は樹脂製絶縁性基板(回路基板の基材)である。27はビアホール内に柱状に充填された直後の導電性ペーストであり、28は後工程での加熱等のため収縮した導電性ペーストである。90は、導電性ペーストの収縮で生じたスペースである。48は電極(接続用の電極である回路のランド若しくはパッド)である。このため、1つのビア抵抗は初期が38mΩであったのが、125℃、950時間経過後には1140mΩになったりもする。
By the way, the multilayer substrate is heated under pressure many times during its manufacture. On the other hand, in many cases, the conductive paste is a resin mixed with a metal body (fine particles, fibers, etc.). For this reason, shrinkage is caused by repeated heating in the post-process after the state of (4) in the background art section described above, or heat generation and cooling after use, and as a result, via resistance may increase. is there. The state of this contraction is shown in FIG.
(1) in FIG. 1 shows a cross section of the via hole immediately after manufacture, and (2) shows a cross section of the via hole in which the conductive paste is contracted after several hundred hours under heating after manufacture for an acceleration test. In addition, 10 of a figure is a resin-made insulating board | substrate (base material of a circuit board). 27 is a conductive paste immediately after filling a via hole in a columnar shape, and 28 is a conductive paste shrunk due to heating or the like in a later process. Reference numeral 90 denotes a space generated by contraction of the conductive paste. Reference numeral 48 denotes an electrode (a circuit land or pad which is a connection electrode). For this reason, one via resistance is initially 38 mΩ, but may be 1140 mΩ after 950 hours at 125 ° C.

以上から加熱下、高温下でもかかるビア抵抗の増加がないビアホールの接続構造の開発が望まれていた。   From the above, it has been desired to develop a via hole connection structure that does not increase the via resistance under heating and high temperatures.

本発明は、以上の課題を解決することを目的としてなされたものであり、ビアホールの両端に在る基板内の電極に貫通孔を設け、この貫通孔内に導電ペーストを侵入させ、これによりその収縮の防止、たとえ収縮したとしても貫通孔の外表面が凹むだけであり電極との接触面積は減少せずこのためビア抵抗の増加とならないようにしている。更に、貫通孔の内径途中を最大若しくは最小としてひっかかりがあるようにすることにより、その収縮を機械的、物理的により一層拘束するようにしている。 The present invention has been made for the purpose of solving the above-mentioned problems. A through hole is provided in an electrode in a substrate at both ends of a via hole, and a conductive paste is intruded into the through hole. Prevention of contraction, even if contracted, the outer surface of the through-hole is only recessed, and the contact area with the electrode is not reduced, so that the via resistance is not increased. Furthermore, the contraction is further constrained more mechanically and physically by setting the middle of the inner diameter of the through hole as a maximum or minimum so as to be caught.

また、電極の導電ペーストに向く面、貫通孔内を粗化して導電ペーストとの接触面積の増加と接着力の向上を図り、併せて導電ペーストの収縮によるスペースの発生の防止を図っている
またその製造に際しては、転写箔プロセスを用いている。このため、転写用基板上にランド、パッド部はもちろんその他の回路パターン同時に形成し、樹脂製基板に転写によりビアホールの接続構造のみならず電極となるランド、パッド等を含む回路パターンを同時に、同一工程で製造しうるようにしている。更に、転写用基板に電極を形成するからこそ、その導電ペースト側の表面を粗化することも容易になしうることをも考慮している。

In addition, the surface of the electrode facing the conductive paste and the inside of the through hole are roughened to increase the contact area with the conductive paste and improve the adhesion, and to prevent the generation of space due to the shrinkage of the conductive paste. In the production, a transfer foil process is used. For this reason, land and pad portions as well as other circuit patterns are simultaneously formed on the transfer substrate, and the same circuit pattern including lands, pads, etc. that become electrodes as well as via-hole connection structures is transferred simultaneously to the resin substrate. It can be manufactured in the process. Further, it is considered that the surface on the conductive paste side can be easily roughened because the electrode is formed on the transfer substrate.

以上の手段を採ることにより、特に基板内の電極の貫通孔内に導電性ペーストを入り込ませ、孔の形成で収縮の方向を分散させることができるとともに収縮を拘束することにより、導電性ペーストの後工程での加熱や時間の経過による収縮はなくなるか、あったとしても非常に少なくなり、その結果電極とビアホールの接続抵抗は、後工程での加熱や使用時の発熱、放冷の繰り返しによる増加が従来品に比べて非常に少なくなる。これにより、電子機器の信頼性も向上する。   By adopting the above means, in particular, the conductive paste can be put into the through-holes of the electrodes in the substrate, the direction of shrinkage can be dispersed by forming the holes, and the shrinkage can be restrained. Heating in the subsequent process and shrinkage due to the passage of time are eliminated or very little, if any. As a result, the connection resistance between the electrode and the via hole is due to repeated heating, heating during use, and cooling. The increase is very small compared to conventional products. This also improves the reliability of the electronic device.

以下、本発明をその好ましい実施の形態に基づいて説明する。
(第1の実施の形態)
本実施の形態は、図2の(B)に示すように電極41の貫通孔の中央部の内径が最も太くしている。このため、たとえ導電性ペースト26が収縮しようとしても、収縮力が分散することに加えて電極の孔の内周面の形状により機械的、あるいは物理的に拘束されるため、収縮によるスペースは内部には形成されず、図2(B)に示すごとく孔内の内部の外周面に凹所91が生じるだけである。このため、導電性ペーストと電極との接触面積はほとんど変わらず、ビア抵抗の増加はあったとしても僅少に抑制できる。なお念のため記載するが、本図に示すのは導電ペーストが収縮した状態であり、製造時には孔内の凹所は存在しないのはもちろんである。
Hereinafter, the present invention will be described based on preferred embodiments thereof.
(First embodiment)
In the present embodiment, as shown in FIG. 2B, the inner diameter of the central portion of the through hole of the electrode 41 is the largest. For this reason, even if the conductive paste 26 is contracted, the contraction force is dispersed and, in addition, the shape of the inner peripheral surface of the electrode hole is mechanically or physically constrained. However, as shown in FIG. 2 (B), only the recess 91 is formed on the inner peripheral surface in the hole. For this reason, the contact area between the conductive paste and the electrode hardly changes, and even if there is an increase in via resistance, it can be suppressed slightly. It should be noted that, as a precaution, the drawing shows a state where the conductive paste is contracted, and of course there is no recess in the hole at the time of manufacture.

次に、この回路基板そのものの製造方法について説明する。
図3の(1)はビアホール内に導電ペースト25が充填された状態の樹脂製の絶縁性基板となるプリプレグ10及び、中央に貫通孔42のある転写用の電極40と回路パターン49がその表面に形成された転写用金属箔51を前記プリプレグ10に形成されているビアホールに丁度電極40が嵌まり込むように位置合せして、両面から付着しようとしている状態を示す。
図3の(2)は、この転写用金属箔51をプリプレグ10に正しく配置した状態で押圧し、更に加熱している状態を示す。
図3の(3)は、転写された回路が、樹脂製の絶縁基板10に形成されたビアホールを介して基板の厚み方向の電気的接続がなされた状態である。なお、転写用金属箔は既に除去されている。この後、場合によっては上下に更に他の絶縁性基板や銅箔が加圧下での加熱等で付着され、銅箔へのエッチング等で回路パターンが形成され、これを繰り返して多層の回路パターンが形成されることととなる。
Next, a method for manufacturing the circuit board itself will be described.
FIG. 3 (1) shows a prepreg 10 that is a resin insulating substrate in which a conductive paste 25 is filled in a via hole, and a transfer electrode 40 and a circuit pattern 49 having a through hole 42 in the center. A state in which the metal foil for transfer 51 formed in (1) is positioned so that the electrode 40 fits into the via hole formed in the prepreg 10 and is going to be attached from both sides.
(2) of FIG. 3 shows a state in which the metal foil for transfer 51 is pressed and further heated in a state where it is correctly disposed on the prepreg 10.
FIG. 3 (3) shows a state in which the transferred circuit is electrically connected in the thickness direction of the substrate through a via hole formed in the resin-made insulating substrate 10. The transfer metal foil has already been removed. Thereafter, in some cases, another insulating substrate or copper foil is attached to the top and bottom by heating under pressure, etc., and a circuit pattern is formed by etching or the like on the copper foil, and this is repeated to form a multilayer circuit pattern. It will be formed.

なおまた、図3の(1−a)は、中央の貫通孔42の形成された電極40を反転写用基板側より見た図であり、電極40のランド若しくはパッドに回路が接続されている。参考のため示すものである。
次に、順序は逆になったかもしないが、図2の()に示す形状の、すなわち中心に貫通孔のある電極が表面に形成された転写用基板の製造方法について、図4を参照しつつ順に説明する。
(1)先ず、ステンレス製転写用基板50上に感光性のドライフィルム膜60(デュポン社製、品番「FX−140」)を形成し、更にその上方にフォトマスク70を取り付ける。
(2)次いで、フォトマスク70上方より光を当てて露光し、現像する。この際、(2−a)に示すように、焦点を多少ぼかす等の露光条件やドライフィルムの厚みを調整したり、その他光の回折を利用して、残るドライフィルムの中心部上下方向の切断面が台形、すなわち図上で下広がりとなるように露光させる。
(3)次に、フォトマスク70を取り去り、次いで非露光部を除去する。
(4)転写用基板50ごと銅メッキを行い、取り去られた非露光部に銅の層を形成する。なお、めっきの条件であるが、本実施例では45秒程度電気めっきを行い、35μm厚さに銅の膜を付着させた。
(5)最後に、露光したドライフィルムをエッチング等で除去する。
なお、この際、転写用基板上に同時に回路パターンを形成しておくのが工程の削減、コストダウンの面から好ましい。
このように形成した貫通孔を有する電極(孔の狭い径が100μm、広い径が110μm)を使用した場合、ビア径が300μmで基板厚みが800μmの1つのビア抵抗は、初期が14mΩであり、125℃、950時間後には54mΩであった。
Further, (1-a) in FIG. 3 is a view of the electrode 40 in which the central through hole 42 is formed as seen from the side of the substrate for transfer, and a circuit is connected to the land or pad of the electrode 40. . It is shown for reference.
Then, although the order is not be is reversed, the shape shown in FIG. 2 (B), i.e. a method for manufacturing the transfer substrate on which electrodes are formed on the surface of the through hole in the center, see Figure 4 However, it demonstrates in order.
(1) First, a photosensitive dry film film 60 (manufactured by DuPont, product number “FX-140”) is formed on a stainless steel transfer substrate 50, and a photomask 70 is attached thereon.
(2) Next, the photomask 70 is exposed to light from above to be developed. At this time, as shown in (2-a), the exposure condition such as the focus is slightly blurred and the thickness of the dry film is adjusted, or other diffraction of light is used to cut the center of the remaining dry film in the vertical direction. The exposure is performed so that the surface is trapezoidal, that is, spreads downward in the figure.
(3) Next, the photomask 70 is removed, and then the non-exposed portion is removed.
(4) The transfer substrate 50 is subjected to copper plating, and a copper layer is formed on the removed non-exposed portion. In this example, electroplating was performed for about 45 seconds to deposit a copper film to a thickness of 35 μm.
(5) Finally, the exposed dry film is removed by etching or the like.
In this case, it is preferable to form a circuit pattern on the transfer substrate at the same time from the viewpoints of reduction of process and cost.
When an electrode having a through hole formed in this way (narrow hole diameter is 100 μm, wide diameter is 110 μm), one via resistance having a via diameter of 300 μm and a substrate thickness of 800 μm is initially 14 mΩ, It was 54 mΩ after 950 hours at 125 ° C.

(第2の実施の形態)
その他の形状の電極の製造方法等について、図5を参照しつつ説明する。
図5の(A)は、ウェットエッチングを使用するものである。このため、85はエッチングレジストであり、80はエッチング用樹脂層である。ウェットエッチングでは、エッチング液はエッチングレジスト85の開孔86より内部へ入り込んでエッチング樹脂層80を侵食するため、下広がりの侵食となる。
(Second Embodiment)
The manufacturing method of electrodes having other shapes will be described with reference to FIG.
FIG. 5A uses wet etching. For this reason, 85 is an etching resist and 80 is an etching resin layer. In the wet etching, the etching solution enters the inside through the opening 86 of the etching resist 85 and erodes the etching resin layer 80, so that the etching spreads downward.

なお、本図に示す形状の現像済等の硬化した樹脂柱が一旦形成された後は、転写用基板ごと銅めっきされ、樹脂が除去されるのは図4の場合と同じである。   In addition, after a cured resin column having a developed shape having the shape shown in this figure is once formed, the transfer substrate is plated with copper and the resin is removed in the same manner as in FIG.

図5の(B)は、電極に中央部の内径が太い貫通孔を形成するものである。この場合には、
(1)ステンレス製転写用基板50上にエポキシ樹脂層90と銅箔95を形成し、YAGレーザーを用いて中太の孔91を穿ける。
(2)銅箔を取り去り、更にエッチング樹脂層の孔を電気めっきにより銅96で埋める。
(3)エポキシ樹脂層をエッチングで除去し、転写用電極40を製造する。
また、どの様な製造方法においても、必要に応じての7%塩酸水や純水での洗浄、脱脂等が行われるが、これらは周知技術なのでその説明は省略する。
(B) of FIG. 5 forms a through-hole with a thick inner diameter at the center in the electrode. In this case,
(1) An epoxy resin layer 90 and a copper foil 95 are formed on a stainless steel transfer substrate 50, and a medium-sized hole 91 is formed using a YAG laser.
(2) The copper foil is removed, and the holes of the etching resin layer are filled with copper 96 by electroplating.
(3) The epoxy resin layer is removed by etching, and the transfer electrode 40 is manufactured.
In any production method, cleaning with 7% hydrochloric acid or pure water, degreasing, etc. are performed as necessary. However, since these are well-known techniques, description thereof is omitted.

このようにして形成した貫通孔を有する電極(孔の広い径100μm、狭い径92μm)を使用した場合、ビア径が300μmで基板厚みが800μmの1つのビアの抵抗は、初期が14mΩの抵抗が、125℃、950時間後には51mΩとなった。   When an electrode having a through hole formed in this way (wide hole diameter of 100 μm, narrow diameter of 92 μm) is used, the resistance of one via having a via diameter of 300 μm and a substrate thickness of 800 μm is initially 14 mΩ. The temperature became 51 mΩ after 950 hours at 125 ° C.

(第3の実施の形態)
本実施の形態は、基板内の電極の貫通孔内面を含む導電性ペーストとの接触面側の表面に粗化処理を行うものである。このため、転写基板に電極が形成された状態、すなわち図4の(5)に示す状態(孔が3つ開孔され、その狭い孔径が75μm、広い孔径が80μm)で次の処理がなされる。その処理手段であるが、本実施の形態では導電性ペーストとの良好な電気抵抗の確保のため、表面に酸化銅の形成される黒色酸化処理ではなく、金などのめっき、エッチング及びブラスト処理等の機械的処理を行う。ただし、これらの処理そのものは周知技術であるため、その説明は省略する。
(Third embodiment)
In the present embodiment, the surface of the contact surface side with the conductive paste including the inner surface of the through hole of the electrode in the substrate is subjected to a roughening treatment. Therefore, the following processing is performed in a state in which the electrodes are formed on the transfer substrate, that is, the state shown in FIG. 4 (5) (three holes are opened, the narrow hole diameter is 75 μm, and the wide hole diameter is 80 μm). . In this embodiment, in order to ensure good electrical resistance with the conductive paste, in this embodiment, not black oxidation treatment in which copper oxide is formed on the surface, but plating such as gold, etching and blast treatment, etc. Perform mechanical processing. However, since these processes themselves are well-known techniques, description thereof is omitted.

金めっきによる本実施の形態では、ビア径が300μmで基板厚みが800μmの1つのビア抵抗は、初期が14mΩの抵抗であり、125℃、950時間後には41mΩとなった。   In the present embodiment using gold plating, one via resistance having a via diameter of 300 μm and a substrate thickness of 800 μm was initially 14 mΩ, and became 41 mΩ after 950 hours at 125 ° C.

以上、本発明をその幾つかの実施の形態に基づいて説明して来たが、本発明は何もそれらに限定されないのは勿論である。すなわち、例えば以下のようにしても良い。
(1)基板内の電極としてアルミ等を使用する又、他に金めっき等のめっき処理されたものを使用する等、基板、転写用基板や導電性ペースト更には製造に使用する薬品等に他の材料等を使用している。
(2)基板内の電極の肉厚等も他の寸法としている。更に電極の寸法やビアホー
ルの直径の如何によっては、貫通孔の断面形状は丸のみならず楕円、多角形など又、複数形成している。
As mentioned above, although this invention has been demonstrated based on the some embodiment, it cannot be overemphasized that this invention is not limited to them. That is, for example, the following may be performed.
(1) Use aluminum or the like as the electrode in the substrate, or use other plated materials such as gold plating, etc. Other than the substrate, transfer substrate, conductive paste, and chemicals used in manufacturing, etc. Materials are used.
(2) The thickness of the electrode in the substrate is also set to other dimensions. Further, depending on the size of the electrode and the diameter of the via hole, the cross-sectional shape of the through hole is not only a circle but also an ellipse or a polygon.

従来のビアホールで、収縮してスペースが発生し、電極との接触が悪くなるのを概念的に示す図である。It is a figure which shows notionally that a conventional via hole shrinks and a space is generated, resulting in poor contact with an electrode. 電極に貫通孔を有するビアホールで、貫通孔の内径が、基板の厚みの中心側へ行くほど小である参考図である。FIG. 6 is a reference diagram illustrating a via hole having a through hole in an electrode, and the inner diameter of the through hole is smaller toward the center of the thickness of the substrate. 本発明に係るビアホールで、貫通孔の内径が、基板の厚みの途中を最小若しくは最大としてひっかかりがあるようにすることにより、導電ペーストが収縮しても基板内の電極との接触が良好に維持される様子を概念的に示す図である。In the via hole according to the present invention, the inner diameter of the through hole is caught with the middle of the thickness of the substrate being minimized or maximized, so that the contact with the electrode in the substrate is maintained well even when the conductive paste contracts. It is a figure which shows notably a mode that it is performed. 電極に貫通孔を有する回路基板そのものの製造手順を示す図である。It is a figure which shows the manufacture procedure of the circuit board itself which has a through-hole in an electrode . 貫通孔を有するビアホール用の電極の製造手順を示す参考図である。It is a reference drawing which shows the manufacturing procedure of the electrode for via holes which has a through-hole . 本発明に係るビアホール用の電極の他の幾つかの実施の形態の製造手順の要部を示す図である。It is a figure which shows the principal part of the manufacture procedure of some other embodiment of the electrode for via holes which concerns on this invention.

符号の説明Explanation of symbols

10 プリプレグ(樹脂製の絶縁性基板)
20 ビアホール内の導電性ペースト
25 ビアホール内の導電性ペースト(製造前)
26 収縮した導電性ペースト(実施例の加速試験後)
40 ビアホール両端の貫通孔がある基板内の電極
42 電極の貫通孔
48 ビアホール両端の電極(従来技術)
50 転写用基板
51 電極の形成された転写用基板
60 感光性樹脂膜(ドライフィルム)
70 フォトリソグラフィー用マスク
80 エッチング用樹脂層
85 エッチングレジスト
86 マスクの開孔
90 エポキシ樹脂層
95 銅箔
10 Prepreg (resin insulating substrate)
20 Conductive paste in via hole 25 Conductive paste in via hole (before manufacture)
26 Shrinked conductive paste (after accelerated test of example)
40 Electrode in substrate with through hole at both ends of via hole 42 Through hole of electrode 48 Electrode at both ends of via hole (prior art)
50 Transfer Substrate 51 Transfer Substrate with Electrodes 60 Photosensitive Resin Film (Dry Film)
70 Photolithographic Mask 80 Etching Resin Layer 85 Etching Resist 86 Mask Opening 90 Epoxy Resin Layer 95 Copper Foil

Claims (4)

基板に形成されたビアホール内に樹脂に金属体を分散させた導電材を充填してなる層間接続部の基板内の電極が、中心に貫通孔を有し、該貫通孔の内部へ導電材が侵入し、かつ導電材が基板にフラッシュ回路的に埋設された電極の内側表面の一部と接している接続構造のビアホールであって、貫通孔の内径は、基板の厚みの途中最小若しくは最大としてひっかかりがあるようにすること、ならびに、該電極は、該導電材側の表面及び該貫通孔内面が粗化されていることを特徴とする接続構造のビアホール。 Electrode in the substrate interlayer connection portion formed by filling a conductive material obtained by dispersing metal body into the resin in the via holes formed in the substrate has a through hole in the center, the conductive material into the interior of the through hole there invaded, and a via-hole of the connecting structure in which part the contact of the conductive material the inner surface of the flash circuit to buried the electrodes on the substrate, the inner diameter of the through hole, the thickness of the substrate A via hole having a connection structure characterized in that there is a trapping with a minimum or maximum halfway , and the electrode has a roughened surface on the conductive material side and an inner surface of the through hole. 前記電極は、電気的に回路の一部であるランド若しくはパッド部材であることを特徴とする請求項1に記載の接続構造のビアホール。 The via hole of the connection structure according to claim 1, wherein the electrode is a land or a pad member that is electrically part of a circuit. 基板のビアホールに導電材が充填され、更にその上下の端面には、内部へ導電材が侵入した貫通孔が形成されている電極が配設されてなるビアホールの接続構造を有する回路基板用の電極の製造方法であって、転写用基板の表面に形成されたフォトレジスト膜からフォトリソグラフィを使用して上記電極及び回路となる部分のフォトレジストを取り去るめっき用基板製造ステップと、該ステップにて製造されためっき用基板をめっきして、フォトレジストの取り去られた場所に金属をめっきするめっきステップと、該めっきステップ終了後に転写用基板表面のフォトレジストを全て取り去る転写用電極基板完成ステップと、を有していることを特徴とする、請求項1に記載の回路基板のビアホール接続に使用する転写用電極の製造方法。 A circuit board electrode having a via hole connection structure in which a conductive material is filled in a via hole of a substrate, and an electrode in which a through hole into which the conductive material has penetrated is formed on the upper and lower end surfaces thereof. A method of manufacturing a plating substrate, wherein the photoresist film formed on the surface of the transfer substrate is removed from the photoresist film using photolithography to remove the portion of the photoresist that becomes the electrodes and circuits, and the manufacturing step A plating step of plating the plated substrate and plating the metal at a place where the photoresist has been removed, and a transfer electrode substrate completion step of removing all the photoresist on the surface of the transfer substrate after the completion of the plating step; The manufacturing method of the electrode for transfer used for the via-hole connection of the circuit board of Claim 1 characterized by the above-mentioned. 基板のビアホールに導電材が充填され、更にその上下の端面には、内部へ導電材が侵入した貫通孔が形成されている電極が配設されてなるビアホールの接続構造を有する回路基板用の電極の製造方法であって、転写用基板の表面に形成されたレジスト膜からエッチングを使用して上記電極及び回路となる部分のレジストを取り去るめっき用基板製造ステップと、該ステップにて製造されためっき用基板をめっきして、レジストの取り去られた場所に金属をめっきするめっきステップと、該めっきステップ終了後に転写用基板表面のレジストを全て取り去る転写用電極基板完成ステップと、を有していることを特徴とする、請求項1に記載の回路基板のビアホール接続に使用する転写用電極の製造方法。 A circuit board electrode having a via hole connection structure in which a conductive material is filled in a via hole of a substrate, and an electrode in which a through hole into which the conductive material has penetrated is formed on the upper and lower end surfaces thereof. And a plating substrate manufacturing step of removing a portion of the resist that is to be the electrode and circuit from the resist film formed on the surface of the transfer substrate by etching, and the plating manufactured in the step. A plating step of plating the substrate for plating and plating the metal at a place where the resist is removed, and a transfer electrode substrate completion step of removing all the resist on the surface of the transfer substrate after the plating step is completed. The method for producing a transfer electrode used for via-hole connection of a circuit board according to claim 1.
JP2003398605A 2003-11-28 2003-11-28 Electrode for connecting via holes with through holes Expired - Fee Related JP4470465B2 (en)

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WO2013111995A1 (en) * 2012-01-27 2013-08-01 주식회사 아모그린텍 Multilayer printed circuit board and method for manufacturing same

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JP4830505B2 (en) * 2006-01-19 2011-12-07 富士ゼロックス株式会社 Wiring method and donor substrate
JP4748279B2 (en) * 2006-04-13 2011-08-17 日立化成工業株式会社 Conductive paste, and prepreg, metal foil-clad laminate, and printed wiring board using the same
CN116981160A (en) * 2022-04-24 2023-10-31 华为技术有限公司 Electronic equipment, circuit board and manufacturing method of circuit board

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013111995A1 (en) * 2012-01-27 2013-08-01 주식회사 아모그린텍 Multilayer printed circuit board and method for manufacturing same

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