JP4466169B2 - Manufacturing method of substrate for semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device substrate comprising a plurality of wiring layers and having thin and high density wiring.

  Along with the advancement of electronic technology, there is an increasing demand for miniaturization, weight reduction, and high functionality of electronic information terminals. For this reason, high density is also strongly demanded for semiconductor device substrates. Conventionally, a substrate for a semiconductor device has a structure in which an insulating layer and a wiring pattern are alternately repeated. However, an electrical connection method between wiring patterns in each layer is made through a through hole or a via hole. Yes. That is, the cross-sectional structure is a structure in which “wiring layer 21 (wiring pattern and insulator around it)” and “insulating layer 22 (insulator and via hole)” are alternately stacked, that is, the wiring layer on which the wiring pattern is formed and In this structure, insulating layers having via holes formed only by circular patterns having a diameter of about 50 to 150 μm arranged corresponding to the upper and lower wiring patterns are alternately stacked (see FIG. 1).

  In addition to a normal multilayer substrate and a buildup multilayer substrate, a substrate having an all-layer IVH structure is also known. Various processes have been proposed for substrates with this structure. After prepregs that serve as insulating layers are drilled with a laser and filled with a conductive paste, conductive foils are stacked on the front and back surfaces in the same process as copper-clad laminates. After forming a material covered with copper foil, etching the conductive foil on the surface to form a wiring pattern (Patent Documents 1 to 3), or printing a spine-shaped conductive paste on the copper foil, after heat curing A prepreg and normal copper foil are stacked to form a material whose surface is covered with copper foil by a process similar to that for forming a copper-clad laminate, and a conductive pattern on the surface is etched to form a wiring pattern (Patent Document 4) ) And many similar techniques are known (see FIG. 2).

Recently, a photosensitive agent is applied to a special mesh substrate, and the exposed part is activated and electroless copper plating is performed to selectively form a conductive part and a non-conductive part penetrating vertically. A technique for forming a wiring pattern on the surface has been announced (Non-Patent Document 1).
However, any of these techniques is based on an insulating layer in which conductive portions (via holes) are formed, and a wiring pattern is formed on the surface, and the wiring layers and insulating layers (+ via holes) are alternately stacked.

  In the prior art, when forming a via hole for connecting the upper and lower wiring patterns, the diameter of the via hole is usually about φ100 to 200 μm, and the upper and lower via lands for receiving the via hole need to be 50 to 100 μm larger than that. It was. For example, if the via hole has a diameter of 150 μm, the via land size is 210 μm, which is 60 μm larger than that.

  On the other hand, the wiring pattern can be formed with a pitch of about 100 μm even if the process of the same technical level is used, and if the via land exists in the wiring pattern, the via land occupies the portion where the three wirings are arranged. Wiring density is extremely reduced. Further, a process for forming a via hole with a UV laser is known for products requiring higher density. In this case, a via having a diameter of up to about 50 μm can be formed. When the via diameter is 50 μm, the via land size is about 110 μm, which still inhibits one or two wires.

As described above, since the via hole greatly affects the high density of the wiring pattern, further miniaturization of the via hole and reduction of the difference between the via land size and the via diameter are desired. However, if the diameter of the via is about 50 μm or less, it is difficult to stably drill the via, and the plating of the via is further difficult including the pretreatment.

The above is a technical problem in forming a via hole, but also includes a facility problem such that a facility for forming a via such as a laser processing apparatus is required in addition to the wiring pattern forming facility.
Japanese Patent No. 3321537 Japanese Patent No. 2991032 Japanese Patent No. 3366458 Japanese Patent No. 3251711 Toshiba Review VOL. 57, no. 4 (2002): "New high-density wiring technology combining nanoporous materials and selective plating technology"

The present invention has been made in order to solve the above-mentioned problem, and enables thinning of the connection portion of the wiring pattern without using a facility for forming a via such as a laser processing apparatus. An object of the present invention is to provide a semiconductor device substrate having a high-density wiring pattern.
It is another object of the present invention to provide a method for manufacturing the semiconductor device substrate.

That is, in the first aspect of the present invention, (1) a step of forming the first wiring pattern and the surrounding insulator on a flat base substrate so that the surfaces thereof are substantially flush with each other; step of second wiring patterns provided a connection portion formed by stacking directly on the first wiring pattern, the periphery of the insulator of the second wiring pattern surface formed to be substantially coplanar And (3) a step of repeating the above step (2) for the required number of layers.
This is because an insulating material that fills the wiring pattern and its periphery is formed on a flat base substrate with approximately the same thickness, and the surface is formed to be substantially flush with the required number of layers. Is a manufacturing method for obtaining a desired substrate for a semiconductor device.

According to a second aspect of the invention, there is provided a method of manufacturing a substrate for a semiconductor device according to the first aspect, further comprising a step of removing at least a part of the flat base substrate after the step (3). It is a thing.

The invention according to claim 3 is characterized in that the flat base substrate is a metal plate, glass plate, plastic plate, or silicon substrate having a thickness of 50 to 700 μm. This is a manufacturing method of the semiconductor device substrate described.
This stipulates the base substrate material used for smooth and easily available semiconductors and display devices suitable for fine pattern formation and its general thickness.

  The substrate for a semiconductor device according to the present invention has a structure in which the upper and lower wiring patterns of the wiring layers adjacent to each other in the upper and lower sides are directly stacked, so that the multilayer portion does not include a conventional via hole (through hole or blind hole). Since connection is possible, the substrate for a semiconductor device having ultra-thin and high-density wiring is obtained.

As a result of intensive studies, the present inventor was able to solve the conventional problems as described above. FIG. 3 is a cross-sectional view of an example of a substrate for a semiconductor device according to the present invention. As shown in FIG. 3, the connection part of the substrate for a semiconductor device has a structure in which upper and lower wiring patterns (31 to 34) of wiring layers adjacent to each other are directly stacked. In addition, the upper and lower wiring patterns are arranged so as not to be in contact with each other at a portion other than the connecting portion or close to an interval equal to or less than a necessary insulation resistance value.
That is, since a conventional via hole (through hole or blind hole) is not required, the semiconductor device substrate is thin and has high-density wiring.

  Hereinafter, the present invention will be described more specifically based on examples, but is not limited thereto.

(Creation of 4-layer wiring board)
The second layer wiring pattern 2 and the third layer wiring pattern 3 are formed on the front and back sides, and both sides of the two-layer wiring board (FIG. 4A) in which the front and back sides are electrically connected by the via holes 1 are insulated. A film (ABF-70H (trade name), manufactured by Ajinomoto Fine Techno Co., Ltd.) was laminated, and the resin was cured by heating at 140 ° C. for 60 minutes. The insulating film surface was polished by buffing on both sides until the copper surfaces of the second and third layer wiring patterns were exposed (FIG. 4B).

  Next, after permanganic acid treatment was performed to roughen both surfaces of the insulating film, electroless copper plating was performed to form a seed layer 4 (FIG. 4C). Thereafter, a dry film (Sunfort AQ-2058 (trade name), manufactured by Asahi Kasei Co., Ltd.) having a thickness of 20 μm is laminated on both sides, and the first and fourth layer wiring patterns are respectively formed using a parallel light type exposure machine. The film was baked and developed with a 1% sodium carbonate solution to obtain a dry film pattern 5 (FIG. 4D). Thereafter, after plating the wiring pattern portion by electrolytic plating (FIG. 4E), the dry film is peeled off (FIG. 4F), and the seed layer is removed by flash etching, so that the first layer wiring A pattern 6 and a fourth-layer wiring pattern 7 were formed (FIG. 4G).

  Insulating films (ABF-70H (trade name), manufactured by Ajinomoto Fine Techno Co., Ltd.) are laminated on both sides in the same manner as before, and the resin is cured by heating at 140 ° C. for 60 minutes. Was polished until the copper surfaces of the wiring patterns of the first layer and the fourth layer were exposed by buffing, and a multilayer circuit board having a four-layer wiring was produced (FIG. 4 (h)).

(Making a three-layer wiring board with a heat sink)
Zirconium-based copper plate 8 having a thickness of 100 μm (C151 (trade name), manufactured by Mitsubishi Shindoh Co., Ltd., CDA alloy NO. C15100) (FIG. 5A) (FIG. 5A), dry film 9 having a thickness of 20 μm (Sunfort) AQ-2058 (trade name, manufactured by Asahi Kasei Co., Ltd.) is laminated, a negative pattern of the wiring pattern is baked on one surface with a parallel light type exposure machine, and the other surface is exposed to the entire surface. After development with a% sodium carbonate solution (FIG. 5B), electrolytic plating was performed at about 15 μm, and the dry film was peeled off with a 3% sodium hydroxide solution to form a third-layer wiring pattern 10 (FIG. 5). 5 (c)).

Next, an insulating film (ABF-70H (trade name), manufactured by Ajinomoto Fine Techno Co., Ltd.) is laminated on the side on which the wiring pattern of the third layer is formed, and the resin is cured by heating at 140 ° C. for 60 minutes. It was. The insulating film surface was polished by buffing until the copper surface of the third layer wiring pattern was exposed (FIG. 5D).
Next, a permanganate treatment was performed to roughen the surface of the insulating film, and then electroless copper plating was performed to form a seed layer 11 (FIG. 5E). Thereafter, a dry film (Sunfort AQ-2058 (trade name), manufactured by Asahi Kasei Co., Ltd.) having a thickness of 20 μm is laminated on both surfaces in the same manner as when the third-layer wiring pattern is formed, and a parallel light type exposure is performed. The negative pattern of the second layer wiring pattern was printed on the surface having the third layer wiring pattern on the machine, and the other surface was exposed to the entire surface and then developed with a 1% sodium carbonate solution (FIG. 5 (f)). Then, electrolytic plating (FIG. 5G), the dry film was peeled off, and a second layer wiring pattern 12 was formed (FIG. 5H). By repeating this process, a first-layer wiring pattern 13 was formed, and a multilayer circuit board having a three-layer wiring with a heat sink was created (FIG. 5 (j)).

(Creation of ultra-thin three-layer wiring board)
The surface on the wiring layer side of the multilayer circuit board (FIG. 6 (a)) having the three-layer wiring with a heat sink created in Example 2 is a dry film (Sunfort AQ-2058 (trade name), Asahi Kasei Co., Ltd.) having a thickness of 20 μm. (Made by Co., Ltd.) was protected by laminating, and the zirconium-based copper plate 8 on the other side was removed by etching to produce an ultrathin film three-layer wiring board (FIG. 6B).

  As mentioned above, although the specific example was described based on the Example, it is not limited to this. Moreover, in this invention, it is good also as a structure which coats the existing soldering resist 14 and coverlay as needed (FIG. 7), and also rust prevention, such as gold plating, tin plating, and heat-resistant preflux application | coating to a connection terminal You may perform the process for. Further, a stiffener (reinforcing plate) 15 may be mounted to improve handling properties (FIG. 8).

It is sectional drawing which shows the structure of the board | substrate for semiconductor devices by the conventional general buildup technique. It is sectional drawing which shows the structure of the board | substrate for semiconductor devices by the conventional thin board | substrate technique. It is sectional drawing which shows the structure of the board | substrate for semiconductor devices concerning this invention. 2 is a process explanatory diagram of Example 1. FIG. 6 is a process explanatory diagram of Example 2. FIG. 6 is a process explanatory diagram of Example 3. FIG. It is explanatory drawing which formed the solder resist. It is explanatory drawing which formed the stefner.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Via hole 2, 12 ... 2nd layer wiring pattern 3, 10 ... 3rd layer wiring pattern 4, 11 ... Seed layer 5 ... Dry film pattern 6, 13, ... First layer wiring pattern 7... Fourth layer wiring pattern 8. Zirconium-based copper plate 9... Dry film 14. Solder resist 15. Stiffener 21. ... Etching the conductive foil on the surface to form a wiring pattern 31, 32, 33, 34 ... Vertical wiring pattern 35 ... Insulator

Claims (3)

(1) forming a first wiring pattern and an insulating material around the first wiring pattern on a flat base substrate so that the surfaces thereof are substantially coplanar;
(2) a second wiring pattern is formed by stacking directly on the first wiring pattern connecting part of the following is provided, so that the periphery of the insulator of the second wiring pattern surface is substantially coplanar Forming the step,
(3) A step of repeating the above step (2) for the required number of layers,
The manufacturing method of the board | substrate for semiconductor devices characterized by having at least.   2. The method for manufacturing a substrate for a semiconductor device according to claim 1, further comprising a step of removing at least a part of the flat base substrate after the step (3). 3. The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein the flat base substrate is a metal plate, glass plate, plastic plate, or silicon substrate having a thickness of 50 to 700 [mu] m.

Images