JP4463097B2 - Data transfer system, data transfer method, and crossbar LSI - Google Patents

Description

  The present invention relates to a data transfer system and a data transfer method in which data transfer is performed between communication nodes via a link in a network system in which a plurality of links exist between a plurality of communication nodes, and data transfer between the communication nodes is relayed The present invention relates to a crossbar LSI.

  In a server device or the like, when a plurality of processors are mounted, a technique of connecting each processor with a crossbar LSI may be used. In the crossbar LSI, for example, an exchange processing unit that performs exchange processing for setting a data transfer path from a processor that is a transmission source communication node to a processor that is a transmission destination communication node, and a link adjustment unit that controls link adjustment The crossbar part which has is mounted (for example, refer patent document 1). In addition, the crossbar LSI includes a port unit that outputs data received from the processor to the crossbar unit and transmits data input from the crossbar unit. The crossbar unit outputs the data received and output by the input port in the port unit to the output port in the other port unit in order to transmit to the other processor or the crossbar LSI.

  FIG. 6 is a block diagram showing the configuration of the crossbar LSI described in Patent Document 1. In FIG. In the configuration shown in FIG. 6, a port unit including an input port 91A and an output port 91B, a port unit including an input port 92A and an output port 92B, a port unit including an input port 93A and an output port 93B, and an input port 94A The port section including the output port 94B and the crossbar section 90 constitute one crossbar LSI.

  In order to increase the speed of data transfer between processors, it is desirable that the data transfer speed be high. When the data transfer rate is increased, in consideration of the influence of temperature change and skew, generally, link adjustment using an adjustment signal is periodically performed in the port unit to tune each link.

  For example, Patent Document 2 describes a technique for adjusting an output AC current level, an output DC level, and the like by generating a test pattern and transmitting / receiving the test pattern when the link is tuned. That is, automatic link adjustment is performed by transmitting and receiving test patterns.

Japanese Patent Laying-Open No. 2004-110507 (paragraphs 0009-0011, FIG. 5) JP 2000-236323 A (paragraph 0008-0011, FIG. 2)

  When link adjustment is being performed, data transfer between the processors cannot be performed via the port unit, so that the execution time of the adjustment operation is preferably short so as not to reduce the throughput (data transfer efficiency). .

  In a network system that connects multiple communication nodes, data transfer is relayed due to differences in whether communication nodes are connected by cables or wiring on a package (board). The characteristics of each link differ due to differences in materials constituting the LSI. That is, an integrated circuit (IC), an LSI on which an IC is further integrated, a package on which the LSI is mounted, a wiring pattern on the package, a cable material connecting the LSIs, a cable length, a driver, a receiver, and various other factors Depending on the effect, the characteristics of each link will be different.

  However, in the conventional link adjustment method, link adjustment is performed at regular time intervals. Therefore, link adjustment is also performed for links that do not require adjustment. When the link is adjusted, the original data transfer cannot be performed on the link, so that the data transfer efficiency (throughput) is reduced. In addition, once an error is detected, the data transfer on the link where the error is detected is interrupted, and the data transfer is stopped in the network system until the adjustment processing, initialization process, diagnosis process, etc. of the link are completed. In such a configuration, adjustment processing, initialization processing, and diagnosis processing are not performed simultaneously on a plurality of links, but there are links that have not been processed. In the network system, data transfer is stopped, and data transfer efficiency is further reduced.

  Therefore, an object of the present invention is to provide a data transfer system, a data transfer method, and a crossbar LSI that can suppress a decrease in data transfer efficiency caused by link adjustment.

In the data transfer system according to the present invention, the communication node detects an error in data received from another communication node (for example, realized by the error detection circuit 58), and the error detected by the error detection unit. Link adjustment based on an error totaling means (for example, realized by an adder 59, an addition result storage unit 60, and an error sampling circuit 61) and the number of errors generated by the error totaling means. Link adjustment interval setting means (for example, realized by a timer setting value selection circuit 50, a -1 subtraction circuit 51, a timer counter 52, and a link adjustment detection circuit 54) , If the transferred frame data is frame data including a field indicating that the order guarantee is not required, the frame data is transferred. Mudeta the switching the transfer path to transfer via other links Adjustment link reconfiguration control circuit (for example,. Realized in link reconfiguration control circuit in the crossbar portion 18, 28) that includes a Features.

  The link adjustment interval setting means may increase the link adjustment execution interval as the error occurrence number of the data transferred through the link in a predetermined time is smaller, and shorten the link adjustment execution interval as the error occurrence amount increases. preferable.

  When the number of error occurrences of data transferred over a link for a certain fixed time exceeds the specified number, the data transfer on that link is stopped and the transfer path is set so that the data is transferred via another link. An error switching link reset control circuit (for example, realized by a transfer suppression circuit 63 in the link control unit 5 and a link reset control circuit in the crossbar units 18 and 28) may be provided.

The data transfer method according to the present invention includes an error detection means for detecting errors, an error count means for counting the number of error occurrences, a link adjustment interval setting means for determining a link adjustment execution interval, and an adjustment time for switching transfer paths. A data transfer method in which a plurality of links exist between a plurality of communication nodes including a link resetting control circuit, and data is transferred between the communication nodes via the links, and the data transfer method performs link adjustment at a predetermined time a is an error detection means detects an error in data received from another communication node, an error aggregation means aggregates the number of occurrences of errors detected every predetermined time, the link adjustment interval setting means, higher incidence of aggregated failure that a longer execution interval of the link adjustment, shortening the interval of the link adjustment greater the number of generated errors, adjustment link Setting control circuit, when the link adjustment execution, the frame data that has been transferred, when the frame data includes a field indicating that the order guarantee is not required, the frame data via the other link transfer The transfer path is switched as described above.

Advance the number of generated errors per predetermined time is divided into a plurality of stages, to define the interval of link adjustment corresponding to the respective links adjusting interval setting means, among the plurality of stages, the number of occurrences of the aggregated error The link adjustment may be executed at an execution interval corresponding to the stage to which it belongs.

The crossbar LSI according to the present invention includes error detection means for detecting errors in data received from other crossbar LSIs or processors, error counting means for counting the number of occurrences of errors detected by the error detection means, and error counting means A link adjustment interval setting means for determining a link adjustment execution interval based on the number of errors generated, and a field indicating that the frame data transferred at the time of link adjustment does not require an order guarantee. In the case of frame data, an adjustment-time link reset control circuit that switches a transfer path so as to transfer the frame data via another link is provided.

  When the number of error occurrences of data transferred over a link for a certain fixed time exceeds the specified number, the data transfer on that link is stopped and the transfer path is set so that the data is transferred via another link. An error link re-setting control circuit for switching may be provided.

According to the present invention, the optimum link adjustment interval can be automatically set for each link based on the frequency of error occurrence, the throughput of the data transfer system can be improved , and no order guarantee is required. Data link can be transferred using a free link even in link adjustment (including initialization and retransmission processing), so that if there is a link that can be used other than the link to be adjusted, another free link is available. The data frame can be transferred via the network, so that highly efficient data transfer is possible.

  Furthermore, by automatically performing link disconnection and link switching according to the error occurrence frequency, the link can be disconnected according to the error occurrence frequency and frame data can be transferred using another link. It is possible to prevent the overall system performance from being deteriorated due to the poor state.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a data transfer system according to the present invention. In the system shown in FIG. 1, signal lines 100, 101, 102, and 103 are connected between a device 1 as a communication node and another communication node (not shown). Signal lines 104, 105, 106, and 107 are connected between the device 1 and the device 2 as a communication node. Signal lines 108, 109, 110, and 111 are connected between the apparatus 2 and another communication node (not shown).

  The devices 1 and 2 as communication nodes have an exchange function for relaying data transmitted by other communication nodes to a communication node that is a transmission destination. Here, the case where the devices 1 and 2 are crossbar LSIs and the other communication node is a processor is taken as an example. That is, a data transfer system for transferring data between multiprocessors that perform parallel processing is taken as an example. Here, a case where a processor as a communication node is connected to the end of the apparatus 1 and a processor as a communication node is connected to the end of the apparatus 2 will be described as an example. As a communication node, a device having the same configuration as the devices 1 and 2 may be connected. Hereinafter, the communication node connected to the end of the apparatus 1 and the communication node connected to the end of the apparatus 2 may be referred to as a connection destination apparatus, respectively.

  In the device 1, link control units 10, 11, 12, and 13 are provided between the crossbar unit 18 that performs data exchange processing and the signal lines 100, 101, 102, and 103. In addition, link control units 14, 15, 16, and 17 are provided between the crossbar unit 18 and the signal lines 104, 105, 106, and 107, respectively. In the apparatus 2, link control units 20, 21, 22, and 23 are provided between the crossbar unit 28 that performs data exchange processing and the signal lines 104, 105, 106, and 107. In addition, link control units 24, 25, 26, and 27 are provided between the crossbar unit 28 and the signal lines 108, 109, 110, and 111, respectively. The configuration of the crossbar unit 18 and the configuration of the crossbar unit 28 are the same.

  In this embodiment, it is assumed that a link is formed by two link control units and a signal line connected between them. For example, one link is formed by the link control unit 14, the signal line 104, and the link control unit 20.

  The configurations of the link control units 10 to 17 and 20 to 27 shown in FIG. 1 are the same. FIG. 2 is a block diagram illustrating a configuration example of the link control units 10 to 17 and 20 to 27 illustrated in FIG. In FIG. 2, the link control units 10 to 17 and 20 to 27 are shown as the link control unit 5. The link control unit 5 includes a transmission / reception control unit (port unit) 70 that outputs data (serial data) to the signal line 205 and inputs data (serial data) from the signal line 206. The signal lines 205 and 206 correspond to any of the signal lines 100 to 111 in FIG. For example, when the link control unit 5 is regarded as the link control unit 10 illustrated in FIG. 1, the signal lines 205 and 206 correspond to the signal line 100.

  In the example shown in FIG. 2, the transmission / reception control unit 70 serializes serial data, a synchronization circuit 71 that synchronizes data with a clock signal, a PLL adjustment / deskew circuit 72 that performs PLL adjustment and absorbs variations between parallel data. A serial-parallel conversion circuit 73 is provided that converts the data into data and outputs the data, and converts the input serial data into parallel data. The transmission / reception control unit 70 transmits data input from the inside of the device (specifically, the selection circuit 57 in the example shown in FIG. 2) to the connection destination device via the signal line 205, and transmits the signal line 206 from the connection destination device. The data received via the network is output to the inside of the apparatus (specifically, in the example shown in FIG. 2, the transfer inhibiting circuit 63).

  In addition, the link control unit 5 counts a timer setting value selection circuit 50 that selects a time that defines the link adjustment interval, and a value (timer setting value) corresponding to the time selected by the timer setting value selection circuit 50 as an initial value. A timer counter 52 to be performed, and a -1 subtraction circuit 51 for subtracting one by one in synchronization with a clock signal from a value set in the timer counter 52 are included. The timer counter 52 loads the timer setting value selected by the timer setting value selection circuit 50 as an initial value when the error detection circuit 58 detects an error or when the link adjustment detection circuit 54 decides to perform link adjustment. To do.

  FIG. 3 shows an example of timer setting values selected by the timer setting value selection circuit 50. The timer set value selection circuit 50 selects a time interval (link adjustment interval) for executing link adjustment. Specifically, the timer set value selection circuit 50 determines the timer according to the number of errors output by the link disconnection determination circuit 62 based on the number of errors by the error sampling circuit 61 that samples the number of errors generated per certain time. Select a setting value. For example, when the number of errors is greater than a specified value (initial value commensurate with the performance of the link), the link adjustment interval is shortened by a certain rate (eg, -10%, -20%, -30%, -n%). When the number of errors is smaller than the specified value, the link adjustment interval is extended at a certain rate (for example, + 10%, + 20%, + 30%, + n%).

  The link control unit 5 includes a link adjustment detection circuit 54 that detects whether or not to perform link adjustment. The link adjustment detection circuit 54 indicates that the timer counter 52 has timed up, that is, the value set in the timer counter 52 has changed from “1” to “0”, or that the error detection circuit 58 has detected an error. The link adjustment is determined to be performed, and “1” as a link adjustment flag is set in the link adjustment flag register 55. The state of the link adjusting flag is also output to the crossbar unit 18 via the signal line 200. In the following description, it is assumed that the link control unit 5 is provided in the device 1 shown in FIG. If the link control unit 5 is provided in the device 2 shown in FIG. 1, the state of the link adjustment flag is output to the crossbar unit 28.

  Further, the link control unit 5 selects either frame data input from the crossbar unit 18 side via the signal line 201 or data output from the adjustment pattern output circuit 56 and outputs the selected data to the transmission / reception control unit 70. A selection circuit 57 is included. The adjustment pattern output circuit 56 outputs a link disconnection message when a disconnection instruction is output from the link disconnection determination circuit 62, and outputs a link adjustment pattern when “1” is set in the link adjustment flag register 55. To do. The selection circuit 57 selects the data output from the adjustment pattern output circuit 56 when “1” is set in the link adjustment flag register 55 or when a disconnection instruction is output from the link disconnection determination circuit 62. . Note that the disconnection instruction from the link disconnection determination circuit 62 is also output to the crossbar unit 18 via the signal line 202.

  Further, the link control unit 5 receives an error from the connection destination device via the signal line 206 and detects an error in the frame data via the transmission / reception control unit 70, and when the error detection circuit 58 detects an error. Via an adder 59 that adds the number of detected errors and the number of errors (cumulative number) stored in the addition result storage unit 60 and stores the addition result in the addition result storage unit 60, and the signal line 204 An error sampling circuit 61 that samples the number of errors (number of error occurrences) stored in the addition result storage unit 60 by the set pulse input from the crossbar unit 18 is included. The link disconnection determination circuit 62 compares the number of errors, which is the sampling result of the error sampling circuit 61, with a threshold for determining whether to disconnect the link, and if the number of errors exceeds the threshold, Outputs a disconnection instruction. In the link disconnection determination circuit 62, a threshold for determining whether or not to disconnect the link is set in advance from a diagnostic processor or the like.

  The frame data received from the connection destination device via the signal line 206 and passing through the transmission / reception control unit 70 is further output to the crossbar unit 18 side via the signal line 203 via the transfer suppression circuit 63. The transfer suppression circuit 63 prevents the frame data from the transmission / reception control unit 70 from being output to the crossbar unit 18 side when the error detection circuit 58 detects an error.

  In addition to the circuit that executes the switching function, the crossbar units 18 and 28 receive at least a circuit that periodically outputs a set pulse via the signal line 204 and a link disconnection message from another device. In addition, a link reset control circuit that recognizes link disconnection and switches the transfer path so that frame data transferred on the disconnected link is transferred via another link (link reset control circuit in case of error). ) And are included. In addition, when the link adjustment is started, if the frame data that has been transferred is frame data that does not require an order guarantee, the transfer route is set so that the frame data is transferred via another link. A link reset control circuit for switching (adjustment link reset control circuit) is included.

  Next, the operation will be described with reference to the flowchart of FIG. 4 and the explanatory diagram of FIG. FIG. 5 shows a frame configuration example of the frame data used in this embodiment.

  When data transfer between the device 1 and the device 2 becomes possible, for example, when a system including the device 1 and the device 2 is started, the link control units 10 to 17 and 20 to 27 first set timer setting values. The selection circuit 50 selects a timer setting value (a default value 5000 (1388h) shown in FIG. 3) that is a value that defines the link adjustment interval. Then, the timer set value is set in the timer counter 52 (step S1). The -1 subtraction circuit 51 subtracts 1 from the value set in the timer counter 52 in synchronization with the clock signal. That is, the set value of the timer counter 52 is decremented by 1 in synchronization with the clock signal.

  The error detection circuit 58 checks whether there is an error in the frame data received from the connection destination device via the signal line 206 (step S2). If the error detection circuit 58 does not detect an error, the transfer suppression circuit 63 outputs the frame data to the crossbar unit 18 via the signal line 203. The crossbar unit 18 transfers the frame data to the connection destination device via the timer control unit connected to the signal line leading to the connection destination device (transmission destination device).

  The timer counter 52 is decremented by the -1 subtracting circuit 51 in synchronism with the clock signal unless the output of the OR circuit 53 is "0" and the value of the timer counter 52 is "0". Stored value.

  If the value of the timer counter 52 is not “0”, the frame data transfer is continued (steps S3 and S14). When the value of the timer counter 52 becomes “0”, that is, when the time corresponding to the timer set value has elapsed (step S3), the timer counter 52 again sets the value output from the timer set value selection circuit 50. set. At the same time, the link adjustment detection circuit 54 detects that the value of the timer counter 52 has become “0”, and sets “1” in the link adjustment flag register 55. That is, link adjustment is instructed. When “1” is set in the link adjustment flag register 55, the adjustment pattern output circuit 56 generates and outputs a link adjustment pattern (step S4). The link adjustment detection circuit 54 is a circuit for instructing link adjustment. When the value of the timer counter 52 changes from “1” to “0”, or when the error detection circuit 58 detects an error, the link adjustment detection flag is set. Set to 1 ”.

  The link adjustment flag set in the link adjustment flag register 55 is set to “1” by the link adjustment detection circuit 54. However, the link adjustment flag continues to be set until the link adjustment using the link adjustment pattern is completed. When the output circuit 56 transmits the final adjustment pattern, it is reset to “0” (step S5). When the link adjustment flag is “0”, the selection circuit 57 transmits the data frame received via the signal line 201 to the connection destination device via the transmission / reception unit 70 and the link adjustment flag is “1”. In some cases, the link adjustment pattern output from the adjustment pattern output circuit 56 is selected.

  The link adjustment pattern is transmitted to the connection destination device via the transmission / reception control unit 70. When the transmission / reception control unit 70 of the link control unit in the connection destination apparatus receives the link adjustment pattern, the transmission / reception control unit 70 executes link adjustment as described in, for example, Japanese Patent Application Laid-Open No. 2004-110507. The adjustment pattern output circuit 56 transmits a fixed pattern such as, for example, 00000000-0Z, 010101101-1Z, 00110011-1Z, and the like as the link adjustment pattern at the time of link adjustment.

  The adjustment pattern output circuit 56 outputs a link disconnection message when a disconnection instruction signifying execution of link disconnection is input from the link disconnection determination circuit 62. The link disconnection message is transmitted to the connection destination device via the transmission / reception control unit 70. In the connection destination device, when the crossbar unit 28 detects reception of the link disconnection message, the link disconnection message is disconnected.

  Further, when the link adjustment is performed in steps S4 and S5, the crossbar unit 18 checks the out-of-order transaction field of the subsequent frame data (step S6).

  FIG. 5 shows an example of frame data used in this embodiment. In the first frame, OOTF indicates an out-of-order transaction field. When this field is “0”, it indicates that the frame data requires an order guarantee. When the field is “1”, no order guarantee is required. Indicates that there is a frame data (frame data generated later may be transferred first). The frame data is defined as one instruction (or packet) from the first frame to the nth frame corresponding to the data length.

  When the out-of-order transaction field is “0”, the crossbar unit 18 determines that the frame data needs to be guaranteed in order and becomes an instruction to be overtaken. Frame data transfer via the signal line 201 is suppressed during initialization, diagnosis, and retransmission processing. When the out-of-order transaction field is “1”, it is not necessary to guarantee the order of the instructions. Therefore, the crossbar unit 18 determines a link that can transfer data from a plurality of other links, and performs OOTF. = 1 The frame data transfer path is switched to a link capable of data transfer, and the data transfer is continued (step S7).

  If the error detection circuit 58 detects an error in step S2, the transfer suppression circuit 63 invalidates the data in which the error is detected. That is, the data is not transferred. The error detection circuit 58 performs an ECC check or a CRC check on the data received from the connection destination device via the signal line 206. When an error is detected based on the check, an adder 59 for adding the number of errors, a transfer suppression circuit 63 for interrupting the transfer of the error-detected data, and instructing link adjustment due to the error detection "1" indicating an error detection notification is output to the link adjustment detection circuit 54. When the link adjustment detection circuit 54 receives a notification that an error has been detected from the error detection circuit 58, the link adjustment detection circuit 54 executes link initialization / adjustment in the same manner as in steps S4 and S5. Thereafter, a retransmission sequence is executed.

  The adder 59 adds the addition result storage unit 60 and the output of the error detection circuit 58 and stores the addition value in the addition result storage unit 60. When the set pulse output from the crossbar unit 18 is input via the signal line 204, the error sampling circuit 61 samples the number of errors stored in the addition result storage unit 60 (step 9). Note that the crossbar unit 18 outputs a set pulse once every hour, for example. Therefore, the error sampling circuit 61 periodically samples the number of errors that have occurred within a certain time. This fixed time can be arbitrarily set by, for example, a diagnostic processor.

  The link disconnection determination circuit 62 determines that the number of error occurrences within a predetermined time exceeds a predetermined number of error occurrences based on a signal output from the error sampling circuit 61, that is, a signal indicating the number of errors generated within the predetermined time. In this case, it is a circuit that determines link disconnection and outputs a disconnection instruction. Note that an arbitrary value based on the system configuration or the like can be set as a predetermined number of error occurrences from a diagnostic processor or the like. When the link disconnection determination circuit 62 determines link disconnection, the link disconnection determination circuit 62 also outputs a disconnection instruction to the crossbar unit 18 via the signal line 202.

  In response to the disconnection instruction, the crossbar unit 18 switches to perform data transfer using another link. Also, the disconnection instruction is output to the adjustment pattern output circuit 56, and the adjustment pattern output circuit 56 generates and outputs a link disconnection message (step S11). When the disconnection instruction is output from the link disconnection determination circuit 62, the selection circuit 57 selects data output from the adjustment pattern output circuit 56. Therefore, the link disconnection message is output to the transmission / reception control unit 70 via the selection circuit 57, and further transmitted to the connection destination device via the signal line 205, and the link disconnection processing is also performed in the connection destination device (step S12). ).

  In step S10, when the link disconnection determination circuit 62 determines that the number of error occurrences does not exceed the predetermined number of error occurrences, a timer handled by the timer set value selection circuit 50 according to the number of error occurrences. A signal for adjusting the set value is generated (see FIG. 3) and output to the timer set value selection circuit 50. Thereafter, the timer set value selection circuit 50 selects the timer set value indicated by the signal output from the link disconnection determination circuit 62 (step S13).

  In the example shown in FIG. 3, a code (Select in FIG. 3) that defines the number of error occurrences per fixed time from 0 to 6 or more and selects the link adjustment interval corresponding to each is defined. That is, the number of error occurrences per predetermined time is divided into a plurality of stages, and the link adjustment execution interval corresponding to each is defined. And then. A signal for adjusting the timer set value corresponding to the code corresponding to the number of error occurrences is output to the timer set value selection circuit 50. An appropriate link adjustment interval time is set in the timer counter 52 in accordance with the number of error occurrences. That is, link adjustment is executed at an execution interval corresponding to the stage to which the total number of error occurrences belongs among a plurality of stages. In addition, in each link control part 10-17, 20-27, you may enable it to set a respectively different division | segmentation.

  As described above, in this embodiment, since the means for automatically setting the link adjustment interval according to each link characteristic (error occurrence frequency) is provided, each link based on the error occurrence frequency is provided. The optimal link adjustment interval can be automatically set, and the throughput of the crossbar LSI can be improved.

  In addition, OOTF (out-of-order transaction field) is provided in the data frame, and means for transferring data frames that do not require an order guarantee using a free link even during link adjustment, initialization, and retransmission processing is provided. When there is a link that can be used other than the link to be adjusted, the data frame can be transferred via another free link, and highly efficient data transfer is possible.

  In addition, since a means for automatically disconnecting and switching the link according to the error occurrence frequency is provided, the link can be disconnected according to the error occurrence frequency and frame data can be transferred using other links. Therefore, it is possible to prevent the overall system performance from being deteriorated due to the bad state of a certain link. Conventionally, when errors frequently occur, the operator is notified and the link is cut by the operator. In this embodiment, the link can be automatically cut.

  In the above embodiment, the crossbar LSI is exemplified as the devices 1 and 2, but the present invention is not limited to being applied to the crossbar LSI, and the present invention is not limited to a processor and an information processing device having a data transfer function. The present invention can be widely applied to LSIs and devices having a data transfer function, such as router devices.

  The present invention can be applied to an application for controlling link adjustment in a network system. In particular, the present invention can be suitably applied even when the link characteristics of a plurality of links differ depending on the constituent material, the installation environment, and the usage situation.

It is a block diagram which shows the example of 1 structure of the data transfer system by this invention. It is a block diagram which shows the structural example of a link control part. It is explanatory drawing which shows the example of a timer setting value. It is a flowchart which shows operation | movement of a data transfer system. It is explanatory drawing which shows the example of a frame structure of frame data. It is a block diagram which shows the structure of the conventional crossbar LSI.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Apparatus 100-111 Signal line 5,10-17,20-27 Link control part 18,28 Crossbar part 50 Timer setting value selection circuit 51-1 subtraction circuit 52 Timer counter 53 OR circuit 54 Link adjustment detection circuit 55 Link Adjustment flag register 56 Adjustment pattern output circuit 57 Selection circuit 58 Error detection circuit 59 Adder 60 Addition result storage unit 61 Error sampling circuit 62 Link disconnection determination circuit 63 Transfer inhibition circuit 70 Transmission / reception control unit 71 Synchronization circuit 72 PLL adjustment / deskew Circuit 73 Serial parallel conversion circuit

Claims (7)

In a data transfer system in which a plurality of links exist between a plurality of communication nodes and data is transferred between the communication nodes via the links, and the data transfer system performs link adjustment at a predetermined time.
The communication node is
An error detection means for detecting an error in data received from another communication node;
Error counting means for counting the number of occurrences of errors detected by the error detection means;
A link adjustment interval setting means for determining a link adjustment execution interval based on the number of errors generated by the error aggregation means;
When the frame data that has been transferred at the time of link adjustment is frame data that includes a field indicating that the order guarantee is not required, the transfer path is configured to transfer the frame data via another link. A data transfer system comprising: an adjustment link resetting control circuit for switching between the two. The link adjustment interval setting means lengthens the link adjustment execution interval as the error occurrence number of the data transferred through the link in a predetermined time decreases, and shortens the link adjustment execution interval as the error occurrence amount increases. 1. The data transfer system according to 1. When the number of error occurrences of data transferred over a link for a certain fixed time exceeds the specified number, the data transfer on that link is stopped and the transfer path is set so that the data is transferred via another link. claim 1 or claim 2 data transfer system according with error during link reconfiguration control circuit for switching. An error detecting means for detecting an error; an error counting means for counting the number of error occurrences; a link adjustment interval setting means for determining a link adjustment execution interval; and an adjustment link reset control circuit for switching a transfer path. In a data transfer method in which a plurality of links exist between a plurality of communication nodes and data is transferred between the communication nodes via the link, and the data transfer method performs link adjustment at a predetermined time.
The error detection means detects an error in data received from another communication node;
It said error aggregation means aggregates the number of occurrences of errors detected every predetermined time,
Wherein the link adjusting interval setting means, as the number of occurrence of aggregated failure that a longer execution interval of the link adjustment, shortening the interval of the link adjustment greater the number of generated errors,
When the link reconfiguration control circuit at the time of adjustment performs frame adjustment, if the frame data transferred is frame data including a field indicating that the order guarantee is not required, the frame data is transferred to another frame data. A data transfer method comprising switching a transfer path so as to transfer via a link. Divide the number of error occurrences per predetermined time into multiple stages in advance, define the link adjustment execution interval corresponding to each,
Links adjusting interval setting means, said among the plurality of stages, aggregated data transfer method according to claim 4, wherein the number of occurrences of errors to perform a link adjustment execution interval corresponding to belong step. In crossbar LSIs that transfer data to or from other crossbar LSIs or processors,
Error detection means for detecting errors in data received from other crossbar LSIs or processors;
Error counting means for counting the number of occurrences of errors detected by the error detection means;
A link adjustment interval setting means for determining a link adjustment execution interval based on the number of errors generated by the error aggregation means;
When the frame data that has been transferred at the time of link adjustment is frame data that includes a field indicating that the order guarantee is not required, the transfer path is configured to transfer the frame data via another link. A crossbar LSI, comprising: an adjustment link resetting control circuit for switching between. When the number of error occurrences of data transferred over a link for a certain fixed time exceeds the specified number, the data transfer on that link is stopped and the transfer path is set so that the data is transferred via another link. The crossbar LSI according to claim 6, further comprising a switching error reset control circuit for switching.

Images