JP4419575B2 - RESISTANCE ELEMENT AND ITS MANUFACTURING METHOD, BIAS CIRCUIT AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Google Patents

Description

  The present invention relates to a resistance element mounted on a power amplifier applied to, for example, a transmitter of a wireless system, a manufacturing method thereof, a bias circuit, and a manufacturing method of a semiconductor device.

  In a power amplifier (power amplifier module) of a radio transmitter, particularly a power amplifier module applied to a transmitter for a mobile phone, setting the bias current of a field effect transistor (FET) as an amplifying element to a predetermined value is a power It is an important factor that determines the performance (power added efficiency, distortion characteristics, etc.) of the amplifier module.

  In order to determine the bias voltage and bias current of the field effect transistor, a bias circuit is connected to the gate. This bias circuit uses a method in which a voltage supplied from a gate bias supply terminal is divided by a resistor and applied to the gate. However, when the threshold value of the field-effect transistor varies due to a process error, there is a problem that the operating current does not become constant when the voltage is divided by a constant resistance value.

  In addition, although the bias voltage to the gate is adjusted after the completion of the field effect transistor, trimming of the resistance is required for each field effect transistor, and the area of the bias circuit that increases the trimming time is increased. There was a problem of increasing.

A bias circuit for solving this problem has been proposed (see Patent Document 1). The invention proposed in Patent Document 1 uses the same structure as a channel of a field effect transistor as a resistor. As described above, when a resistance element having a resistance value that matches the threshold value of the completed field effect transistor can be fabricated in the semiconductor substrate in conjunction with the process variation of the threshold voltage, the size of the bias circuit can be reduced. Therefore, it is possible to greatly reduce the labor of bias adjustment.
JP-A-9-283710

  However, when the threshold voltage becomes positive, the sheet resistance of the channel is on the order of MΩ to GΩ, and there is a problem that such a resistance element cannot be used in the bias circuit. This is because the channel of the enhancement mode field effect transistor is basically designed so that no current flows when the voltage applied to the gate electrode is 0V.

  For field-effect transistors used for power amplifiers in particular, enhancement-type transistors are manufactured that increase the threshold voltage and reduce the off-current when the gate voltage is 0 V in order to reduce power consumption. The demand to do is strong.

  As described above, it can be applied even when the threshold voltage is positive, the sheet resistance of the channel can be reduced to about several hundreds Ω, and the resistance element having a structure applicable to a circuit such as a bias circuit and its manufacture A method is desired. Further, there is a need for a bias circuit that can be applied even when the threshold voltage is positive and that can keep the bias current constant without performing trimming.

  The present invention has been made in view of the above circumstances, and its purpose is that even if the threshold value of a field effect transistor fluctuates due to process variations, the resistance value is linked to the fluctuation of the threshold value. It is an object of the present invention to provide a resistance element having a practical resistance value that matches the threshold value of the field effect transistor and a manufacturing method thereof.

  Another object of the present invention is to provide a bias circuit capable of keeping the bias current constant even if the threshold value of the field effect transistor varies due to process variations.

  Another object of the present invention is that even if the threshold value of the field effect transistor fluctuates due to process variations, the resistance value is linked to the fluctuation of the threshold value, and matches the threshold value of the completed field effect transistor. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a resistance element having a practical resistance value on the same substrate as a field effect transistor.

To achieve the above object, the present onset Ming, a resistive element field-effect transistor formed on a semiconductor substrate formed with a channel of a first conductivity type, a first conductive formed on the semiconductor substrate The second conductivity type impurity is introduced in a channel resistance using the channel of the mold, a pair of terminals for passing current through the channel resistance, and a slit-like pattern extending along the direction of current flowing through the channel resistance. And a resistance adjusting unit that adjusts a band energy of the semiconductor substrate including the channel resistance to adjust a resistance value of the channel resistance.

  In the resistance element of the present invention described above, the channel of the first conductivity type of the field effect transistor formed in another region of the semiconductor substrate is used as the channel resistance. And the resistance adjustment part which adjusts the band energy of the semiconductor substrate containing channel resistance and adjusts the resistance value of channel resistance is formed with the slit-shaped pattern. The resistance adjuster is formed in a slit-like pattern extending along the direction of the current flowing through the channel resistance, so that the resistance value of the channel resistance is secured while securing a current path for obtaining a practical resistance value. Adjusted. Further, by using the channel of the first conductivity type of the field effect transistor as the channel resistance, a resistance value having a correlation with the threshold value of the field effect transistor can be obtained.

To achieve the above object, the present onset Ming, bias adjustment voltage supplied from the bias voltage supply terminal by resistance-dividing, the bias voltage to the gate terminal of the field effect transistor having a channel of the first conductivity type A circuit having a bias voltage supply terminal, a reference potential, a first resistance element, and a second resistance element; and a first terminal of the first resistance element and the second resistance. A first terminal of an element is connected; the connection point is connected to the gate terminal of the field effect transistor; a second terminal of the first resistance element is connected to the bias voltage supply terminal; A second terminal of the element is connected to the reference potential, and the second resistance element is formed on the same semiconductor substrate as the field effect transistor, and the channel of the first conductivity type formed on the semiconductor substrate is formed. And channel resistance of the first conductivity type using said second conductivity type impurity in the slit-like pattern extending along the direction of the current flowing through the channel resistance is formed by introducing, the semiconductor substrate including the channel resistance A resistance adjusting unit that adjusts the band energy of the channel resistance to adjust the resistance value of the channel resistance.

  In the above-described bias circuit of the present invention, the second resistance element having a correlation with the threshold value of the field effect transistor is connected between the reference potential and the gate terminal of the field effect transistor. Therefore, even when the threshold value of the field effect transistor fluctuates, the resistance value of the second resistance element increases or decreases according to the increase or decrease of the threshold value. That is, when the threshold value increases, the resistance value increases, and the voltage applied to the gate terminal of the field effect transistor increases due to the resistance voltage division. When the threshold value decreases, the resistance value decreases, and the voltage applied to the gate terminal of the field effect transistor decreases due to the resistance voltage division.

To achieve the above object, the present onset Ming, a first conductivity type channel field effect transistor, in other regions of the semiconductor substrate to a method of manufacturing a resistance element utilized as a channel resistance, the semiconductor substrate A step of forming a mask layer having a slit-like pattern opening; and introducing a second conductivity type impurity into the semiconductor substrate using the mask layer as a mask to adjust a band energy of the semiconductor substrate including the channel resistance. Forming a resistance adjusting portion for changing the resistance value of the channel resistance.

In the resistance element manufacturing method of the present invention described above, the channel of the first conductivity type of the field effect transistor formed in another region of the semiconductor substrate is used as the channel resistance. Therefore, a resistance value having a correlation with the threshold value of the field effect transistor can be obtained.
In addition, a resistance adjusting portion that adjusts the resistance value of the channel resistance by adjusting the band energy of the semiconductor substrate including the channel resistance is formed in a slit-like pattern. Adjusting the resistance value of the channel resistance while securing a current path for obtaining a practical resistance value by forming the resistance adjustment part with a slit-like pattern extending along the direction of the current flowing through the channel resistance can do.

To achieve the above object, the present onset Ming, the first region of the same semiconductor substrate to form a field effect transistor, a method of manufacturing a semiconductor device for forming a resistance element in the second region, the Forming a first conductivity type channel of the field effect transistor in a first region of the semiconductor substrate and simultaneously forming a first conductivity type channel resistance of the resistance element in the second region; and Forming a mask layer having a pattern opening in the first region and a slit-shaped pattern opening in the second region, and applying a second conductivity type impurity in the pattern of the mask layer to the semiconductor substrate. It is introduced, to form a junction gate in the first region to adjust the resistance value of the channel resistance by adjusting the band energy of the semiconductor substrate including the channel resistance in the second region And a step of forming an anti-adjuster.

In the method for manufacturing a semiconductor device of the present invention, the first conductivity type channel of the field effect transistor is formed in the first region of the semiconductor substrate, and at the same time, the first conductivity type channel resistance of the resistance element is formed in the second region. Is forming.
Further, a slit-like pattern opening is formed in the second region in the mask layer for forming the gate structure in the first region. Then, a resistance adjusting portion is formed in the second region by using a process of transferring the pattern to the semiconductor substrate using the mask layer as a mask and forming a gate structure in the first region.
As a result, the field effect transistor and the resistance element are manufactured on the same substrate through the same process, so that a resistance element having a correlation with the threshold value of the field effect transistor can be manufactured.

  According to the resistance element and the manufacturing method thereof of the present invention, even if the threshold value of the field effect transistor fluctuates due to process variations, the resistance value is linked to the fluctuation of the threshold value. A resistive element having a practical resistance value that matches the threshold value can be realized.

  According to the bias circuit of the present invention, the bias current can be made constant even if the threshold value of the field effect transistor varies due to process variations.

  According to the semiconductor device manufacturing method of the present invention, even if the threshold value of the field effect transistor fluctuates due to process variations, the resistance value is linked to the fluctuation of the threshold value, and the threshold value of the completed field effect transistor is increased. A semiconductor device in which a resistance element having a practical resistance value matching the value and a field effect transistor are formed on the same substrate can be manufactured.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a power amplifier module (power amplifier) including a bias circuit according to the present embodiment.

  As shown in FIG. 1, a power amplifier 1 includes an FET (field effect transistor) 2, a bias circuit 3 connected to the gate terminal G of the FET 2 at a connection point ND11, and a bias voltage supplied with, for example, a positive voltage Vgg. It has a supply terminal 4 and a power supply voltage supply terminal 5 to which a power supply voltage Vdd is supplied. The bias circuit 3 includes a first resistance element R11 and a second resistance element R12 connected in series between the bias voltage supply terminal 4 and the ground potential GND.

The first terminal of the first resistance element R11 and the first terminal of the second resistance element R12 are connected, and the connection point ND11 is connected to the gate terminal G of the FET2.
The second terminal of the first resistance element R11 is connected to the bias voltage supply terminal 4, and the second terminal of the second resistance element R12 is connected to the ground potential GND.
The drain terminal D of the FET 2 is connected to the power supply voltage supply terminal 5 and the source terminal S is connected to the ground potential (reference potential) GND.

  Normally, a trimming resistor is used for the first resistor element R11 or the second resistor element R12, but in this embodiment, no trimming resistor is used. Instead, the FET 2 and the second resistance element R12 are formed on the same semiconductor substrate. The first resistance element R11 is configured by a channel resistance unrelated to the threshold value of the FET 2, a metal thin film resistance, or the like. Note that the first resistance element R11 is also preferably formed on the same substrate as the FET2.

  In the power amplifier 1, a high frequency signal is applied to the gate terminal G of the FET 2. The bias circuit 2 sets a bias voltage to be applied to the gate terminal G based on the positive voltage supplied from the bias voltage supply terminal 4. The FET 2 amplifies at an operating point based on the bias voltage and outputs a bias current including a high frequency component.

  The bias circuit 3 according to the present embodiment has a function of applying a bias voltage proportional to the change to the connection point ND11 in accordance with a change in the threshold value of the FET 2 due to process variations without performing trimming. More specifically, since the second resistance element R12 constituting the bias circuit 3 is fabricated on the same semiconductor substrate simultaneously with the FET 2, if the threshold value of the FET 2 varies due to process variations, the second resistance element R12 is similarly applied. Since the resistance value of the second resistance element R12 changes in conjunction with the second resistance element R12, the second resistance element R12 has a resistance value that matches the threshold voltage of the completed FET2.

  FIG. 2 is a schematic cross-sectional view of the FET 2 and the second resistance element R12 formed on the same semiconductor substrate.

  In FIG. 2, the FET 2 is configured by a pseudomorphic high electron mobility transistor (PHEMT) that realizes high electron mobility by allowing lattice mismatch in the epitaxial substrate. This is an example in which the resistance element R12 is manufactured using a PHEMT epitaxial growth substrate. In the present embodiment, as an example, the first conductivity type is n-type, and the second conductivity type is p-type.

  A barrier layer 13 made of a III-V group compound semiconductor is formed on a semi-insulating single crystal GaAs substrate 11 through a buffer layer 12 made of GaAs to which no impurity is added.

The barrier layer 13 is made of, for example, a semiconductor made of AlGaAs mixed crystal containing Al having a composition ratio of 0.2 to 0.3, and includes a high resistance region 13a having a thickness of about 200 nm that does not contain impurities, and a high concentration n-type impurity. As follows, a carrier supply region 13b having a thickness of about 4 nm to which Si is added in an amount of about 2 to 6 × 10 ¹⁸ / cm ³ and a high resistance region 13c having a thickness of about 2 nm to which no impurities are added are sequentially stacked from the buffer layer 12 side. It has a structure. A channel layer 14 is formed on the barrier layer 13.

  The channel layer 14 is made of a semiconductor having a narrower bandgap than the semiconductor constituting the barrier layer 13, for example, a semiconductor made of InGaAs mixed crystal containing In to which no impurity is added at a composition ratio of 0.1 to 0.2. Yes. Thus, carriers (electrons) are supplied to and accumulated in the channel layer 14 from a carrier supply region 13b of the barrier layer 13 and a carrier supply region 15b of the high-resistance barrier layer 15 described later. Thereby, the channel layer 14 constitutes an n-type channel through which electrons travel. A barrier layer 15 is formed on the channel layer 14.

Similar to the barrier layer 13, the barrier layer 15 is made of a semiconductor made of AlGaAs mixed crystal containing Al having a composition ratio of 0.2 to 0.3, and includes a high resistance region 15a having a thickness of about 2 nm not containing impurities, A carrier supply region 15b having a thickness of about 4 nm to which Si is added as an n-type impurity at a concentration of about 2 to 6 × 10 ¹⁸ / cm ^3, and a high resistance region 15c having a thickness of about 70 to 200 nm to which no impurity is added, The channel layer 14 is sequentially stacked from the side.

  In the high resistance region 15c, p-type impurity regions 17a and 17b doped with a p-type impurity such as Zn up to a distance of 10 nm or more from the channel layer 14 are formed. The p-type impurity region 17a constitutes a junction gate of the junction transistor FET2, and the p-type impurity region 17b constitutes a resistance adjusting portion of the resistance element R2.

  Insulating films 16 and 19 made of silicon nitride having a thickness of about 300 nm are formed on the surface of the high resistance region 15c. An opening exposing the p-type impurity region 17a is formed in the insulating film 16, and a gate electrode 18 connected to the p-type impurity region 17a is formed in the opening. The gate electrode 18 has a structure in which Ti, Pt, and Au are sequentially stacked from the substrate side.

  In the insulating films 16 and 19, two openings are formed in the formation region of the FET 11 to expose the barrier layer 15 at an appropriate interval. Further, in the formation region of the second resistance element R12, two openings are formed to expose the barrier layer 15 with an appropriate interval. In each opening, an electrode 21 in ohmic contact with the barrier layer 15 is formed. The two electrodes 21 on the region side of the FET 2 become the source terminal S or the drain terminal D. The two electrodes 21 on the region side of the second resistance element R12 serve as a pair of terminals that allow current to flow through the second resistance element R12. The electrode 21 is configured by sequentially laminating gold germanium (AuGe), nickel (Ni), and gold (Au) from the substrate side.

  As described above, the second resistance element R12 applied to the bias circuit according to the present embodiment uses the channel layer 14 used for the FET 2 as the channel resistance. A p-type impurity region 17b is formed in the upper layer of the channel layer 14 in order to adjust the channel resistance.

  FIG. 3 is a plan view of the second resistance element. 2 on the second resistance element R12 side corresponds to the cross-sectional view taken along the line A-A 'of FIG.

  As shown in FIG. 3, in the second resistance element R12 according to the present embodiment, the p-type impurity region 17b constituting the resistance adjustment unit has the channel layer 14 (having channel resistance on the second resistance element R12 side). It is formed in a slit-like pattern that extends along the direction of the current flowing through the. When the p-type impurity region 17b is formed in the upper layer, the band energy of the semiconductor substrate including the channel resistance (here, the entire layer from the substrate 11 to the barrier layer 15) is adjusted, and the p-type impurity region 17b The resistance value of the channel layer 14 in the portion formed in the upper layer becomes very large and almost no current flows.

  For this reason, if the p-type impurity region 17b is formed on the entire upper surface of the channel layer 14, the resistance value of the second resistance element R12 becomes MΩ to GΩ. In contrast, in the present embodiment, since the p-type impurity region 17b is formed in a slit-like pattern, a current flows in the channel layer 14 in a portion where the p-type impurity region 17b is not formed in the upper layer. The resistance value can be reduced to a practical value of about several hundred Ω.

  The threshold voltage in the FET 2 depends on the channel structure and the gate structure (concentration and depth of the p-type impurity region 17a, gate length). Since the second resistance element R12 according to this embodiment includes the channel resistance using the same channel layer 14 as the FET 2, and the same p-type impurity region 17b as the p-type impurity region 17a serving as the diffusion gate of the FET 2, If the threshold value of the FET 2 varies due to process variations, the resistance value of the second resistance element R12 also changes in conjunction.

  That is, when the threshold value of FET2 increases, the resistance value of the second resistance element R12 increases. Therefore, the bias voltage at the connection point ND11 increases, and a decrease in the bias current is suppressed. On the other hand, when the threshold value of the FET 2 decreases, the resistance value of the second resistance element R12 decreases. Accordingly, the bias voltage at the connection point ND11 is lowered, and the fluctuation of the bias current is suppressed. Since the resistance value (sheet resistance) of the second resistance element R12 is about several hundreds Ω, it functions as a bias circuit.

  Actually, when the threshold value Vth of the FET 2 and the resistance value of the second resistance element R12 were measured when the above-mentioned JPHEMT was manufactured, a correlation as shown in FIG. 4 was obtained. In the figure, CV1 is measured when a channel resistor having a width of 30 μm and a length of 10 μm is used as the second resistance element R12, and 30 p-type impurity regions 17b are arranged at a width of 0.5 μm and an interval of 0.5 μm. It is a result. CV2 is a measurement result when channel resistance of 30 μm width and 10 μm length is used as the second resistance element R12, and 15 p-type impurity regions 17b are arranged at a width of 1 μm and an interval of 1 μm.

  As shown in FIG. 4, it can be seen that the resistance value of the second resistance element R12 increases as the threshold value Vth of the FET2 increases. Furthermore, it can be seen that by controlling the width, interval, and number of slit-like patterns in the second impurity region 17b, the change in resistance value with respect to the change in the threshold value of the FET 2 can be adjusted. As the number of patterns of the p-type impurity region 17b increases with respect to the width of the channel resistance, the rate of change in resistance increases.

  For example, when the positive voltage supplied to the bias voltage supply terminal 4 is 3 V, the bias voltage is 0.5 V when the threshold voltage of the FET 2 is 0.4 V, and the threshold voltage of the FET 2 is 0.5 V. In the case of adjusting the bias voltage to 0.6 V at this time, for example, the first resistance element is set to 2.5 kΩ. The resistance of the second resistance element R12 has a correlation such that the resistance is 500Ω when the threshold value of the FET2 is 0.4V and 625Ω when the threshold value of the FET2 is 0.5V. If the structure of the second resistance element R12 is set, the bias voltage can be controlled without any problem.

  As described above, according to the second resistance element R12 according to the present embodiment, even if the threshold value of the FET 2 fluctuates due to process variations, the resistance value is linked to the fluctuation of the threshold value. It has a practical resistance value that matches the threshold value of FET2.

  Therefore, according to the bias circuit of the present invention configured by applying the above-described resistance element, the bias current can be made constant even if the threshold value of the FET 2 varies due to process variations.

  Next, a method for manufacturing a semiconductor device in which the FET 2 and the second resistance element R12 are formed on the same semiconductor substrate will be described with reference to FIGS.

  First, as shown in FIG. 5A, a buffer layer 12 is formed by epitaxially growing GaAs not containing impurities on a substrate 11 made of GaAs. On the buffer layer 12, an AlGaAs layer without addition of impurities, an n-type AlGaAs layer with addition of Si as an impurity, and an AlGaAs layer without addition of impurities are sequentially epitaxially grown, and a high resistance region 13 a, a carrier supply region 13 b and a high resistance region 13 c are stacked. The barrier layer 13 is formed.

  Next, on the barrier layer 13, InGaAs containing no impurities is epitaxially grown to form a channel layer 14. Further, AlGaAs without addition of impurities, n-type AlGaAs with addition of Si and AlGaAs without addition of impurities are sequentially epitaxially grown on the channel layer 14 to obtain a high resistance region 15a, a carrier supply region 15b, and a high resistance region 15c. Is formed.

  Next, as shown in FIG. 5B, an insulating film (mask layer) 16 is formed on the barrier layer 15 by depositing silicon nitride by, eg, CVD (Chemical Vapor Deposition).

  Next, as shown in FIG. 6C, using the resist as a mask, the insulating film 16 in the region for forming the resistance element and the region for forming the gate of the FET is removed by RIE (Reactive Ion Etching) to open the openings 16a, 16b is formed. Thereafter, the resist is removed. The pattern of the opening 16a on the FET2 side formed in the insulating film 16 is a gate pattern, and the pattern of the opening 16b on the second resistance element R12 side is a slit pattern as shown in FIG. The insulating film 16 corresponds to the mask layer of the present invention, but the material is not particularly limited.

Next, as shown in FIG. 6D, for example, the substrate is heated to 600 °, and Zn serving as a p-type impurity is vapor-phase diffused in the openings 16 a and 16 b of the insulating film 16, so that the barrier layer 15 is constant. P-type impurity regions 17a and 17b having a depth of 2 are formed.
Here, it is possible to dope the p-type impurity by ion implantation. However, in this case, it is necessary to activate the doped impurity by high-temperature heat treatment, so vapor phase diffusion is preferable. Here, when vapor phase diffusion is performed, the diffusion depth is controlled by time control.

  Next, as shown in FIG. 7E, a resist having an opening in the opening 16a is formed, a Ti / Pt / Au laminated film is deposited as a gate metal, and a portion other than the gate electrode is formed by a lift-off method. The gate metal is removed and the gate electrode 18 is formed. Thereby, a gate electrode 18 connected to the p-type impurity region 17a is formed in the opening 16a of the insulating film 16.

  Next, as shown in FIG. 7F, an insulating film 19 is formed by depositing silicon nitride on the entire surface of the wafer by, for example, the CVD method.

  Next, as shown in FIG. 7G, two openings exposing the barrier layer 15 are formed in the insulating films 16 and 19 on the formation region side of the second resistance element R12 by, for example, etching using a resist. Then, two openings for exposing the barrier layer 15 are formed in the insulating films 16 and 19 on the formation region side of the FET 2.

  As a subsequent process, for example, a gold germanium alloy AuGe, nickel Ni, and gold Au are sequentially deposited on the entire surface while leaving the resist pattern, and a metal layer is formed by a lift-off method, and an unnecessary portion of the metal layer is removed together with the resist pattern. Then, leaving the metal layer only in the electrode formation portion, alloying by, for example, a heat treatment of about 400 ° C., and forming the pair of terminals of the second resistance element and the electrode 21 that becomes the source terminal or the drain terminal, The semiconductor device shown in FIG. 2 is manufactured.

  According to the resistance element manufacturing method and the semiconductor device manufacturing method according to the above-described embodiment, the second resistance element R12 using the semiconductor substrate on which the FET 2 is formed can be formed simultaneously with the FET 2. Cost reduction can be achieved. Further, since the FET 2 and the second resistance element R12 are formed on the same substrate, the size can be reduced.

(Second Embodiment)
In the first embodiment, the example in which the second resistance element R12 is manufactured using the substrate structure of the FET2 having the junction gate structure has been described. However, in the present embodiment, the second structure using the substrate structure of the FET2 having the recess gate structure is used. An example of fabricating the resistance element 2 will be described.

  FIG. 8 is a schematic cross-sectional view of the FET 2 and the second resistance element R12 formed on the same semiconductor substrate.

  In FIG. 8, since the configuration of the single crystal GaAs substrate 11 to the barrier layer 15 in the semiconductor substrate is the same as that of the first embodiment, description thereof is omitted.

  In the formation region of the FET 2, the high resistance region 15 c of the barrier layer 15 is engraved to a predetermined depth from the channel layer 14, and a recess structure gate electrode 18 that forms the barrier layer 15 and the Schottky barrier in the engraved portion 17 c is formed. Is formed. In this specification, the structure in which the substrate directly under the gate electrode 18 is engraved is referred to as a recess structure.

  In the formation region of the second resistance element R12, the high resistance region 15c of the barrier layer 15 has a carved portion 17d carved with the same depth as the carved portion 17c. The engraved part 17d constitutes a resistance adjusting part of the second resistance element R2.

  As in the first embodiment, insulating films 16 and 19 made of silicon nitride are formed on the surface of the high resistance region 15c. In the insulating films 16 and 19, two openings for exposing the barrier layer 15 are formed at appropriate intervals in the formation region of the FET 2. Further, in the formation region of the second resistance element R12, two openings are formed to expose the barrier layer 15 with an appropriate interval. In each opening, an electrode 21 in ohmic contact with the barrier layer 15 is formed as in the first embodiment. The two electrodes 21 on the region side of the FET 2 become the source terminal S or the drain terminal D. The two electrodes 21 on the region side of the second resistance element R12 serve as a pair of terminals that allow current to flow through the resistance element R12.

  Similar to the first embodiment, the second resistance element R12 applied to the bias circuit according to the present embodiment uses the channel layer 14 used for the FET 2 as a channel resistance. In order to adjust the channel resistance, an engraved portion 17d is formed in the upper layer of the channel layer 14.

  FIG. 9 is a plan view of the second resistance element. The cross-sectional view of FIG. 8 on the second resistance element R12 side corresponds to the cross-sectional view taken along the line A-A 'of FIG.

  As shown in FIG. 9, in the second resistance element R12 according to the present embodiment, the engraved portion 17d constituting the resistance adjustment portion flows through the channel layer 14 (having channel resistance on the second resistance element R12 side). It is formed in a slit-like pattern extending along the direction of current. When the engraving portion 17d is formed in the upper layer, the band energy of the semiconductor substrate including the channel resistance (herein, the entire layer from the substrate 11 to the barrier layer 15) is adjusted by the influence of the surface depletion layer, and the engraving portion The resistance value of the channel layer 14 in the portion where 17d is formed in the upper layer becomes very large and almost no current flows.

  For this reason, if the engraved portion 17d is formed on the entire upper surface of the channel layer 14, the resistance value of the second resistance element R12 becomes MΩ to GΩ. On the other hand, in this embodiment, since the engraved portion 17d is formed in a slit-like pattern, current flows in the channel layer 14 in a portion where the engraved portion 17d is not formed in the upper layer, and therefore the resistance value is It can be reduced to a practical value of about 100Ω.

  The threshold voltage in the FET 2 depends on the channel structure and the gate structure (the depth of the engraved portion and the gate length). The second resistance element R12 according to the present embodiment includes a resistance channel using the same channel layer 14 as the FET 2, and a carved portion 17d similar to the FET 2 engraved portion 17d. If the value fluctuates, the resistance value of the second resistance element R12 also changes in conjunction.

  That is, when the threshold value of FET2 increases, the resistance value of the second resistance element R12 increases. Therefore, the bias voltage at the connection point ND11 increases, and the fluctuation of the bias current is suppressed. On the other hand, when the threshold value of the FET 2 decreases, the resistance value of the second resistance element R12 decreases. Accordingly, the bias voltage at the connection point ND11 is lowered, and the fluctuation of the bias current is suppressed. Since the resistance value (sheet resistance) of the second resistance element R12 is about several hundreds Ω, it functions as a bias circuit.

  Further, similarly to the first embodiment, by controlling the width, interval, and number of slit-shaped patterns of the engraved portion 17d, it is possible to adjust the change in the resistance value with respect to the change in the threshold value of the FET2. As the number of patterns of the engraved portion 17d increases with respect to the width of the channel resistance, the rate of change in resistance increases.

  As described above, according to the second resistance element R12 according to the present embodiment and the bias circuit configured by applying the second resistance element, the same effects as in the first embodiment can be obtained. it can.

  Regarding the method of manufacturing the semiconductor device in which the FET 2 and the second resistance element R12 are formed on the same semiconductor substrate, the insulating film is formed in the step of introducing the p-type impurity shown in FIG. 6D described in the first embodiment. The engraved portions 17c and 17d may be formed by etching the barrier layer 15 using 16 as an etching mask, and the others can be manufactured in the same procedure as in the first embodiment. The insulating film 16 serving as an etching mask corresponds to the mask layer of the present invention, but a normal resist mask may be used as the mask layer.

  Also by the resistance element and the method for manufacturing a semiconductor device according to the present embodiment, it is possible to reduce the cost and the size as in the first embodiment.

(Third embodiment)
FIG. 10 is a circuit diagram showing another configuration example of the power amplifier including the bias circuit according to the present invention. The power amplifier 40 according to this embodiment is a configuration example of a power amplifier module (power amplifier) in which FETs are arranged in multiple stages.

As shown in FIG. 10, the power amplifier 40 according to this embodiment includes an input matching connected between a bias circuit 43 of an FET 41, a bias circuit 44 of an FET 42, and a connection point 41 of the bias circuit 43 and an input terminal T _IN. and an output matching circuit 47 connected between the drain terminal D of the connection point ND42 between connected stages to the matching circuit 46, FET 42 and the output terminal T _OUT of the drain terminal D and the bias circuit 44 of the circuit 45, FET 41 Have.

  The bias circuit 43 includes a first resistance element R41 and a second resistance element R42 connected in series between a bias voltage supply terminal 48 to which a positive voltage Vgg is supplied and a ground potential GND. A connection point ND41 between the resistor element R41 and the second resistor element R42 is connected to the gate terminal G of the FET 41. The drain terminal D of the FET 41 is connected to the supply terminal 49 of the power supply voltage Vdd, and the source terminal S is grounded.

  The bias circuit 44 includes a first resistance element R43 and a second resistance element R44 connected in series between a bias voltage supply terminal 48 to which a positive bias voltage Vgg is supplied and a ground potential GND. A connection point ND42 between the first resistance element R43 and the second resistance element R44 is connected to the gate terminal G of the FET. The drain terminal D of the FET 42 is connected to the supply terminal 49 of the power supply voltage Vdd, and the source terminal S is grounded.

  In the power amplifier 40 having the above configuration, the second resistance element R42 and the second resistance element R44 are formed on the same semiconductor substrate as the FET 41 and the FET 42. The first resistance elements R41 and R43 are configured by channel resistance unrelated to the threshold values of the FETs 41 and 42, metal thin film resistance, or the like. The first resistance elements R41 and R43 are also preferably formed on the same substrate as the FETs 41 and 42.

  The structures of the second resistance elements R42 and R44 formed on the same semiconductor substrate as the FET 41 and FET 42 are the same as those described in the first embodiment or the second embodiment.

  Even in the configuration of the power amplifier as described above, the same effects as those of the first embodiment or the second embodiment can be obtained.

  The present invention is not limited to the description of the above embodiment. For example, in the present embodiment, the enhancement type FET that applies a positive voltage to the gate terminal has been described. However, the present invention can be similarly applied to a case where a negative voltage is applied to the gate terminal. Accordingly, a wide range of threshold values can be handled.

  For example, the present invention can be applied to a JFET transistor. In this case, Si is first implanted into the GaAs substrate as an n-type (first conductivity type) channel. After annealing and activating the n-type impurity, an insulating film of a selective diffusion mask is deposited. A portion to be a gate is opened in the FET region, and an opening is formed in a slit pattern in the resistor element region. Thereafter, Zn which is a p-type (second conductivity type) impurity is diffused. As the threshold value changes positively, the resistance value of the resistance element changes so as to increase. By using this resistance element in a transistor bias circuit, the bias current can be kept constant even if the threshold voltage varies.

Further, the substrate 11 is not limited to GaAs, but can be applied to an InP-based substrate. In this case, the channel layer 14 uses an InAs-based semiconductor, and the barrier layers 13 and 15 use a semiconductor having an energy band gap larger than that of the channel layer 14.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a figure which shows the structural example of the power amplifier module (power amplifier) provided with the bias circuit which concerns on 1st Embodiment. It is typical sectional drawing of FET formed in the same semiconductor substrate and 2nd resistance element in 1st Embodiment. It is a top view of the 2nd resistance element shown in FIG. It is a figure which shows correlation with the threshold value of FET, and the resistance value of a 2nd resistance element. It is process sectional drawing of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing of the manufacturing method of the semiconductor device which concerns on this embodiment. It is typical sectional drawing of FET formed in the same semiconductor substrate and 2nd resistance element in 2nd Embodiment. It is a top view of the 2nd resistance element shown in FIG. It is a figure which shows the structural example of the power amplifier module (power amplifier) provided with the bias circuit which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power amplifier, 2 ... Field effect transistor (FET), 3 ... Bias circuit, 4 ... Bias voltage supply terminal, 5 ... Power supply voltage supply terminal, 11 ... Substrate, 12 ... Buffer layer, 13 ... Barrier layer, 13a ... High Resistance region, 13b ... carrier supply region, 13c ... high resistance region, 14 ... channel layer, 15 ... barrier layer, 15a ... high resistance region, 15b ... carrier supply region, 15c ... high resistance region, 16 ... insulating film, 17a, 17b: p-type impurity region, 17c, 17d ... engraved portion, 18 ... gate electrode, 19 ... insulating film, 21 ... electrode, R11, R12, R41, 42 ... resistance element, 41, 42 ... FET, 43, 44 ... bias Circuit 45... Input matching circuit 46 46 interstage matching circuit 47 output matching circuit 48 bias voltage supply terminal 49 power supply voltage supply terminal

Claims (10)

A resistance element formed on a semiconductor substrate on which a field effect transistor having a first conductivity type channel is formed,
Channel resistance using the channel of the first conductivity type formed in the semiconductor substrate;
A pair of terminals for passing current through the channel resistance;
The second resistance type impurity is introduced in a slit-like pattern extending along the direction of the current flowing through the channel resistance, and the resistance of the channel resistance is adjusted by adjusting the band energy of the semiconductor substrate including the channel resistance. A resistance element having a resistance adjustment unit for adjusting a value. A resistance element formed on a semiconductor substrate on which a field effect transistor having a first conductivity type channel is formed,
Channel resistance using the channel of the first conductivity type formed in the semiconductor substrate;
A pair of terminals for passing current through the channel resistance;
The semiconductor substrate is engraved with a slit-like pattern extending along the direction of the current flowing through the channel resistance, and the band energy of the semiconductor substrate including the channel resistance is adjusted to adjust the resistance value of the channel resistance. The resistance adjustment section to adjust
A resistance element having A bias circuit for resistance-dividing a voltage supplied from a bias voltage supply terminal to adjust a bias voltage to a gate terminal of a field effect transistor having a first conductivity type channel;
The bias voltage supply terminal;
A reference potential;
A first resistance element;
A second resistance element;
Have
A first terminal of the first resistance element and a first terminal of the second resistance element are connected, and the connection point is connected to the gate terminal of the field effect transistor;
A second terminal of the first resistance element is connected to the bias voltage supply terminal;
A second terminal of the second resistive element is connected to the reference potential;
The second resistance element is:
Formed on the same semiconductor substrate as the field effect transistor,
A channel resistance of a first conductivity type using the channel of the first conductivity type formed in the semiconductor substrate;
The second resistance type impurity is introduced in a slit-like pattern extending along the direction of the current flowing through the channel resistance, and the resistance of the channel resistance is adjusted by adjusting the band energy of the semiconductor substrate including the channel resistance. A bias circuit having a resistance adjustment unit for adjusting a value. The field effect transistor, a bias circuit according to claim 3 have a junction gate containing a second conductivity type impurity. A bias circuit for resistance-dividing a voltage supplied from a bias voltage supply terminal to adjust a bias voltage to a gate terminal of a field effect transistor having a first conductivity type channel;
The bias voltage supply terminal;
A reference potential;
A first resistance element;
A second resistance element;
Have
A first terminal of the first resistance element and a first terminal of the second resistance element are connected, and the connection point is connected to the gate terminal of the field effect transistor;
A second terminal of the first resistance element is connected to the bias voltage supply terminal;
A second terminal of the second resistive element is connected to the reference potential;
The second resistance element is:
Formed on the same semiconductor substrate as the field effect transistor,
A channel resistance of a first conductivity type using the channel of the first conductivity type formed in the semiconductor substrate;
The semiconductor substrate is engraved with a slit-like pattern extending along the direction of the current flowing through the channel resistance, and the band energy of the semiconductor substrate including the channel resistance is adjusted to adjust the resistance value of the channel resistance. The resistance adjustment section to adjust
A bias circuit. The field effect transistor, a bias circuit according to claim 5 wherein the have a recess structure in which the semiconductor substrate is engraved directly under the gate terminal. A method of manufacturing a resistance element that uses a channel of a first conductivity type of a field effect transistor as a channel resistance in another region of a semiconductor substrate,
Forming a mask layer having a slit-like pattern opening on the semiconductor substrate;
Introducing a second conductivity type impurity into the semiconductor substrate using the mask layer as a mask, and adjusting a band energy of the semiconductor substrate including the channel resistance to form a resistance adjustment unit that changes a resistance value of the channel resistance; A method for manufacturing a resistance element comprising: A method of manufacturing a resistance element that uses a channel of a first conductivity type of a field effect transistor as a channel resistance in another region of a semiconductor substrate,
Forming a mask layer having a slit-like pattern opening on the semiconductor substrate;
Etching the semiconductor substrate using the mask layer as a mask, and adjusting a band energy of the semiconductor substrate including the channel resistance to form a resistance adjustment unit that changes a resistance value of the channel resistance;
The manufacturing method of the resistive element which has this. A method of manufacturing a semiconductor device in which a field effect transistor is formed in a first region of the same semiconductor substrate and a resistance element is formed in a second region,
Forming a first conductivity type channel of the field effect transistor in the first region of the semiconductor substrate and simultaneously forming a first conductivity type channel resistance of the resistance element in the second region;
Forming a mask layer having a pattern opening in the first region of the semiconductor substrate and a slit-like pattern opening in the second region;
A second conductivity type impurity is introduced into the semiconductor substrate in a pattern of the mask layer to form a junction gate in the first region, and a band energy of the semiconductor substrate including the channel resistance in the second region. Forming a resistance adjusting unit that adjusts and adjusts the resistance value of the channel resistance. A method of manufacturing a semiconductor device in which a field effect transistor is formed in a first region of the same semiconductor substrate and a resistance element is formed in a second region,
Forming a first conductivity type channel of the field effect transistor in the first region of the semiconductor substrate and simultaneously forming a first conductivity type channel resistance of the resistance element in the second region;
Forming a mask layer having a pattern opening in the first region of the semiconductor substrate and a slit-like pattern opening in the second region;
Etching the semiconductor substrate with the pattern of the mask layer to form a gate electrode having a recess structure in the first region, and adjusting a band energy of the semiconductor substrate including the channel resistance in the second region Forming a resistance adjuster for adjusting a resistance value of the channel resistance;
A method for manufacturing a semiconductor device comprising:

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