JP4401039B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit incorporating internal circuits such as a plurality of processors and logic blocks, and more particularly to a debug circuit that supports software debugging.
[0002]
[Prior art]
For debugging of the processor built in the semiconductor integrated circuit, the test access port (TCK, TMS, TDI, TDO, TRST) of JTAG and other terminals are usually used from the outside of the semiconductor integrated circuit to the inside of the processor, Alternatively, a method is used in which a debugging support circuit such as an external JTAG circuit (a circuit including a TAP controller compliant with IEEE1149.1) is controlled.
[0003]
Conventional Example 1
FIG. 5 is a block diagram showing a semiconductor integrated circuit incorporating a conventional processor. In FIG. 5, 1-1 and 1-2 are processors, and 2-1 and 2-2 are JTAG circuits. Here, the processors 1-1 and 1-2 have JTAG circuits 2-1 and 2-2 each including a plurality of JTAG scan registers (not shown), which are JTAG test access ports (TCK, TMS). , TDI, TDO, TRST) can exchange signals with the outside.
[0004]
In a semiconductor integrated circuit incorporating such a processor, the JTAG circuits 2-1 and 2-2 are connected in series to the TDI terminal and the TDO terminal, and the JTAG scan register is connected in series. It is common to debug 1, 1-2.
[0005]
Next, the operation will be described.
Corresponding to the number of JTAG scan registers chained by serial connection of the processors 1-1 and 1-2, a predetermined clock is input from the TCK terminal, the JTAG circuits 2-1 and 2-2 become active, and the test pattern is output from the TDI terminal. Is input, and the two processors 1-1 and 1-2 are debugged at a time. Thereafter, similarly, a predetermined clock is input from the TCK terminal, and the debug result is output to the outside from the TDO terminal.
Thus, the conventional method of JTAG on-chip debugging is to connect the JTAG scan registers of a plurality of processors in series.
[0006]
Conventional Example 2
Alternatively, there is a method of debugging only the selected processor by inserting a selector between the JTAG test terminal (TAP) and the processor. FIG. 6 is a block diagram of a semiconductor integrated circuit incorporating such a conventional processor. In FIG. 6, 1-1 and 1-2 are processors, 2-1 and 2-2 are JTAG circuits, and 60 is It is a selector circuit. The difference from Conventional Example 1 is that an external select terminal (SEL) is provided and a selector circuit 60 controlled by this select terminal is inserted.
[0007]
Next, the operation will be described.
According to the SEL signal input from the external select terminal, the selector circuit 60 controls the JTAG circuit included in one of the processors 1-1 and 1-2. For example, the JTAG circuit 2- of one processor 1-1 is controlled. 1 is being controlled, the other processor 1-2 side is controlled not to operate the JTAG circuit 2-2, for example, by holding the test logic reset state. As a result, it is possible to select one of the processors 1-1 and 1-2 to be debugged and perform debugging.
[0008]
[Problems to be solved by the invention]
Since the conventional semiconductor integrated circuit is configured as described above, in the conventional example 1, as shown in FIG. 5, the JTAG scan registers of the processors 1-1 and 1-2 are replaced with the JTAG circuits 2-1 and 2-2. Are connected in series via each other, the number of shift clocks required for setting instructions in the instruction registers of the TAP controllers of the processors 1-1 and 1-2 and setting data in the data registers increases. For this reason, there is a problem that the time required for controlling the processor and downloading data to the internal memory and external memory of the processor by the debugger control device outside the semiconductor integrated circuit is increased.
[0009]
Further, when the types of the plurality of processors are different, there is a problem that it is difficult to simultaneously control the TAP controllers of the plurality of processors by the external debugger program.
[0010]
Further, as shown in FIG. 6, the conventional example 2 has a problem that the manufacturing cost of the semiconductor integrated circuit is increased by providing the external terminal.
[0011]
The present invention has been made to solve the above-described problems, and facilitates JTAG on-chip debugging of an LSI equipped with internal circuits such as a plurality of processors and logic blocks without increasing external terminals. An object of the present invention is to obtain a semiconductor integrated circuit capable of controlling an internal circuit and shortening a time required for downloading data to a memory.
[0012]
[Means for Solving the Problems]
The semiconductor integrated circuit according to the present invention is connected to first and second internal circuits each having a JTAG circuit, and a selector circuit that constitutes a debugging support circuit together with the JTAG circuit, and is connected to the selector circuit and has an external terminal A JTAG test access port, and a JTAG test as a select terminal of a selector circuit for selecting an internal circuit to be debugged during on-chip debugging of the first and second internal circuits using the debug support circuit The TRST terminal of the access port is used.
[0013]
The semiconductor integrated circuit according to the present invention includes first and second internal circuits each having a JTAG circuit, a JTAG test access port connected to the first and second terminals, and a TRST terminal of the first and second internal circuits. And an inverter circuit provided between any one of the two internal circuits, and the debugging support circuit configured by the JTAG circuit and the inverter executes debugging of either the first or second internal circuit Is.
[0014]
The semiconductor integrated circuit according to the present invention includes a plurality of internal circuits each provided with a JTAG circuit, a JTAG test access port connected to the JTAG test circuit and constituting an external terminal, and a counter connected to the TRST terminal and the TCK terminal. A debug support circuit including a JTAG circuit and a first control circuit that inputs a TRST signal and a TCK signal via the TRST terminal and the TCK terminal, respectively. One of the plurality of internal circuits is debugged by the block.
[0015]
The semiconductor integrated circuit according to the present invention is connected to a plurality of internal circuits each having a JTAG circuit, a JTAG test access port connected to the JTAG test access port and constituting an external terminal, and a TMS terminal and a TCK terminal of the JTAG test access port. And a second support circuit that constitutes a functional block including a counter, and a debug support circuit configured by the JTAG circuit and the second control circuit receives the TMS signal and the TCK signal via the TMS terminal and the TCK terminal, respectively. Input is performed, and any one of a plurality of internal circuits is debugged by the function block.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a block diagram of a semiconductor integrated circuit according to Embodiment 1 of the present invention, in which 1-1 and 1-2 are processors (internal circuits), and 2-1 and 2-2 are JTAG circuits. Reference numeral 10 denotes a selector circuit using the JTAG test access port TRST terminal as a control terminal. Here, the JTAG circuits 2-1 and 2-2 and the selector circuit 10 constitute a debugging support circuit.
[0017]
Next, the operation will be described.
In FIG. 1, when the TRST signal applied from the outside by the selector circuit 10 is HIGH level, the TRST signal sig1 on the processor 1-1 side is set to HIGH level, and the TRST signal sig2 on the processor 1-2 side is set to LOW level. Become. At this time, the processor 1-2 is in a test logic reset state.
[0018]
When the TRST signal applied from the outside is at the LOW level, the TRST signal sig1 on the processor 1-1 side is set to the LOW level and the TRST signal sig2 on the processor 1-2 side is set to the HIGH level by the selector circuit 10. At this time, the processor 1-1 is in a test logic reset state.
[0019]
For debugging the processor 1-1, first, the externally applied TRST signal is set to the LOW level to reset the JTAG circuit 2-1 of the processor 1-1 (test logic reset). Next, the external TRST signal is set to the HIGH level, the test logic reset state of the JTAG circuit 2-1 of the processor 1-1 is released, and the processor 1-- is used using the JTAG test access ports (TCK, TMS, TDI, TDO). Debug 1 During debugging of the processor 1-1, the JTAG circuit 2-2 of the processor 1-2 does not operate in the test logic reset state.
[0020]
On the other hand, for debugging the processor 1-2, first, the external TRST signal is set to the LOW level, and the JTAG circuit 2-2 of the processor 1-2 is reset (test logic reset). Next, the external TRST signal is set to the HIGH level, the test logic reset state of the JTAG circuit 2-2 of the processor 1-2 is released, and the processor 1-- is used by using the JTAG test access port (TCK, TMS, TDI, TDO). Debug 1 During debugging of the processor 1-2, the JTAG circuit 2-1 of the processor 1-1 does not operate in the test logic reset state.
[0021]
In this way, by using the TRST terminal of the JTAG test access port as the select terminal, the processor to be debugged is selected from the processors 1-1 and 1-2 without adding an external terminal, thereby controlling the TAP controller. In addition, high-speed debugging of the processor can be easily performed without increasing the number of clocks required for data setting.
[0022]
As described above, according to the first embodiment, an external terminal is added in on-chip debugging using a debugging support circuit of a semiconductor integrated circuit incorporating two processors, that is, processors 1-1 and 1-2. In addition, it is possible to debug any one of the selected processors, thereby obtaining an effect of preventing an increase in the number of clocks and realizing high-speed on-chip debugging.
[0023]
Embodiment 2. FIG.
FIG. 2 is a block diagram of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 2, 1-1 and 1-2 are processors, 2-1 and 2-2 are JTAG circuits, and 20 is an inverter. . Here, the JTAG circuits 2-1 and 2-2 and the inverter 20 constitute a debugging support circuit.
[0024]
Next, the operation will be described.
In FIG. 2, when the TRST signal applied from the outside by the inverter 20 is HIGH level, the TRST signal sig1 on the processor 1-1 side is HIGH level, and the TRST signal sig2 on the processor 1-2 side is LOW level. . At this time, the processor 1-2 is in a test logic reset state.
[0025]
When the TRST signal applied from the outside is at the LOW level, the TRST signal sig1 on the processor 1-1 side is set to the LOW level and the TRST signal sig2 on the processor 1-2 side is set to the HIGH level by the inverter 20. At this time, the processor 1-1 is in a test logic reset state.
[0026]
In debugging the processor 1-1, first, the external TRST signal is set to the LOW level to reset the JTAG circuit 2-1 of the processor 1-1 (test logic reset). Next, the external TRST signal is set to the HIGH level, the test logic reset state of the JTAG circuit 2-1 of the processor 1-1 is released, and the processor 1-- is used using the JTAG test access ports (TCK, TMS, TDI, TDO). Debug 1 During debugging of the processor 1-1, the JTAG circuit 2-2 of the processor 1-2 does not operate in the test logic reset state.
[0027]
On the other hand, for debugging of the processor 1-2, first, the external TRST signal (output signal of the inverter 20) is set to the LOW level to reset the JTAG circuit 2-2 of the processor 1-2 (test logic reset). Next, the external TRST signal (output signal of the inverter 20) is set to HIGH level, the JTAG circuit 2-2 of the processor 1-2 is released from the test logic reset state, and the JTAG test access ports (TCK, TMS, TDI, The processor 1-2 is debugged using TDO). During debugging of the processor 1-2, the JTAG circuit 2-1 of the processor 1-1 does not operate in the test logic reset state.
[0028]
As described above, according to the second embodiment, by inserting the inverter 20 between the TRST terminal of the JTAG test access port and the processors 1-1 and 1-2, as in the first embodiment, There is an effect that high-speed on-chip debugging can be realized without increasing the number of clocks without adding an external terminal.
[0029]
Embodiment 3 FIG.
FIG. 3 is a block diagram of a semiconductor integrated circuit according to Embodiment 3 of the present invention, in which 1-1 to 1-N are processors (N is a natural number), and 2-1 to 2-N are JTAG circuits. , 30 is a first control circuit, 300 is a counter, 301 is a decoder with reset, 302 and 31-1 to 31 -N (N is a natural number) are AND gates, and 320 is an OR gate. The semiconductor integrated circuit according to the third embodiment is inserted between the processors 1-1 to 1-N, the JTAG test access port, the JTAG test access port, and the processors 1-1 to 1-N. It comprises a first control circuit 30 that receives a signal. Further, the first control circuit 30 includes a counter 300, a decoder 301, AND gates 302 and 31-1 to 31-N, and an OR gate 320.
[0030]
Next, the operation will be described.
In FIG. 3, the counter 300 counts the number of cycles of the TCK (clock) signal while the external TRST signal is at the LOW level. When the output of the counter 300 is input, the decoder 301 outputs the HIGH level only to the signal of the bit number corresponding to the output of the counter 300 when the TRST signal transits to the HIGH level, and outputs the LOW level to the other signals. . At this time, only the processor 1-n (1 ≦ n ≦ N, where N is a natural number) to which a HIGH level TRST signal is input cancels the JTAG test logic reset state. On the other hand, the other processors hold the test logic reset state.
[0031]
When debugging the processor 1-n, the external TRST signal is first set to the LOW level. At this time, all the output signals (sig1 to sigN) of the decoder 301 are at the LOW level, and all the processors 1-1 to 1-N are in the test logic reset state. Further, the TCK signal is applied for n cycles while the TRST signal is at the LOW level. The counter 300 counts the number of cycles of the applied TCK signal and outputs n to the decoder 301.
[0032]
Next, the external TRST signal is set to HIGH level. When the TRST signal becomes HIGH level, the decoder 301 outputs HIGH level only for the nth bit signal sign and outputs LOW level for the other signals.
[0033]
As a result, the HIGH level of the TRST terminal is propagated only to the processor 1-n, and the test logic reset state is released. As a result, only the processor 1-n can be controlled from the test access port and can be debugged. On the other hand, the TRST signal input to the other processors maintains the test logic reset state while remaining at the LOW level.
[0034]
As described above, by inserting the first control circuit 30 including the counter 300 and the decoder 301 instead of the selector circuit 10 described in the first embodiment, two or more processors 1-1 to 1- An arbitrary processor to be debugged can be easily selected from N.
[0035]
As described above, according to the third embodiment, one processor, for example, the n-th processor 1-n can be selected from a plurality of processors, that is, the processors 1-1 to 1-N. Similar to the first embodiment, an effect is achieved that high-speed on-chip debugging can be realized without increasing the number of clocks without increasing the number of external terminals.
[0036]
Embodiment 4 FIG.
4 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In the figure, 1-1 to 1-N are processors (N is a natural number), and 2-1 to 2-N are JTAG circuits. , 40 is a second control circuit, 400 is a control circuit, 401 is a counter, 402 is a decoder, 41-1 to 41-N and 430 are OR gates, 42-1 to 42-N are AND gates, 440 is AND gates 441 to 445 are registers. Here, the control circuit 400 includes AND gate 440 and registers 441 to 445 using the TMS signal as a shift-in input and the TCK signal as a clock input. Further, the second control circuit 40 includes the control circuit 400, the counter 401, The decoder 402 includes OR gates 41-1 to 41-N and 430 and AND gates 42-1 to 42-N.
[0037]
Next, the operation will be described.
In FIG. 4, when a high level signal is applied for five cycles or more from the external TMS signal, the control circuit 400 propagates a TCK signal (clock) to the counter 401 while the external TMS signal is high level. The counter 401 counts the number of cycles of the input TCK signal and inputs the output to the decoder 402. The decoder 402 outputs a HIGH level only to a signal having a bit number corresponding to the output of the counter 401, and the other signals output a LOW level.
[0038]
At this time, of the OR gates (41-1 to 41-N) that receive the output signal of the decoder 402, only the OR gate that receives the HIGH level signal is activated. The external TMS signal is propagated only to the processor connected to the activated OR gate. In other processors, the TMS signal is held at the HIGH level. As a result, the processor through which the external TMS signal propagates is released from the JTAG test logic reset state. Other processors remain in the test logic reset state.
[0039]
When debugging the n-th processor 1-n (1 ≦ n ≦ N, where n is a natural number), the TCK signal (clock) is applied for five cycles with the external TMS signal at the HIGH level. At this time, all the processors 1-1 to 1-N are placed in the test logic reset state.
[0040]
Next, the clock TCK signal is applied for n cycles while the TMS signal is held at the HIGH level. The counter 401 counts the number of cycles of the applied TCK signal and sets the output to the decoder 402 to n.
[0041]
The decoder 402 outputs a HIGH level only for the nth bit signal sign, and outputs a LOW level for the other signals. As a result, only the OR gate 41-n is activated, and the TMS signal is propagated to the processor 1-n. At the same time when the TMS signal transitions from the HIGH level to the LOW level (falling edge), the processor 1-n is released from the test logic reset state and can be controlled from the test access port, that is, can be debugged. On the other hand, the TMS signal input by the other processor remains at the HIGH level and maintains the test logic reset state.
[0042]
In this way, by using the TMS terminal instead of the TRST terminal in the third embodiment, one processor 1-n to be debugged is selected from the two or more processors 1-1 to 1-N. It becomes possible.
[0043]
As described above, according to the fourth embodiment, one processor 1-n can be selected from the plurality of processors 1-1 to 1-N. There is an effect that high-speed on-chip debugging can be easily realized without increasing the number of clocks without increasing the number of clocks.
[0044]
In the first to fourth embodiments, the description has been given by taking a plurality of processors as an example. However, the same applies to the case where a logic block is used instead. The same effect can be realized even if they are mixed.
[0045]
【The invention's effect】
As described above, according to the present invention, the selector circuit which is connected to the first and second internal circuits each including the JTAG circuit and forms the debugging support circuit together with the JTAG circuit, and the external terminal connected to the selector circuit are connected. A JTAG test access port as a select terminal of a selector circuit for selecting an internal circuit to be debugged when debugging the first and second internal circuits using the debug support circuit. Since the TRST terminal is used, the processor to be debugged can be selected without adding an external terminal, thereby increasing the number of clocks required for controlling the TAP controller and setting data. There is an effect that high-speed debugging of the circuit can be easily realized.
[0046]
According to the present invention, first and second internal circuits each having a JTAG circuit, a JTAG test access port connected to the first and second terminals and constituting an external terminal, the TRST terminal, and the first and second internal circuits And an inverter circuit provided between the first and second internal circuits, and the debug support circuit configured by the JTAG circuit and the inverter is configured to execute debugging of one of the first and second internal circuits. Therefore, similarly, it is possible to select the processor to be debugged without adding an external terminal, and easily realize high-speed debugging of internal circuits without increasing the number of clocks required for TAP controller control and data setting. There is an effect that can be done.
[0047]
According to the present invention, a plurality of internal circuits each including a JTAG circuit, a JTAG test access port connected to the JTAG test access port and constituting an external terminal, and a functional block including a counter connected to the TRST terminal and the TCK terminal are configured. A debugging support circuit configured by the JTAG circuit and the first control circuit inputs a TRST signal and a TCK signal via the TRST terminal and the TCK terminal, respectively, and a plurality of functional blocks Since any one of the internal circuits is debugged, similarly, a processor to be debugged can be selected without adding an external terminal, and a clock required for TAP controller control and data setting There is an effect that high-speed debugging of internal circuits can be easily realized without increasing the number.
[0048]
According to the present invention, a plurality of internal circuits each provided with a JTAG circuit, a JTAG test access port connected to this to constitute an external terminal, and a functional block including a counter connected to the TMS terminal and the TCK terminal are constituted. A debugging support circuit configured by the JTAG circuit and the second control circuit receives the TMS signal and the TCK signal via the TMS terminal and the TCK terminal, respectively, Since any one of the internal circuits is debugged, similarly, a processor to be debugged can be selected without adding an external terminal, and a clock required for TAP controller control and data setting There is an effect that high-speed debugging of the internal circuit can be easily realized without increasing the number.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 4 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
5 is a block diagram of a semiconductor integrated circuit according to Conventional Example 1. FIG.
6 is a block diagram of a semiconductor integrated circuit according to Conventional Example 2. FIG.
[Explanation of symbols]
1-1 to 1-N processor (internal circuit), 2-1 to 2-N JTAG circuit, 10, 60 selector circuit, 20 inverter, 30 first control circuit, 40 second control circuit, 31-1 to 31-N, 42-1 to 42-N, 302, 440 AND gate, 41-1 to 41-N, 320, 430 OR gate, 300, 401 counter, 301, 402 decoder, 320, 400 control circuit, 441 445 registers.

Claims (4)

  First and second internal circuits each having a JTAG circuit, a selector circuit connected to the first and second internal circuits and constituting a debugging support circuit together with the JTAG circuit, and connected to the selector circuit and externally connected In a semiconductor integrated circuit having a JTAG test access port constituting a terminal, the above-mentioned selection for selecting the internal circuit to be debugged when debugging the first and second internal circuits using the debug support circuit A semiconductor integrated circuit using the TRST terminal of the JTAG test access port as a select terminal of the selector circuit.   First and second internal circuits each having a JTAG circuit, a JTAG test access port connected to the first and second internal circuits and constituting an external terminal, the TRST terminal of the JTAG test access port, and the above In a semiconductor integrated circuit including an inverter circuit provided between any one of the first and second internal circuits, the first and second debug support circuits configured by the JTAG circuit and the inverter A semiconductor integrated circuit which executes debugging of any one of internal circuits. A plurality of internal circuits each including a JTAG circuit, a JTAG test access port connected to the plurality of internal circuits and constituting an external terminal, and a function including a counter connected to the TRST terminal and the TCK terminal of the JTAG test access port In a semiconductor integrated circuit including a first control circuit constituting a block, the debug support circuit configured by the JTAG circuit and the first control circuit includes a TRST signal and a TCK signal via the TRST terminal and the TCK terminal. , And any one of the plurality of internal circuits is debugged by the functional block. A plurality of internal circuits each including a JTAG circuit, a JTAG test access port connected to the plurality of internal circuits and constituting an external terminal, and a function including a counter connected to the TMS terminal and the TCK terminal of the JTAG test access port In a semiconductor integrated circuit including a second control circuit constituting a block, the debug support circuit configured by the JTAG circuit and the second control circuit includes a TMS signal and a TCK signal via the TMS terminal and the TCK terminal. , And any one of the plurality of internal circuits is debugged by the functional block.

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