CN101776728B - Boundary scanning method and device of device inside single plate - Google Patents

Abstract

The present invention provides a method and device for boundary scanning of devices in a single board, the method and device belong to the field of network communication, the single board includes a first programmable logic device PLD, a device to be detected and a first JTAG Jacket; wherein the The JTAG pins of the first JTAG Jacket and the device to be detected are respectively connected to the input and output pins Bank of the first programmable logic device; the working level of the Bank is the working level of the connected device, The method includes: connecting the device to be detected in series with the first JTAG Jacket through the first PLD; receiving a JTAG detection signal from the first JTAG Jacket, and performing boundary scan on the device to be detected in series. The invention has the advantages of simple connection relationship of detection devices in a single board, short transmission distance of detection signals, good signal quality, less BOM list and flexible chaining mode.

Description

Boundary scan method and device for devices in a single board

technical field

The invention relates to the communication field, in particular to a method and device for boundary scanning of devices in a single board.

Background technique

The currently designed digital hardware single board has a high density, more powerful functions, and a wide variety of devices on the board. This brings many difficulties and inconveniences to the production and maintenance of the veneer. In order to test the devices in the single board, the prior art provides a common detection method for the devices in the single board. The method uses boundary scan technology (Joint Test Action Group, JTAG) to detect the devices in the single board. JTAG initially It is used to test the chip. The basic principle of JTAG is to define a test access port (Test Access Port, TAP) inside the device to test the internal nodes through a dedicated JTAG test tool. The JTAG test allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which can test each device separately. Therefore, in JTAG technology, it is necessary to connect the JTAG pins of each device on the board in series to form a scan chain. Boundary scan is performed on the devices in the scan chain.

In the process of realizing the present invention, the inventor finds that the prior art has the following problems:

In the solution of the prior art, if there are many devices in the single board, the connection relationship between the JTAG pins of the devices will be complicated.

Contents of the invention

In order to simplify the connection relationship between JTAG pins, one aspect of the present invention provides a boundary scan method for devices in a single board, the single board includes a first programmable logic device PLD, a device to be detected and a first JTAG Jacket; wherein the JTAG pins of the first JTAG Jacket and the device to be detected are respectively connected to the input and output pins Bank of the first programmable logic device; the working level of the Bank is its connection device The working level, the method includes:

The device to be detected is connected in series with the first JTAG Jacket through the first PLD;

A JTAG detection signal is received from the first JTAG Jacket, and a boundary scan is performed on the serially connected devices to be detected.

Another aspect of the present invention provides a boundary scan device for devices in a single board, including: a first programmable logic device PLD, a device to be detected, and a first JTAG Jacket; wherein the first JTAGJacket and the device to be detected The JTAG pins of the device are respectively connected to the input and output pins Bank of the first programmable logic device; the working level of the Bank is the working level of the connected device.

As can be seen from the technical scheme provided above, the JTAG pin of the device to be detected in the technical scheme of the embodiment of the present invention is connected to the JTAG EPLD, because the Bank operating level of the JTAG EPLD can be adjusted to be connected to the work of the device on the Bank. Level, so no additional level conversion circuit is needed, which can simplify the connection relationship of the JTAG pins of the device to be detected, and then simplify the BOM list; and the detection signals are sent through the JTAG EPLD, the detection signal transmission distance is short, and the signal Good quality.

Description of drawings

FIG. 1 is a schematic flowchart of a boundary scan method for a device in a single board provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a device in a single board provided by another embodiment of the present invention;

FIG. 3 is a schematic flowchart of a boundary scan method for a device in a single board provided by an embodiment of the present invention;

4 is a schematic structural diagram of a device in a board after changing the device to be detected in a boundary scan method for devices in a board according to an embodiment of the present invention;

5 is a schematic structural diagram of a device in a board when Boot loading is implemented in a boundary scan method for devices in a board according to an embodiment of the present invention;

Detailed ways

Embodiments of the present invention provide a boundary scan method for devices in a single board, where the single board includes a first programmable logic device (Programmable Logic Device, PLD), such as an erasable programmable logic device (Erasable Programmable Logic Device, EPLD) , CPLD, Field Programmable Gate Array (Field Programmable Gate Array, FPGA), etc., for the convenience of description, the first PLD in the following description will be explained by taking JTAG EPLD as an example.

In this implementation, the single board includes a JTAG EPLD, a device to be detected and a first JTAG Jacket; wherein the JTAG pins of the device to be detected and the first JTAG Jacket are respectively connected to the input and output pin Bank of the JTAGEPLD; and The working level of the Bank is the working level of the device connected to the Bank, and the above-mentioned JTAG Jacket is a JTAG socket, which can be connected with the JTAG test equipment. In the flow diagram shown in Figure 1, the following steps are included:

S11, the device to be detected is connected in series with the first JTAG Jacket through the JTAG EPLD;

One or more (two or more) devices can be selected from the device to be detected, and connected in series with JTAG Jacket to form a JTAG scan chain. Among them, the chaining scheme can be realized by EPLD programming language, such as Verilog; under the control of the CPU, if the CPU configures the registers in the JTAG EPLD, different scan chains can be formed.

S12. Receive a JTAG detection signal from the first JTAG Jacket, and perform boundary scan on the serially connected devices to be detected.

The above-mentioned Bank can be a pair of pins in the JTAG EPLD, and the above-mentioned device to be detected can be an electronic device that needs to be detected in the single board, such as CPU, FPGA, etc.

Optionally, the above-mentioned single board can also include a second JTAG Jacket, which is connected to the JTAG pin of the JTAG EPLD, and online loading software for the JTAG EPLD by the second JTAG Jacket. The above-mentioned method of loading software online to JTAG EPLD is actually that the software loading device is connected to JTAG EPLD through the second JTAG Jacket, and the online loading software to JTAG EPLD is completed.

The above-mentioned software loading device may be a CPU or a JTAG debugging instrument or the like.

In the method provided by this embodiment, the JTAG pin of the device to be detected is connected to the JTAG EPLD, since the Bank operating level of the JTAG EPLD can be adjusted to the operating level of the device connected to the Bank, no additional level is required The conversion circuit can simplify the connection relationship of the JTAG pins of the device to be detected, thereby simplifying the BOM list; and the detection signals are all sent through the JTAG EPLD, the detection signal transmission distance is short, and the signal quality is good; further, the device to be detected The connection method can be realized by software, so there is no need to change the welding points of the devices, and the chaining method is more flexible.

The method provided by another embodiment of the present invention can be applied in the single board as shown in Figure 2, and the device in the single board can specifically include: JTAG EPLD 21 (the JTAG EPLD here has passed the second JTAG Jacket (in the figure) Not shown) completed the software loading), the first JTAG Jacket 22, DSP23, application specific integrated circuit 24 (Application Specific Integrated Circuit, ASIC), the first integrated circuit (Integrated Circuit, IC) device 25, CPU 26, PLD 27 , FPGA 28 and the second IC device 29; Wherein, DSP23, ASIC24, the first IC device 25, CPU26, PLD27, FPGA 28 and the second IC device 29 can be the device to be detected; Among the above-mentioned JTAG EPLD21 and the first JTAG Jacket22 1. The working level of the Bank connected to the first IC device, CPU26, PLD27 and FPGA28 is 3.3V; the working level of the Bank connected to the second IC device in JTAGEPLD21 is 2.5V; the Bank connected to DSP23 and ASIC24 in JTAG EPLD21 The working level is 1.8V; it should be noted that the above-mentioned first JTAGJacket 22, DSP23, ASIC24, first IC device 25, CPU 26, PLD 27, FPGA 28 and the second IC device 29 are connected to the pins of JTAG EPLD21 Both are JTAG pins.

In the schematic flow chart shown in Figure 3, the following steps are included:

S31, through the JTAG EPLD 21, the device to be detected in the single board is connected in series with the first JTAG Jacket 22;

The concrete method that realizes S31 can be, through JTAG EPLD 21, DSP23, ASIC24, first IC device, CPU 26, EPLD27, FPGA28, the second IC device 29 and first JTAG Jacket 22 are connected in order; The series connection may not be in the above order, and the series connection only needs to include all the devices to be detected. For the method for realizing the above series connection, refer to the relevant description in S11.

Optionally, in actual situations, the device to be detected can also be a single device, such as detecting the CPU alone. At this time, it is only necessary to connect the first JTAG Jacket and the CPU in series.

S32. The JTAG EPLD21 receives the detection signal from the first JTAG Jacket22, and sends the detection signal to the device to be detected in series order to complete the detection of the device to be detected.

The concrete steps of above-mentioned finishing S32 can comprise: the first JTAG Jacket22 sends detection signal to CPU26 by JTAG EPLD21, as CPU26 detection is normal, then this detection signal is delivered to PLD27 by JTAGEPLD21, as PLD27 detection is normal, then this detection signal passes through JTAG EPLD21 Pass to the first IC device, if the detection of the first IC device is normal, then the detection signal is passed to the next device through JTAG EPLD21 until all the devices are detected.

Optionally, after the detection of the device to be detected is completed, it is necessary to detect the changed device to be detected. Here, FPGA28 is used as an example to illustrate. After the device to be detected is changed to FPGA28, the internal device of the single board The structural diagram is shown in Figure 4, and in the flowchart shown in Figure 3, the method may also include:

S33, the first JTAG Jacket22 is connected in series with FPGA28 by JTAG EPLD21;

S34, the first JTAG Jacket22 sends the detection signal to the FPGA28 through the JTAG EPLD21 to complete the detection.

In addition, optionally, after S32, the above-mentioned method can also include controlling the PLD27 to complete the loading of the startup program Boot, and realize the device structure diagram in the single board loaded by the Boot as shown in Figure 5, and the loading process is as follows:

S35, connect PLD27 with CPU26 by JTAG EPLD21, and also connect PLD27 with the first JTAG Jacket22 by JTAG EPLD21;

After S36, JTAG EPLD21 receives the loading command of CPU26 and the loading command of the first JTAG Jacket22, select a control PLD27 from CPU26 and the first JTAG Jacket22 according to selection command and finish the loading to single board Boot.

Select first JTAG Jacket22 as above-mentioned selection command, then the method for finishing S36 can comprise: first JTAG Jacket22 sends loading order to JTAG EPLD21, and JTAG EPLD21 sends this loading order to PLD27 to control PLD27 to finish the loading to single board Boot.

Select CPU26 as above-mentioned selection command, then the method for finishing S36 specifically can comprise: CPU26 sends control command to JTAG EPLD21, and JTAG EPLD21 sends this loading command to PLD27 to control PLD27 to complete the loading of single board Boot.

The concrete realization mode that above-mentioned JTAG EPLD receives the load command of CPU and the load command of the first JTAG Jacket can be that JTAG EPLD receives the load command sent by CPU and the first JTAG Jacket respectively, also can be that JTAG EPLD receives the first load command forwarded by CPU. The load command of JTAG Jacket and its own load command sent by the CPU.

Further, before step S31, the method provided by this embodiment may also include loading software online for the JTAG EPLD through the JTAG pin of the JTAGEPLD.

For example, the JTAG pin of the JTAG EPLD is connected to the JTAG Jacket. After the JTAG EPLD is powered on or reset, the JTAG EPLD is controlled to load software online through the JTAG Jacket.

In the method provided by this embodiment, the JTAG pin of the device to be detected is connected to the JTAG EPLD, since the Bank operating level of the JTAG EPLD can be adjusted to the operating level of the device connected to the Bank, no additional level is required The conversion circuit can simplify the connection relationship of the JTAG pins of the device to be detected, thereby simplifying the BOM list; and the detection signals are all sent through the JTAG EPLD, the detection signal transmission distance is short, and the signal quality is good; further, the device to be detected The connection method can be realized by software, so there is no need to change the welding points of the devices, and the chaining method is more flexible.

The present invention also provides a device detection device in a single board, comprising: a first PLD, a device to be detected, and a first JTAG Jacket; wherein the first JTAG Jacket and the JTAG pins of the device to be detected are respectively connected to the first The input and output pin Bank of the PLD is on; and the working level of the Bank is the working level of the device connected to it.

Optionally, the above-mentioned device also includes:

A series connection unit, configured to connect the device to be detected and the first JTAGJacket in series through the first PLD.

For the specific implementation of the above series connection, refer to the relevant description in S11.

After the series connection is completed, the first JTAG Jacket completes the boundary scan of the device to be detected through the first PLD.

Optionally, there are at least two devices to be detected.

Optionally, the device to be detected includes: a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, and the second PLD is also connected to the first JTAG Jacket through the first PLD; the above-mentioned device also include:

The loading unit is used to select a control second PLD from the CPU and the first JTAG Jacket according to the selection command to complete the loading of the single board Boot after the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket.

Optionally, the above single board also includes: a second JTAG Jacket, the second JTAG Jacket is connected to the JTAG pin of the first PLD, and is used to load online software for the first PLD through the second JTAG Jacket.

For the specific implementation of online software loading, reference may be made to the relevant descriptions in the foregoing method embodiments.

In the device provided by this embodiment, the JTAG pins of all the devices to be detected are connected to the first PLD, because the Bank operating level of the first PLD can be adjusted to the operating level of the device connected to the Bank , so no additional level conversion circuit is needed, which can simplify the connection relationship of the JTAG pins of the device to be tested, and then simplify the BOM list; and the detection signals are all sent through the first PLD, the detection signal transmission distance is short, and the signal quality Good; furthermore, the connection method of the devices to be tested can be realized by software, so there is no need to change the soldering points of the devices, and the chaining method is more flexible.

Those skilled in the art can understand that the drawing is only a schematic diagram of a preferred embodiment, and the modules or processes in the drawing are not necessarily necessary for implementing the present invention.

Those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, One or a combination of steps of the method embodiments are included.

To sum up, the technical solution provided by the specific embodiment of the present invention has the advantages of simple connection relationship of detection devices in a single board, short detection signal transmission distance, good signal quality, less BOM list, and flexible chaining.

The embodiments of the present invention have been described in detail above, and specific examples have been used in this paper to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only used to help understand the method and core idea of the present invention; at the same time, for Those skilled in the art will have changes in the specific implementation and scope of application according to the idea of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (8)

1. the boundary scan method of device in a kind of single board, it is characterized in that, described single board comprises the first programmable logic device PLD, device to be detected and first boundary scan socket JTAG Jacket; Wherein said first JTAG Jacket and The JTAG pins of the device to be detected are respectively connected to the input and output pins Bank of the first programmable logic device; the working level of the Bank is the working level of the connected device, and the method includes: The device to be detected is connected in series with the first JTAG Jacket through the first PLD; Receive a JTAG detection signal from the first JTAG Jacket, and carry out boundary scan to the device to be detected in series; Wherein, the device to be detected includes a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, and the second PLD is also connected to the first JTAGJacket through the first PLD connected, the method further comprising: After the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket, select one of the CPU and the first JTAG Jacket according to the selection command to control the second PLD to complete the single Loading of the board startup program Boot. 2. The method according to claim 1, characterized in that there are at least two devices to be tested. 3. method according to claim 1, is characterized in that, described according to selection command, selects one to control described second PLD from described CPU and described first JTAG Jacket and completes the loading to single-board Boot comprising: The CPU sends a loading command to the second PLD through the first PLD, and controls the second PLD to complete the loading of the single-board Boot through the loading command; Or the first JTAG Jacket sends a load command to the second PLD through the first PLD, and controls the second PLD to complete the loading of the single board Boot through the load command. 4. The method according to any one of claims 1-2, wherein the single board further comprises: a second JTAG Jacket, the second JTAG Jacket is connected to the JTAG pin of the first PLD, the The method also includes: Online loading software for the first PLD through the second JTAG Jacket. 5. A boundary scan device for devices in a single board, comprising: a first programmable logic device PLD, a device to be detected and a first boundary scan socket JTAG Jacket; wherein said first JTAGJacket and said to be detected The JTAG pins of the device are respectively connected to the input and output pins Bank of the first programmable logic device; the working level of the Bank is the working level of the connected device; The device to be detected includes: a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, and the second PLD is also connected to the first JTAG Jacket through the first PLD, then The device also includes: The loading unit is used to select a control device from the CPU and the first JTAG Jacket according to the selection command after the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket The second PLD completes the loading of the single-board startup program Boot. 6. The device according to claim 5, further comprising: A series connection unit, configured to connect the device to be detected and the first JTAGJacket in series through the first PLD. 7. The device according to any one of claims 5 or 6, characterized in that there are at least two devices to be tested. 8. The device according to claim 5, wherein the device further comprises: a second JTAG Jacket, the second JTAG Jacket is connected to the JTAG pin of the first PLD, and through the second JTAG Jacket Load software online for the first PLD.

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