JP4396036B2 - Control device for voltage-driven semiconductor elements connected in series - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for controlling switching timing when a plurality of voltage-driven semiconductor elements connected in series are simultaneously turned on and off.
[0002]
[Prior art]
In a power conversion device including semiconductor switching elements connected in series, many problems and solutions are known in order to simultaneously turn on and off each switching element. In particular, the problem when voltage-driven semiconductor switching elements are connected in series will be described with reference to a circuit in which two elements are connected in series as shown in FIG.
[0003]
In FIG. 8, Q1 and Q2 are voltage-driven semiconductor elements, collector-emitter voltages at each stage are indicated by VCE1 and VCE2, respectively, and gate voltages are indicated by VGE1 and VGE2, respectively.
[0004]
When the elements Q1 and Q2 connected in series are switched, the delay times of the gate drive circuit and the elements are the same. If the switching timings are the same, the voltage sharing of the two elements becomes equal. However, in actuality, these delay times vary and change depending on the temperature, so that the switching timings of the elements are different.
[0005]
Therefore, as shown in FIG. 9, when the element Q1 is turned off faster than the element Q2, a high voltage is applied to the element Q1, and when the element Q1 is turned on later than the element Q2. If a high voltage is applied to the element Q2 and the switching timing difference is large, the element may be overvoltaged and destroyed.
[0006]
One conventional means for suppressing this voltage sharing imbalance is to connect a snubber circuit in parallel with the element. FIG. 10 shows a circuit configuration example to which this snubber circuit is applied. This circuit is for one phase of a two-level inverter, and an IGBT (insulated gate bipolar transistor) is connected in series as an element. Q1 to Q4 are IGBTs, and a circuit including a resistor R, a capacitor C, and a diode D connected in parallel to each other is a snubber circuit. GDU1 to GDU4 are gate drive circuits, and the power supply voltage is Ed. In this circuit, when the upper arm, that is, Q1 and Q2 are turned off and Q1 is turned off at a timing earlier than Q2, the operation waveform when there is no snubber circuit is shown in FIG. 11A, and the operation waveform when there is a snubber circuit. Is shown in FIG. As shown in this waveform, Q1 starts the turn-off operation first, and since Q2 is still in the on state during the period Δt from this start time, only the element voltage VCE (Q1) of Q1 rises and voltage imbalance occurs. Occurs. However, when the snubber circuit is connected, the voltage increase rate dv / dt of the element voltage can be reduced as compared to when the snubber circuit is not connected, and as a result, the voltage imbalance during the period of Δt can be reduced. it can. This dv / dt depends on the capacitance of C of the snubber circuit, and the voltage unbalance reduction effect can be increased as this is increased.
[0007]
[Problems to be solved by the invention]
Thus, by connecting a snubber circuit in parallel with the element and reducing the dv / dt of the element voltage, it becomes possible to reduce the element voltage unbalance due to the switching timing difference, but the circuit becomes larger and the loss increases. The problem occurs.
[0008]
Accordingly, an object of the present invention is to suppress variations in switching timing of elements connected in series with a simpler circuit.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, according to the present invention, when the gate lines of elements connected in series are magnetically coupled, and the current value flowing through each gate line differs when the element is turned on or off, the difference In response to this, the gate line impedance is instantaneously changed, so that the gate currents coincide with each other to suppress the variation in switching timing.
[0010]
More specifically, according to the present invention, a plurality of voltage-driven semiconductor elements connected in series to form an arm, and a gate signal to each gate terminal of the plurality of voltage-driven semiconductor elements in each arm. a gate drive circuit for supplying, in the semiconductor switching circuit consisting of,
To match the current flowing through the gate line of the current flowing through the gate line and the next stage of the voltage-driven semiconductor element of the voltage-driven semiconductor element of each stage, the first stage gate line next stage gate line The gate lines of each stage except the first stage and the final stage are magnetically coupled to the previous stage gate line and the next stage gate line, and the final stage gate line is magnetically coupled to the previous stage gate line. Item 1).
[0011]
According to the present invention, a plurality of voltage-driven semiconductor elements that are connected in series to form an arm, and a gate drive that supplies a gate signal to each gate terminal of the plurality of voltage-driven semiconductor elements in each arm. a circuit, the semiconductor switching circuit consisting of,
To match the current flowing through the gate line of the current flowing through the gate line and the next stage of the voltage-driven semiconductor element of the voltage-driven semiconductor element of each stage, the first stage gate line next stage gate line The gate lines of each stage except the first stage and the last stage are magnetically coupled to the previous stage gate line and the next stage gate line, and the last stage gate line is magnetically coupled to the previous stage gate line. The present invention is applicable to a voltage-driven semiconductor element (the invention according to claim 2).
[0012]
According to another solution of the present invention, in the semiconductor switch circuit according to claim 1 or 2, emitter lines connecting the gate drive circuit and an emitter terminal of the voltage-driven semiconductor element, or a gate line and an emitter. The same effect can be exhibited by magnetically coupling the wire (the invention according to claim 3).
[0013]
[Form of the present invention]
The present invention will be described by taking as an example a circuit configured by connecting two sets of IGBTs connected in series.
[0014]
FIG. 1 shows a circuit configuration example using the semiconductor switch circuit of the present invention, and this circuit is one phase of a two-level inverter as in FIG.
[0015]
The feature of this circuit is that the gate line for each arm is magnetically coupled. When magnetic coupling is performed, each gate line is wound around the same magnetic body MC as shown in FIG. Thereby, for example, when the gate current Ig1 flows, a magnetic flux of Φ1 is generated in the magnetic body, and this crosses the gate line of the GDU2. Similarly, when Ig2 flows, a magnetic flux of Φ2 is generated and crosses the gate line of GDU1. As a result, each gate line is magnetically coupled. At this time, the number of turns N1 and N2 of the gate line to the magnetic material is the same, and when Φ1 | Ig2, the relationship is | Φ1 | = | Φ2 |, and when Ig1 and Ig2 are opposite in polarity, Φ1 and Φ2 are opposite in polarity. To be. The circuit operation at this time will be described taking a turn-off operation as an example.
[0016]
When the turn-off timings of Q1 and Q2 are the same, the voltage waveforms VGE (Q1) and VGE (Q2) between the gates (G) and the emitters (E) are substantially equal. Since the IGBT GE can be equivalently regarded as a capacitor Cies as shown in FIG. 3, a discharge current of Cies transiently flows in the same waveform in Ig1 and Ig2 as shown in FIG. 4A. At this time, the magnetic materials Ig1 and Ig2 have opposite polarities, and Φ1 and Φ2 have the same level and opposite polarities, so that the magnetic flux generated in the magnetic material cancels each other out between Φ1 and Φ2. Therefore, magnetic coupling is not performed, and discharge current continues to flow from each Cies of Ig1 and Ig2.
[0017]
Next, as shown in FIG. 4B, when the turn-off timing of Q1 and Q2 becomes unbalanced (in this case, Q1 is turned off first), that is, when Ig1 flows out before Ig2, Φ1 ≠ Φ2 Therefore, a magnetic flux of | Φ1-Φ2 | is generated in the magnetic body and is magnetically coupled. At this time, inductances L1 and L2 are generated in the respective gate lines, and these have characteristics proportional to | Φ1-Φ2 |. That is, as the imbalance between Ig1 and Ig2 increases, L1 and L2 also increase. Moreover, since the impedance of the gate line increases as L1 and L2 increase, Ig1 and Ig2 do not flow easily. By this operation, as shown in FIG. 5, the impedance of the gate line is automatically changed according to the unbalance of Ig1 and Ig2, and the operation can be performed so that Ig1 and Ig2 coincide.
[0018]
By the above method, it is possible to suppress the variation in the turn-off timing between Q1 and Q2 without delay. This also works effectively for suppressing variations in turn-on timing.
[0019]
FIG. 6 shows an embodiment of the invention as set forth in claim 2 and shows a circuit configuration when n elements are connected in series. As is clear from the figure, the gate lines of Q1 and Q2 are magnetically coupled to match the gate current values, and the gate currents of Q3 and Q3 are magnetically matched to match the gate currents of Q3 with reference to these current values. By magnetically coupling the gate lines in a subordinate manner such as coupling, it becomes possible to instantaneously suppress the imbalance of the switching timing of all elements, and one magnetic body per two gate lines. Wiring can be simplified because only installation is required.
[0020]
In addition, as shown in FIG. 1, since the gate current flows through one route, the current values flowing in the gate line and the emitter line are the same. For this reason, even if the gate line and the emitter line or the emitter line and the emitter line are magnetically coupled as shown in FIG.
[0021]
【The invention's effect】
According to the present invention, when a large number of voltage-driven semiconductor elements are connected in series, the gate line is magnetically coupled for each arm, and the impedance of the gate line is instantaneously changed according to the amount of unbalance of the gate current, It is possible to suppress variations in switching timing without delay time with a very simple circuit.
[Brief description of the drawings]
FIG. 1 is a circuit connection diagram of an embodiment of the present invention.
FIG. 2 is a connection diagram for explaining the principle of the present invention.
FIG. 3 is a circuit diagram for explaining an equivalent circuit of an IGBT input unit;
FIG. 4 is an operation waveform diagram for explaining the operation of the gate waveform when the switching timing changes.
FIG. 5 is a circuit connection diagram showing an equivalent circuit of a gate line when the present invention is applied.
FIG. 6 is a circuit connection diagram showing another embodiment of the present invention when multiple elements are connected in series.
FIG. 7 is a circuit connection diagram of still another embodiment of the present invention.
FIG. 8 is a diagram illustrating a configuration of two series connection of elements.
FIG. 9 is an operation waveform diagram showing a voltage waveform when the switching timing varies.
FIG. 10 is a circuit connection diagram showing a conventional circuit configuration using a snubber circuit.
FIG. 11 is an operation waveform diagram showing a circuit voltage waveform according to a conventional element overvoltage suppressing method.

Claims (3)

A voltage-driven semiconductor element forming the arm is a plurality series, the gate drive circuit supplies a gate signal to the gate terminal of the plurality of each said voltage-driven semiconductor elements in each arm, the semiconductor switching circuit consisting of In
Controller of series-connected voltage-driven semiconductor element, wherein a gate line was magnetically coupled to each other for connecting the gate terminal of each of the voltage-driven semiconductor element of the gate driving circuit and said each arm. A voltage-driven semiconductor element forming the arm is a plurality series, the gate drive circuit supplies a gate signal to the gate terminal of the plurality of each said voltage-driven semiconductor elements in each arm, the semiconductor switching circuit consisting of In
To match the current flowing through the gate line of the current flowing through the gate line and the next stage of the voltage-driven semiconductor element of the voltage-driven semiconductor element of each stage, the first stage gate line next stage gate line A series connection characterized in that the gate lines of each stage except the first stage and the last stage are magnetically coupled to the previous stage gate line and the next stage gate line, and the last stage gate line is coupled to the previous stage gate line. Control device for a voltage-driven semiconductor element. The semiconductor switch circuit according to claim 1 or 2,
A control device for voltage-driven semiconductor elements connected in series, characterized in that the emitter lines connecting the gate drive circuit and the emitter terminal of the voltage-driven semiconductor element or the gate lines and the emitter lines are magnetically coupled. .

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