JP4393109B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a PMOS (P-Channel Metal Oxide Semiconductor) and an NMOS (N-Channel MOS).
[0002]
[Prior art]
A logical operation element made up of a combined circuit of PMOS and NMOS is usually called a CMOS (Complementary MOS) device.
[0003]
A conventional manufacturing process of a semiconductor device having a dual gate CMOS device will be described below.
[0004]
Conventionally, in a semiconductor device having a dual gate CMOS device, an LDD (Lightly Doped Drain) structure has been used from the viewpoint of suppressing deterioration of hot carrier lifetime. As a result of the improvement, a structure in which the concentration of the source / drain extension region, which has conventionally been an LDD structure, is adopted.
[0005]
Also, from the viewpoint of improving the short channel characteristics accompanying the miniaturization of the gate length, a step of forming source / drain extension regions through offset spacers formed on the side surfaces of the gate electrode is employed.
[0006]
[Patent Document 1]
JP-A-10-163339
[0007]
[Problems to be solved by the invention]
However, the above process has the following problems.
[0008]
In general, p + dopants (for example, boron) are more likely to thermally diffuse than n + dopants (for example, arsenic), and therefore, short channel characteristics tend to be more deteriorated in PMOS than in NMOS.
[0009]
When the short channel characteristic is deteriorated, the performance of the transistor becomes out of specification when the gate length is shortened due to variations in the manufacturing process, so that a semiconductor device having the required performance cannot be stably manufactured.
[0010]
By the way, in Japanese Patent Laid-Open No. 10-163339 (conventional example 1), the n + type high concentration impurity region in the NMOS region is formed by a thin junction to improve the current driving capability, and the p + type high concentration impurity region in the PMOS region is the channel. A method of manufacturing a semiconductor device is disclosed which is formed away from the semiconductor device so as to improve short channel characteristics.
[0011]
However, in the conventional example 1, as for the offset spacer at the time of ion implantation of the impurity region, only the case where the NMOS region and the PMOS region have the same thickness and the case where only the PMOS region has the offset spacer are shown. There is no disclosure about making the thickness of the offset spacer different between the NMOS region and the PMOS region during ion implantation of the impurity region.
[0012]
The present invention has been made in view of the above-described problems, and an object of the present invention is to make the current difference by making the thickness of the offset spacer different between the NMOS region and the PMOS region at the time of ion implantation of the impurity region. An object of the present invention is to provide a semiconductor device with improved driving force and short channel characteristics.
[0013]
[Means for Solving the Problems]
  A method of manufacturing a semiconductor device according to the present invention is as follows., NA step of preparing a semiconductor substrate having a MOS region and a PMOS region; a step of forming a first gate insulating film on the NMOS region; a second gate insulating film on the PMOS region; and a sidewall portion on the first gate insulating film Forming a first gate electrode having a sidewall and a second gate electrode having a sidewall on the second gate insulating film, and forming an oxide film covering the semiconductor substrate after forming the first gate electrode and the second gate electrode A step of forming a first nitride film covering the oxide film, a step of removing the first nitride film covering the NMOS region and exposing the oxide film covering the NMOS region after forming the first nitride film, (1) After removing the nitride film, leaving the oxide film formed on the sidewall of the first gate electrode, removing the oxide film on the NMOS region, exposing the semiconductor substrate in the NMOS region; Exposed semiconductor substrate After the step of implanting, the step of implanting the first n + dopant into the semiconductor substrate in the NMOS region, and the implantation of the first n + dopant, leaving the oxide film and the first nitride film formed on the side wall of the second gate electrode. After removing the oxide film and the first nitride film in the PMOS region, exposing the semiconductor substrate in the PMOS region, and exposing the semiconductor substrate in the PMOS region, a first p + dopant is implanted into the semiconductor substrate in the PMOS region. Forming a second nitride film on the sidewall of the oxide film formed on the sidewall of the first gate electrode after implanting the first p + dopant, and forming on the sidewall of the second gate electrode After the step of forming the third nitride film on the side wall portion of the first nitride film and the second nitride film and the third nitride film are formed, the first p + dopant is formed in the semiconductor substrate in the PMOS region. Too large After the second p + dopant is implanted at a high acceleration voltage, and the second nitride film and the third nitride film are formed, the second n + dopant is introduced into the semiconductor substrate in the NMOS region at a higher acceleration voltage than the first n + dopant. And injecting step.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor device according to the present invention will be described below.
[0015]
(Embodiment 1)
1 to 10 are cross-sectional views in each step of the manufacturing process of the semiconductor device according to the first embodiment. Here, in FIGS. 1 to 10, (a) shows the cross section of the NMOS region, and (b) shows the cross section of the PMOS region.
[0016]
The semiconductor device according to the present embodiment is a semiconductor device having a CMOS device, and as shown in FIG. 10, an NMOS having a sidewall spacer 12a as a first offset spacer and a second offset spacer as A PMOS having a sidewall spacer 12b is provided, and the width (W2) of the sidewall spacer 12b is formed to be about 5 nm to 10 nm larger than the width (W1) of the sidewall spacer 12a.
[0017]
The side wall spacer 12a includes an offset spacer 5a formed of an oxide film and an offset spacer 11 formed of a nitride film. On the other hand, the sidewall spacer 12b includes an offset spacer 9 including an oxide film 5 having an L-shaped cross-sectional shape and a nitride film 6 as a first nitride film, and an offset spacer 11 as a second nitride film. .
[0018]
The semiconductor device manufacturing method shown in FIG. 10 includes a step of forming an offset spacer 5a as a first offset spacer on the side wall of the gate electrode 3 of the NMOS, as shown in FIGS. 1 to 9, and the offset spacer 5a. An n + source / drain extension region 8 as an NMOS impurity region is formed by ion implantation, and an offset spacer 9 as a second offset spacer having a width larger than the offset spacer 5a on the side wall of the PMOS gate electrode 3 And forming a p + source / drain extension region 10 as an impurity region of the PMOS by using the offset spacer 9 by ion implantation.
[0019]
The offset spacer 5 a has a single layer structure made of the oxide film 5, and the offset spacer 9 has a laminated structure including the oxide film 5 and the nitride film 6.
[0020]
Hereinafter, the above manufacturing method will be described in more detail with reference to FIGS.
[0021]
As shown in FIG. 1, in the NMOS and PMOS regions included in the CMOS device, after forming the gate oxide film 2, the gate electrode 3, and the silicide film 4 on the silicon substrate 1, it has a thickness of about 10 nm to 30 nm. The oxide film 5 is formed by CVD (Chemical Vapor Deposition), and then the nitride film 6 having a thickness of about 5 nm to 10 nm is formed by CVD.
[0022]
From the state of FIG. 1, as shown in FIG. 2, a photoresist 7 is formed on the PMOS region by lithography, and then only the nitride film 6 in the NMOS region is selected by isotropic etching by RIE (Reactive Ion Etching). Etch away. At this time, the RIE conditions must be set such that the nitride film 6 has a high etching grade and the oxide film 5 has a low etching grade.
[0023]
From the state of FIG. 2, as shown in FIG. 3, the oxide film 5 in the NMOS region is etched by RIE anisotropic etching to leave the oxide film 5 only on the side surface of the gate electrode 3. The remaining oxide film 5 becomes an offset spacer 5a at the time of ion implantation of the n + source / drain extension region 8 in the NMOS region.
[0024]
From the state of FIG. 3, as shown in FIG. 4, the n + source / drain extension region 8 in the NMOS region is formed by ion implantation in the direction indicated by the arrow. Here, As, for example, As is used as the n + dopant. In this case, the ion implantation is about 2.0 keV to 4.0 keV and the ion concentration is 1.0 × 10.¹⁴cm^-21.0 × 10 or more¹⁵cm^-2The following conditions are used.
[0025]
Next, as shown in FIG. 5, the photoresist 7 on the PMOS region is removed and the photoresist 7 is formed on the NMOS region by lithography, and then the oxide film in the PMOS region is formed by anisotropic etching by RIE. 5 and nitride film 6 are etched to leave oxide film 5 and nitride film 6 only on the side surface of gate electrode 3. At this time, the RIE conditions need to be set so that the etching grades of the oxide film 5 and the nitride film 6 are substantially the same.
[0026]
As a result of the above etching process, the oxide film 5 on the silicon substrate 1 remains in the PMOS region without being etched by the thickness of the nitride film 6, so that an L shape is formed as shown in FIG. An oxide film 5 is formed. Further, the stacked structure of the oxide film 5 and the nitride film 6 remaining after the implementation of this step becomes the offset spacer 9 at the time of ion implantation of the p + source / drain extension region 10 in the PMOS region. The offset spacer 9 is thicker (wider) than the offset spacer 5a in the NMOS region by the layer thickness of the nitride film 6 remaining on the oxide film 5, so that the ion implantation of the p + source / drain extension region 10 is performed. In some cases, the offset amount between the source / drain can be ensured larger than that during the ion implantation of the n + source / drain extension region 8. Thereby, the short channel effect in PMOS can be suppressed.
[0027]
As shown in FIG. 6, the p + source / drain extension region 10 in the PMOS region is formed from the state of FIG. 5 by ion implantation in the direction indicated by the arrow. Here, for example, B (boron) is used as the p + dopant. In this case, the ion implantation is about 0.6 keV to 1.0 keV and the ion concentration is 1.0 × 10.¹⁴cm^-23.0 × 10 or more¹⁴cm^-2The following conditions are used.
[0028]
From the state of FIG. 6, as shown in FIG. 7, after removing the photoresist 7 in the NMOS region, a nitride film of about 30 nm to 50 nm is formed on the NMOS and PMOS regions by CVD, and anisotropic etching by RIE Thus, the nitride film is etched to leave the nitride film 11 only on the side surface of the gate electrode 3. As a result, a sidewall spacer 12a including the offset spacer 5a and the nitride film 11 is formed in the NMOS region, and a sidewall spacer 12b including the offset spacer 9 and the nitride film 11 is formed in the PMOS region.
[0029]
From the state of FIG. 7, as shown in FIG. 8, a photoresist 7 is formed on the NMOS region by lithography, and then a p + source / drain region 13 in the PMOS region is formed by ion implantation in the direction indicated by the arrow. Here, as the p + dopant, for example, B or BF₂Etc. are used. When the dopant is B, the ion implantation is about 2.0 keV to 4.0 keV and the ion concentration is 2.0 × 10.¹⁴cm^-25.0 × 10 or more¹⁵cm^-2The conditions are as follows, and the dopant is BF₂In the case of 15.0 keV or more and about 30.0 keV or less, the ion concentration is 2.0 × 10.¹⁴cm^-25.0 × 10 or more¹⁵cm^-2The following conditions are used.
[0030]
From the state of FIG. 8, as shown in FIG. 9, the photoresist 7 on the NMOS region is removed, and the photoresist 7 is formed on the PMOS region by lithography. An n + source / drain region 14 in the region is formed. Here, As, for example, As is used as the n + dopant. In this case, the ion implantation is about 30.0 keV or more and 60.0 keV or less, and the ion concentration is 2.0 × 10.¹⁵cm^-25.0 × 10 or more¹⁵cm^-2The following conditions are used. Thereafter, by removing the photoresist 7 on the PMOS region, a semiconductor device having a CMOS device as shown in FIG. 10 is formed.
[0031]
In the present embodiment, with the above configuration, the offset amount between the source / drain regions in the PMOS can be made larger than that in the NMOS, so that the short channel characteristics in the PMOS are improved while ensuring the driving characteristics in the NMOS. be able to.
[0032]
(Embodiment 2)
11 to 19 are cross-sectional views in each step of the manufacturing process of the semiconductor device according to the second embodiment. Here, FIGS. 11 to 19A show cross sections of the NMOS region, and FIGS. 11 to 19B show cross sections of the PMOS region.
[0033]
The semiconductor device according to the present embodiment is a semiconductor device having a CMOS device, and as shown in FIG. 19, an NMOS having a sidewall spacer 12a as a first offset spacer and a second offset spacer as And a PMOS having sidewall spacers 12b. Here, the widths (W1, W2) of the sidewall spacers 12a, 12b are formed to be substantially the same.
[0034]
The side wall spacers 12a and 12b are composed of offset spacers 5a and 5b formed of an oxide film and an offset spacer 11 formed of a nitride film.
[0035]
The semiconductor device manufacturing method shown in FIG. 19 uses a step of forming an offset spacer 5a as a first offset spacer on the side wall of the gate electrode 3 of the NMOS, as shown in FIGS. 11 to 18, and the offset spacer 5a. Forming an n + source / drain extension region 8 as an NMOS impurity region by ion implantation, forming offset spacers 5a and 5b as second offset spacers on the side wall of the PMOS gate electrode 3, and offset; Forming a p + source / drain extension region 10 as a PMOS impurity region by ion implantation using the spacers 5a and 5b.
[0036]
Here, the offset spacers 5a and 5b as the second offset spacers have a laminated structure of the oxide film 5, and have a larger thickness than the offset spacer 5a as the first offset spacer having a single layer structure of the oxide film 5. Have
[0037]
Hereinafter, the above manufacturing method will be described in more detail with reference to FIGS.
[0038]
As shown in FIG. 11, in the NMOS and PMOS regions included in the CMOS device, after forming the gate oxide film 2, the gate electrode 3 and the silicide film 4 on the silicon substrate 1, it has a thickness of about 10 nm to 30 nm. An oxide film 5 is formed by CVD.
[0039]
From the state of FIG. 11, as shown in FIG. 12, the oxide film 5 is etched by anisotropic etching by RIE (Reactive Ion Etching), and the oxide film 5 remains only on the side surface of the gate electrode 3. Show. The remaining oxide film 5 becomes an offset spacer 5a at the time of ion implantation of the n + source / drain extension region 8 in the NMOS region.
[0040]
From the state of FIG. 12, as shown in FIG. 13, a photoresist 7 is formed on the PMOS region by lithography, and then an n + source / drain extension region 8 in the NMOS region is formed by ion implantation in the direction indicated by the arrow. The process to perform is shown. Here, As, for example, As is used as the n + dopant. Further, ion implantation is performed under the same conditions as in the first embodiment.
[0041]
From the state of FIG. 13, as shown in FIG. 14, after removing the photoresist 7 on the PMOS region, an oxide film 5 having a thickness of about 5 nm to 10 nm is formed by CVD in the NMOS and PMOS regions, Thereafter, the oxide film 5 in the NMOS and PMOS regions is etched by anisotropic etching by RIE, so that the oxide film 5 b remains only on the side surface of the gate electrode 3.
[0042]
The stacked structure of the oxide films 5a and 5b remaining after the above etching process becomes offset spacers 5a and 5b at the time of ion implantation of the p + source / drain extension region 10 in the PMOS region. The offset spacers 5a and 5b are thicker (larger in width) than the offset spacer 5a in the NMOS region by the layer thickness of the offset spacer 5b. Therefore, when ion implantation is performed in the p + source / drain extension region 10, The offset amount between the drains can be ensured larger than that during the ion implantation of the n + source / drain extension region 8. Thereby, the short channel effect in PMOS can be suppressed.
[0043]
From the state of FIG. 14, as shown in FIG. 15, a photoresist 7 is formed on the NMOS region by lithography, and then a p + source / drain extension region 10 in the PMOS region is formed by ion implantation in the direction indicated by the arrow. To do. Here, for example, B (boron) is used as the p + dopant. Further, ion implantation is performed under the same conditions as in the first embodiment.
[0044]
After removing the photoresist 7 on the NMOS region from the state of FIG. 15, a nitride film of about 30 nm to 50 nm is formed on the NMOS and PMOS regions by CVD, and anisotropy by RIE is performed. The nitride film is etched by etching, and the nitride film 11 remains only on the side surface of the gate electrode 3. Thus, sidewall spacers 12a and 12b including offset spacers 5a and 5b and nitride film 11 are formed in the NMOS and PMOS regions, respectively.
[0045]
From the state of FIG. 16, as shown in FIG. 17, a photoresist 7 is formed on the NMOS region by lithography, and then a p + source / drain region 13 in the PMOS region is formed by ion implantation in the direction indicated by the arrow. Here, as the p + dopant, for example, B or BF₂Etc. are used. Further, ion implantation is performed under the same conditions as in the first embodiment.
[0046]
From the state of FIG. 17, as shown in FIG. 18, the photoresist 7 on the NMOS region is removed, and the photoresist 7 is formed on the PMOS region by lithography, and then the NMOS is implanted by ion implantation in the direction indicated by the arrow. An n + source / drain region 14 in the region is formed. Here, As, for example, As is used as the n + dopant. Further, ion implantation is performed under the same conditions as in the first embodiment. Thereafter, by removing the photoresist 7 on the PMOS region, a semiconductor device having a CMOS device as shown in FIG. 19 is formed.
[0047]
Also in the present embodiment, as in the first embodiment, the offset amount between the source / drain regions in the PMOS can be made larger than that in the NMOS, so that the short channel characteristics in the PMOS are ensured while ensuring the driving characteristics in the NMOS. Can be improved.
[0048]
Hereinafter, an example of the effect related to the improvement of the drive characteristics and the short channel characteristics in the semiconductor device according to the first and second embodiments will be described with reference to FIGS.
[0049]
20 and 21 are diagrams showing the driving characteristics of the semiconductor device with respect to the thickness (14 nm and 19 nm) of the offset spacer during impurity implantation. FIG. 20 shows the driving characteristics of the NMOS region, and FIG. 21 shows the PMOS region. The drive characteristics are shown.
[0050]
20 and 21, the horizontal axis (I_dsn, I_dsp) Is a current flowing between the source / drain regions in the ON state, and the vertical axis (I_off) Is a surface leakage current component flowing on the surface of the transistor in the OFF state. Where the same I_offAgainst I_dsn, I_dspIt can be said that a transistor having a larger is a transistor having excellent driving characteristics.
[0051]
As shown in FIG. 20, in the case of NMOS, when the thickness of the spacer is 5 nm (= 19-14 nm) small, it can be seen that the drive characteristics of the transistor are improved. On the other hand, for PMOS, as shown in FIG. 21, even if the spacer film thickness changes by 5 nm, the transistor drive characteristics do not change significantly.
[0052]
22 and 23 show the gate length L of the transistor._gAnd threshold voltage V_theIt is the figure which showed the relationship. Here, FIG. 22 shows the relationship in the NMOS, and FIG. 23 shows the relationship in the PMOS region. The thickness of the spacer is 14 nm for both NMOS and PMOS.
[0053]
Where the threshold voltage V_theWhen becomes extremely small, a short channel effect tends to occur. However, for NMOS, as shown in FIG._gEven if the threshold voltage V_theIs never extremely small. On the other hand, for the PMOS, as shown in FIG._gIs about 0.10 μm or less, the threshold voltage V_theTend to be extremely small.
[0054]
For the above reasons, the thickness of the offset spacer between the source / drain regions is preferably large in the PMOS region from the viewpoint of suppressing the short channel effect, and from the viewpoint of improving the driving characteristics, the PMOS region in the NMOS region is desirable. It is desirable to make it smaller. From the results of FIGS. 20 to 23, when the thickness of the offset spacer is about 5 nm smaller than the PMOS region in the NMOS region, the short channel effect in the PMOS is suppressed while improving the NMOS driving characteristics of the transistor. It can be said that it is possible. At this time, from the viewpoint of securing current drive characteristics in the PMOS, the difference in the thickness of the offset spacer between the NMOS and PMOS regions is preferably about the above value (10 nm) or less.
[0055]
Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0056]
【The invention's effect】
According to the present invention, the current driving capability and the short channel characteristic of the semiconductor device can be improved by making the thickness of the offset spacer different between the NMOS region and the PMOS region at the time of ion implantation of the impurity region.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views showing a first step of a manufacturing process of a semiconductor device according to a first embodiment of the present invention, where FIG. 1A shows a cross section of an NMOS region and FIG. 1B shows a cross section of a PMOS region; .
FIGS. 2A and 2B are cross-sectional views showing a second step of the manufacturing process of the semiconductor device according to the first embodiment of the invention, in which FIG. 2A shows a cross section of an NMOS region and FIG. 2B shows a cross section of a PMOS region; .
FIGS. 3A and 3B are cross-sectional views showing a third step of the manufacturing process of the semiconductor device according to the first embodiment of the invention, in which FIG. 3A shows a cross section of an NMOS region and FIG. 3B shows a cross section of a PMOS region; .
4 is a cross-sectional view showing a fourth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, where (a) shows a cross-section of an NMOS region and (b) shows a cross-section of a PMOS region. .
5A and 5B are cross-sectional views showing a fifth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, where FIG. 5A shows a cross section of an NMOS region, and FIG. 5B shows a cross section of a PMOS region. .
6 is a cross-sectional view showing a sixth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, wherein (a) shows a cross section of the NMOS region and (b) shows a cross section of the PMOS region. FIG. .
7 is a cross-sectional view showing a seventh step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
8 is a cross-sectional view showing an eighth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
9 is a cross-sectional view showing a ninth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, wherein (a) shows a cross section of the NMOS region and (b) shows a cross section of the PMOS region. .
10A and 10B are cross-sectional views of the semiconductor device according to the first embodiment of the present invention, where FIG. 10A shows a cross section of an NMOS region, and FIG. 10B shows a cross section of a PMOS region.
FIGS. 11A and 11B are cross-sectional views showing a first step of a manufacturing process of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 11A shows a cross section of an NMOS region, and FIG. 11B shows a cross section of a PMOS region; .
12 is a cross-sectional view showing a second step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
13 is a cross-sectional view showing a third step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
14A and 14B are cross-sectional views illustrating a fourth step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where FIG. 14A illustrates a cross-section of an NMOS region, and FIG. 14B illustrates a cross-section of a PMOS region. .
15 is a cross-sectional view showing a fifth step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, wherein (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
16 is a cross-sectional view showing a sixth step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
17 is a cross-sectional view showing a seventh step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
18 is a cross-sectional view showing an eighth step of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, where (a) shows a cross-section of the NMOS region and (b) shows a cross-section of the PMOS region. .
19A and 19B are cross-sectional views of a semiconductor device according to a second embodiment of the present invention, where FIG. 19A shows a cross section of an NMOS region, and FIG. 19B shows a cross section of a PMOS region.
FIG. 20 is a diagram showing the driving characteristics of the semiconductor device with respect to the thickness of the offset spacer at the time of impurity implantation in the NMOS region of the semiconductor device having a CMOS device.
FIG. 21 is a diagram showing a driving characteristic of a semiconductor device with respect to a thickness of an offset spacer at the time of impurity implantation in a PMOS region of a semiconductor device having a CMOS device.
FIG. 22 is a diagram showing a relationship between a gate length and a threshold voltage in an NMOS region of a semiconductor device having a CMOS device.
FIG. 23 is a diagram showing a relationship between a gate length and a threshold voltage in a PMOS region of a semiconductor device having a CMOS device.
[Explanation of symbols]
1 silicon substrate, 2 gate oxide film, 3 gate electrode, 4 silicide film, 5 oxide film, 5a, 5b, 9, 11 offset spacer, 6 nitride film, 7 photoresist, 8 n + source / drain extension region, 10 p + Source / drain extension regions, 12a and 12b, sidewall spacers, 13p + source / drain regions, 14n + source / drain regions.

Claims (2)

Providing a semiconductor substrate having an NMOS (N-Channel Metal Oxide Semiconductor) region and a PMOS (P-Channel Metal Oxide Semiconductor) region;
Forming a first gate insulating film on the NMOS region and a second gate insulating film on the PMOS region;
Forming a first gate electrode having a sidewall portion on the first gate insulating film and a second gate electrode having a sidewall portion on the second gate insulating film;
Forming an oxide film covering the semiconductor substrate after forming the first gate electrode and the second gate electrode;
Forming a first nitride film covering the oxide film;
After forming the first nitride film, removing the first nitride film covering the NMOS region and exposing the oxide film covering the NMOS region;
After the step of removing the first nitride film, the oxide film on the NMOS region is removed, leaving the oxide film formed on the sidewall of the first gate electrode, and the semiconductor substrate in the NMOS region Exposing the step,
After the step of exposing the semiconductor substrate in the NMOS region, implanting a first n + dopant into the semiconductor substrate in the NMOS region;
After implanting the first n + dopant, the oxide film and the first nitride film in the PMOS region are removed, leaving the oxide film and the first nitride film formed on the sidewall of the second gate electrode. Exposing the semiconductor substrate in the PMOS region;
After the step of exposing the semiconductor substrate in the PMOS region, implanting a first p + dopant into the semiconductor substrate in the PMOS region;
After implanting the first p + dopant, forming a second nitride film on the sidewall of the oxide film formed on the sidewall of the first gate electrode, and forming on the sidewall of the second gate electrode Performing a step of forming a third nitride film on the side wall of the first nitride film,
After forming the second nitride film and the third nitride film, injecting a second p + dopant into the semiconductor substrate in the PMOS region with an acceleration voltage larger than the first p + dopant;
And a step of injecting a second n + dopant with an acceleration voltage larger than that of the first n + dopant into the semiconductor substrate in the NMOS region after forming the second nitride film and the third nitride film. Device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein an ion concentration of the second n + dopant is higher than an ion concentration of the first n + dopant, and an ion concentration of the second p + dopant is higher than an ion concentration of the first p + dopant.

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