JP2008066548A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

The stacked source / drain structure and the booster technology described above can be made compatible with each other, whereby the device structure with improved carrier mobility can be miniaturized, thereby further enhancing the functionality. Provided are a semiconductor device that can be achieved and a method for manufacturing the same.
A gap is provided between a gate electrode 4a provided on a silicon substrate 1 via a gate insulating film 3, an insulating offset spacer 6 formed on a side wall of the gate electrode 4a, and the offset spacer 6. The compound semiconductor layer 11 formed by epitaxial growth in the digging pattern a provided on the surface side of the silicon substrate 11 in the maintained state, and the silicon substrate 1 and the compound insulated from the gate electrode 4a by the offset spacer 6 A semiconductor device Tr1 including a silicon layer 13 formed by epitaxial growth on the semiconductor layer 11.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a semiconductor device thereof, and more particularly, to provide a semiconductor device using a stacked source / drain structure and a booster technique in a semiconductor device having a MOS transistor structure and a manufacturing method thereof.

  In a semiconductor device having a MOSFET structure, a so-called elevated source drain structure in which a silicon layer serving as a source / drain is formed on a semiconductor substrate by epitaxial growth has been proposed. The stacked source / drain structure is said to be effective in suppressing the short channel effect because the diffusion depth (Xj) can be kept shallow and the increase in parasitic resistance can be suppressed (for example, the following patent document) 1 and Patent Document 2).

  On the other hand, in a semiconductor device having a MOSFET structure, a technique for improving carrier mobility by applying stress to a silicon substrate in a channel region is also actively used. As one of such technologies, as a source / drain (S / D) of a transistor, a silicon germanium (SiGe) layer or silicon carbide (SiC) having a lattice constant different from that of silicon (Si) is formed by epitaxial growth, and a channel region is formed. A so-called booster technique that applies stress to the surface has been proposed (see, for example, Non-Patent Document 1 below).

JP 2000-82813 A JP 2006-190821 A “IEDM2003 Technical Digest”, T. Ghani et al., “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors” (US), 2003, p. 987

  By the way, in order to achieve further higher functionality in a MOS transistor-structured semiconductor device, the element structure is miniaturized by suppressing the short channel effect using the stacked source / drain structure and the booster technology is applied. It is essential to increase the operating speed by improving the carrier mobility.

  In other words, even in an element structure in which carrier mobility is improved by applying booster technology, it is necessary to suppress the short channel effect by reducing the diffusion depth (Xj) to reduce the element structure. It happens.

  Therefore, the present invention makes it possible to achieve both the above-described stacked source / drain structure and booster technology, thereby enabling miniaturization of the element structure with improved carrier mobility, thereby further enhancing the function. An object of the present invention is to provide a semiconductor device capable of achieving the above and a manufacturing method thereof.

  In order to achieve such an object, a semiconductor device according to the present invention includes a gate electrode provided on a semiconductor substrate via a gate insulating film, an insulating sidewall formed on the side wall, and a surface of the semiconductor substrate. A first semiconductor layer formed by epitaxial growth in a digging pattern provided on the side, and a second semiconductor layer epitaxially grown on the first semiconductor layer are provided. In particular, the digging pattern and the first semiconductor layer are provided with a space between the digging pattern and the side wall. The first semiconductor layer has a lattice constant different from that of the semiconductor substrate. The second semiconductor layer is stacked on the semiconductor substrate and the first semiconductor layer in a state insulated from the gate electrode by the sidewall.

  The present invention is also a method of manufacturing a semiconductor device having such a configuration, and is characterized by performing the following procedure. First, in the first step, a gate electrode is formed on a semiconductor substrate through a gate insulating film, an insulating sidewall is formed on the sidewall of the gate electrode, and a dummy sidewall is formed through the sidewall. . In the next second step, the surface layer of the semiconductor substrate is dug down by etching using the gate electrode, sidewalls, and dummy sidewalls as a mask. Thereafter, in a third step, a first semiconductor layer having a lattice constant different from that of the semiconductor substrate is formed on the surface of the dug semiconductor substrate by epitaxial growth. Next, in the fourth step, the semiconductor substrate is exposed between the sidewall and the first semiconductor layer by selectively removing the dummy sidewall by etching. In the next fifth step, a second semiconductor layer is stacked and formed on the exposed surface of the semiconductor substrate and the surface of the first semiconductor layer by epitaxial growth.

  In the semiconductor device having the above configuration obtained by such a manufacturing method, the first semiconductor layer having a lattice constant different from that of the semiconductor substrate is formed in the digging pattern of the semiconductor substrate by epitaxial growth, so that the semiconductor substrate under the gate electrode A structure in which stress is applied to the portion (that is, the channel region) to increase carrier mobility can be employed.

  Further, the first semiconductor layer is disposed with a gap between the first sidewall of the gate electrode side wall, and on the semiconductor substrate exposed between the first semiconductor layer and the first sidewall, A second semiconductor layer is formed to be stacked. As a result, the stacked second semiconductor layer is disposed closest to the channel region under the gate electrode, and the source / drain junction depth is kept shallow by the second semiconductor layer. The short channel effect is suppressed.

  As described above, according to the present invention, the buried semiconductor layer improves carrier mobility by applying stress to the channel region, and the stacked semiconductor layer keeps the source / drain junction depth shallow to suppress the short channel effect. It becomes possible to do. As a result, it is possible to achieve further enhancement in functionality in the MOS type semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, a manufacturing method will be described first, and then a configuration of a semiconductor device obtained by the manufacturing method will be described.

<First Embodiment>
First, as shown in FIG. 1A, a silicon substrate 1 made of, for example, single crystal silicon is prepared as a semiconductor substrate, and an element isolation region 2 is formed on the surface side using a technique such as STI (Shallow Trench Isolation). Form. Thereby, the surface side of the silicon substrate 1 is separated into a plurality of active regions. Next, although illustration is omitted here, the surface of the silicon substrate 1 is covered with a protective film made of silicon oxide. Then, an impurity for forming a well diffusion layer is introduced into each active region by ion implantation from above the protective film, and further an impurity for adjusting a threshold value of a transistor formed in each active region is introduced. To do.

  Each ion implantation is performed individually in an active region for forming a p-type transistor and an active region for forming an n-type transistor using a resist pattern as a mask. Each ion implantation is performed in a state where channeling of implanted ions is prevented by the protective film. Then, after each ion implantation is completed, the protective film is removed.

  Next, a gate insulating film 3 made of silicon oxide is formed on the surface of the silicon substrate 1 with a thickness of about 1 nm. Next, the gate electrode film 4 made of polysilicon, amorphous silicon, amorphous silicon containing impurities, or the like is formed with a film thickness of about 100 nm to 200 nm by a CVD method. Further, the insulating film 5 made of silicon nitride is formed with a film thickness of about 30 to 100 nm by the CVD method.

  Thereafter, a resist pattern (not shown) is formed on the insulating film 5 by applying a lithography technique such as photolithography (KrF, ArF, F2) or electron beam lithography. Next, the insulating film 5 is patterned by dry etching using this resist pattern as a mask to form a hard mask 5a.

  Next, the resist pattern is removed, and the gate electrode layer 4 is patterned by dry etching from the hard mask 5a to form the gate electrode 4a. It is assumed that the line width of the gate electrode 4a is a minimum of several nm to several tens of nm.

  Next, as shown in FIG. 1B, sidewall-shaped offset spacers 6 are formed on the side walls of the gate electrode 4 a and the insulating film 5. The offset spacer 6 is made of an insulating material, for example, an insulating material such as a silicon nitride film, and is formed as a thin film having a thickness of 1 nm to 10 nm on the side walls of the gate electrode 4a and the hard mask 5a. .

  Next, as shown in FIG. 1 (3), dummy sidewalls 7 are formed further outside the offset spacers 6. The dummy sidewall 7 is formed of a material film that can be selectively removed with respect to the offset spacer 6, and is formed by, for example, etching back a silicon oxide film. Since the dummy sidewall 7 is finally removed by etching, the dummy sidewall 7 may be made of a conductive material as long as it can be selectively removed with respect to the offset spacer 6.

  Next, as shown in FIG. 1 (4), so-called recess etching is performed in which the exposed portion of the silicon substrate 1 is dug by etching using the dummy sidewall 7, the hard mask 5 a and the element isolation region 2 as a mask. Do. Thereby, the dug pattern a is formed on the surface side of the silicon substrate 1 on both sides of the gate electrode 4a.

  Next, as shown in FIG. 2A, a compound semiconductor layer 11 having a lattice constant different from that of the silicon substrate 1 is epitaxially grown on the exposed surface of the silicon substrate 1 as a first semiconductor layer in the dug pattern a. This compound semiconductor layer 11 constitutes a source / drain (S / D).

  At this time, when the semiconductor device formed here is an n-type transistor, a SiC layer is epitaxially grown as the compound semiconductor layer 11. The SiC layer is epitaxially grown while introducing n-type impurities such as arsenic (As) and phosphorus (P). On the other hand, when the semiconductor device formed here is a p-type transistor, a SiGe layer is epitaxially grown as the compound semiconductor layer 11. The SiGe layer is epitaxially grown while introducing a p-type impurity such as boron (B).

  In the formation of the compound semiconductor layer 11 by the epitaxial growth described above, an active region that does not require the compound semiconductor layer 11 is covered with a protective film. As such a protective film, a silicon oxide film constituting the dummy sidewall 7 can be used. In this case, in the formation of the dummy sidewalls 7, the silicon oxide film is left as it is as a protective film without being etched back in the active region where it is not necessary to form the compound semiconductor layer.

  Next, as shown in FIG. 2B, the dummy sidewall 7 made of silicon oxide is removed by wet etching. Thereby, the silicon substrate 1 under the offset spacer 6 and the dummy sidewall 7 made of silicon nitride is exposed.

  Next, as shown in FIG. 2 (3), a silicon layer 13 is stacked and formed as a second semiconductor layer on the exposed surfaces of the silicon substrate 1 and the compound semiconductor layer 11 by epitaxial growth. The stacked silicon layer 13 is formed with a film thickness of 5 nm to 30 nm. Further, it is formed so as to ride on the element isolation region 2. At this time, the protruding width of the stacked silicon layer 13 on the element isolation region 2 is desirably as small as possible, and is 20 nm or less at most.

Such a stacked silicon layer 13 contains impurities so as to form part of the source / drain together with the compound semiconductor layer 11. Impurities may be introduced into the stacked silicon layer 13 by forming the stacked silicon layer 13 by epitaxial growth and then introducing impurities by ion implantation, or by forming the stacked silicon layer 13 into which impurities have been introduced in advance by epitaxial growth. At this time, if the semiconductor device formed here is an n-type transistor, an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the stacked silicon layer 13, and the impurity The concentration is 1 × 10 ¹⁹ to 1 × 10 ²⁰ pieces / cm ³ . On the other hand, when the semiconductor device formed here is a p-type transistor, p-type impurities such as boron (B) and indium (In) are introduced into the stacked silicon layer 13, and the impurity concentration is The impurity concentration is 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ .

  Next, as shown in FIG. 2 (4), a second side wall 15 made of an insulating material is formed on the side wall of the gate electrode 4a via an offset spacer 6 made of silicon nitride. The sidewall 15 is formed, for example, by etching back a silicon oxide film. In this step, the gate electrode 4a made of polysilicon or amorphous silicon is exposed by performing etching for removing the insulating film 5 made of the silicon nitride film on the gate electrode 4a.

  Next, the resistance of a part of the gate electrode 4a and the stacked silicon layer 13 is lowered by ion implantation from the exposed surfaces of the gate electrode 4a and the stacked silicon layer 13. At this time, the side wall 15 serves as a mask, and the portion of the stacked silicon layer 13 close to the gate electrode 4a is left as a low concentration extension region 13a in which impurities are not introduced in a self-aligned manner. The portion into which the impurity is introduced becomes a high concentration source / drain region 13b.

  Thereafter, as shown in FIG. 3, a silicide layer 17 for reducing contact resistance is grown on the exposed surface of the gate electrode 4a and the exposed surface of the stacked silicon layer 13 by self-alignment. The subsequent steps are omitted here, but a general interlayer insulating film is formed, a contact to the MOS transistor is formed through the interlayer insulating film, and a metal wiring is formed on the interlayer insulating film. To complete the manufacturing process of the semiconductor device Tr1 having the MOS transistor configuration.

  The semiconductor device Tr1 obtained as described above is configured as follows.

  That is, the gate electrode 4a is provided on the silicon substrate 1 via the gate insulating film 3, and the offset spacer 6 is provided as an insulating side wall on these side walls. In addition, a compound semiconductor layer 11 formed by epitaxial growth is provided in the digging pattern a provided on the surface side of the silicon substrate 1 with a space between the offset spacers 6. Further, a stacked silicon layer 13 formed by epitaxial growth on the first semiconductor layer is provided on the silicon substrate 1 and the compound semiconductor layer 11 while being insulated from the gate electrode 4 a by the offset spacer 6.

  The stacked silicon layer 13 is stacked on the end of the element isolation region 2. On the other hand, a sidewall 15 made of an insulating material is provided on the sidewall of the gate electrode 4 a on the stacked silicon layer 13 via an offset spacer 6. The impurity concentration in the stacked silicon layer 13 is low in the lower portion of the sidewall 15, that is, in the portion close to the gate electrode 4a. That is, since this stacked silicon layer 13 constitutes a part of the source / drain together with the compound semiconductor layer 11, the portion adjacent to the gate electrode 4a as described above is an extension having a low impurity concentration. This is the layer 13a.

  A silicide layer 17 is provided on the surface of the second semiconductor layer exposed from the sidewall 15. Thereby, the contact resistance with respect to the stacked silicon layer 13 and the compound semiconductor layer 11 constituting the source / drain is reduced.

  In the semiconductor device Tr1 configured as described above, the compound semiconductor layer 11 is formed by epitaxial growth in the digging pattern a of the silicon substrate 1, whereby stress is applied to the channel region under the gate electrode 4a. Carrier mobility in is increased.

  Further, the compound semiconductor layer 11 is disposed with a gap between the offset spacer 6 on the side wall of the gate electrode 4a, and a stacked silicon layer 13 is formed on the silicon substrate 1 exposed in the gap portion. The extension 13a of the stacked silicon layer 13 formed so as to be stacked with respect to the channel region is disposed closest to the channel region. Therefore, the source / drain junction depth is kept shallow, and the short channel effect is suppressed.

  As a result, it is possible to achieve further enhancement in functionality in the MOS type semiconductor device Tr1.

  Furthermore, since the stacked silicon layer 13 is stacked on the end portion of the element isolation region 2, the end portion of the compound semiconductor layer 11 is formed by the stacked silicon layer 13 when the silicide layer 17 is formed on this surface. It can be well protected. That is, in the formation of the compound semiconductor layer 11, the sidewall may be formed in a tapered shape depending on the composition ratio (Si: GE or Si: C) of the compound constituting the compound semiconductor layer 11. In such a case, the film thickness of the compound semiconductor layer 11 is not sufficient at the boundary between the element isolation region 2 and the compound semiconductor layer 11. Therefore, the silicide layer 17 can be formed using the stacked silicon layer 13 as a protective film by covering the compound semiconductor layer 11 with the stacked silicon layer 13 and further overlapping the stacked silicon layer 13 with the element isolation region 2. It becomes possible. Thereby, it is possible to prevent the silicide layer 17 from reaching the silicon substrate 1 and causing junction leakage.

  Further, since the compound semiconductor layer 11 is covered with the stacked silicon layer 13 and the silicide layer 17 is grown on the surface, aggregation occurs in the formation of the silicide layer 17 unlike the silicidation of the compound semiconductor layer 11 surface. Never do. Therefore, it is possible to form a stable silicide layer 17.

Second Embodiment

  First, the same steps as described with reference to FIGS. 1 (1) to 2 (3) in the first embodiment are performed. As a result, as shown in FIG. 4A, a dug pattern a is formed on the surface side of the silicon substrate 1, and a compound semiconductor layer 11 having a lattice constant different from that of the silicon substrate 1 is exposed inside the silicon substrate 1. The process is performed by epitaxial growth on the surface and further the stacked silicon layer 13 is formed.

  Next, as shown in FIG. 4B, an insulating side wall (second side wall) 21 is formed on the side wall of the gate electrode 4a via an insulating offset spacer 6 made of silicon nitride. The sidewall 21 is formed by etching back a silicon oxide film, for example. At this time, the mask pattern 5a made of a silicon nitride film on the gate electrode 4a may be left as it is.

  Next, the resistance of a part of the stacked silicon layer 13 is reduced by ion implantation from the exposed surfaces of the gate electrode 4 a and the stacked silicon layer 13. At this time, the side wall 21 serves as a mask, and the portion of the stacked silicon layer 13 close to the gate electrode 4a is left as a low-concentration extension region 13a in which impurities are not introduced in a self-aligned manner, as in the first embodiment. is there.

  Next, the resistance of a part of the gate electrode 4a and the stacked silicon layer 13 is lowered by ion implantation from the exposed surfaces of the gate electrode 4a and the stacked silicon layer 13. At this time, the side wall 21 serves as a mask, and the portion of the stacked silicon layer 13 close to the gate electrode 4a is left as a low concentration extension region 13a in which impurities are not introduced in a self-aligned manner. The portion into which the impurity is introduced becomes a high concentration source / drain region 13b.

  Next, as shown in FIG. 4C, a silicide layer 23 for reducing contact resistance is grown on the exposed surface of the stacked silicon layer 13 by self-alignment.

  Thereafter, as shown in FIG. 4D, an interlayer insulating film 25 is formed in a state where the gate electrode 4a and the insulating film 5 are embedded. Then, the interlayer insulating film 25, the hard mask 5a, the offset spacer 6, and the sidewall 21 are polished by CMP until the gate electrode 4a is exposed.

  Next, as shown in FIG. 5A, the gate electrode 4a and the gate insulating film 3 are selectively etched away as a dummy pattern. Thereby, the groove pattern 27 is formed in the etched portion, and the silicon substrate 1 is exposed on the bottom surface. At this time, the dummy gate insulating film 3 made of silicon oxide is removed by wet etching using hydrofluoric acid while protecting the stacked silicon layer 13 using the offset spacer 6 made of silicon nitride as a mask.

  Thereafter, as shown in FIG. 5B, an insulating material film having a high dielectric constant (High-k) is formed as a new gate insulating film 29 in a state of covering the inner wall of the groove pattern 27.

  Next, as illustrated in FIG. 5C, a gate electrode film 31 is formed on the gate insulating film 29 in a state where the groove pattern 27 is embedded. The gate electrode film 31 is formed by laminating or forming a single layer structure of a metal or metal compound film.

  Thereafter, as shown in FIG. 5 (4), the gate electrode film 31 is subjected to CMP polishing so that the gate electrode film 31 remains only in the groove pattern 27, thereby forming a buried gate electrode 31a having a damascene structure. Furthermore, it is preferable to remove the excessive high dielectric constant (High-k) material on the interlayer insulating film 25 by CMP polishing the gate insulating film 29 made of a high dielectric constant (High-k) material.

  Thereafter, although illustration is omitted here, formation of a general interlayer insulating film, formation of a contact to the silicide layer 23 via the interlayer insulating film, and formation of metal wiring on the interlayer insulating film are further performed. This completes the manufacturing process of the semiconductor device Tr2.

  In the semiconductor device Tr2 obtained as described above, the gate electrode 31a can be a buried gate electrode and can be made of a metal material.

  Similarly to the semiconductor device (Tr1) obtained in the first embodiment, since the compound semiconductor layer 11 is formed by epitaxial growth in the digging pattern a of the silicon substrate 1, a channel region under the gate electrode 4a is formed. Is applied to the carrier region, and the carrier mobility in the channel region is increased. Further, the compound semiconductor layer 11 is disposed with a gap between the offset spacer 6 on the side wall of the gate electrode 4a, and a stacked silicon layer 13 is formed on the silicon substrate 1 exposed in the gap portion. The extension 13a of the stacked silicon layer 13 formed so as to be stacked with respect to the channel region is disposed closest to the channel region. Therefore, the source / drain junction depth is kept shallow, and the short channel effect is suppressed.

  As a result, as in the first embodiment, it is possible to achieve further enhancement in functionality in the MOS type semiconductor device Tr1.

  Furthermore, since the stacked silicon layer 13 is stacked on the end portion of the element isolation region 2 and the silicide layer 17 is formed on this surface, the silicide layer 17 is formed on the silicon substrate 1 as in the first embodiment. It is possible to prevent junction leakage from occurring and to form a stable silicide layer 17.

  Particularly in the second embodiment, when the buried gate electrode 31a is formed, as described with reference to FIG. 5A, in the hydrofluoric acid treatment for removing the dummy gate insulating film 3, an offset made of silicon nitride is used. Since the stacked silicon layer 13 is protected by the spacer 6, it is possible to prevent damage to the extension 13 a formed by the stacked silicon layer 13.

  In the second embodiment, the offset spacer 6 is made of an insulating material and remains. However, in the case where it is not necessary to consider the damage to the extension 13a, after the dummy gate electrode 4a and the gate insulating film 3 are removed in the process described with reference to FIG. The gate insulating film may be formed by removing the sidewall 21 and the stacked silicon layer 13 on the side wall of the groove pattern 27 and oxidizing the inner wall of the groove pattern 27. As a result, the charge accumulated during the operation of the transistor increases in the extension 13a formed by epi in contact with the gate insulating film, so that the driving capability of the transistor can be increased.

It is sectional process drawing (the 1) explaining the manufacturing method of 1st Embodiment. It is sectional process drawing (the 2) explaining the manufacturing method of 1st Embodiment. It is sectional process drawing (the 3) explaining the manufacturing method of 1st Embodiment. It is sectional process drawing (the 1) explaining the manufacturing method of 2nd Embodiment. It is sectional process drawing (the 2) explaining the manufacturing method of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Element isolation region, 3 ... Gate insulating film, 4a ... Gate electrode, 6 ... Dummy side wall, 7 ... Dummy side wall, 11 ... Compound semiconductor layer (1st semiconductor layer), 13 ... Stacked silicon layer (second semiconductor layer), S / D ... source / drain, 15, 21 ... sidewall (second sidewall), 17, 23 ... silicide layer, 25 ... interlayer insulating film, 29 ... new Gate insulating film, 31a ... new gate electrode, a ... digging pattern, Tr1, Tr2 ... semiconductor device

Claims (11)

A gate electrode provided on a semiconductor substrate via a gate insulating film;
An insulating sidewall formed on the sidewall of the gate electrode;
A first semiconductor layer having a lattice constant different from that of the semiconductor substrate formed by epitaxial growth in a digging pattern provided on the surface side of the semiconductor substrate with a space between the sidewall and the sidewall;
A semiconductor device, comprising: a second semiconductor layer formed by epitaxial growth on the semiconductor substrate and the first semiconductor layer in a state insulated from the gate electrode by the sidewall. In the semiconductor device according to claim 1,
The semiconductor device, wherein the second semiconductor layer comprises impurities and constitutes part of a source / drain. In the semiconductor device according to claim 1,
The second semiconductor layer is stacked on an end portion of an element isolation region provided on the surface side of the semiconductor substrate. In the semiconductor device according to claim 1,
A second sidewall made of an insulating material is provided on the sidewall of the gate electrode on the second semiconductor layer via the sidewall;
The semiconductor device, wherein the impurity concentration in the second semiconductor layer is low at a lower portion of the second sidewall. In the semiconductor device according to claim 1,
A second sidewall made of an insulating material is provided on the sidewall of the gate electrode on the second semiconductor layer via the sidewall;
A semiconductor device, wherein a silicide layer is provided on a surface of the second semiconductor layer exposed from the second sidewall. The semiconductor device according to claim 5.
The second semiconductor layer is made of a silicon layer. Forming a gate electrode on a semiconductor substrate through a gate insulating film, forming an insulating sidewall on the side wall of the gate electrode, and further forming a dummy sidewall through the sidewall;
A second step of digging the surface layer of the semiconductor substrate by etching using the gate electrode, sidewalls, and dummy sidewalls as a mask, and a surface having a lattice constant different from that of the semiconductor substrate, A third step of forming one semiconductor layer by epitaxial growth;
A fourth step of exposing the semiconductor substrate between the sidewall and the first semiconductor layer by selectively etching away the dummy sidewall;
A method of manufacturing a semiconductor device, comprising: performing a fifth step of stacking and forming a second semiconductor layer by epitaxial growth on the exposed surface of the semiconductor substrate and the surface of the first semiconductor layer. The method of manufacturing a semiconductor device according to claim 7.
After the fifth step,
Forming a second sidewall made of an insulating material on the sidewall of the gate electrode through the sidewall;
And a step of introducing an impurity into the second semiconductor layer using the gate electrode, the sidewall, and the second sidewall as a mask. The method of manufacturing a semiconductor device according to claim 7.
After the fifth step,
Forming a second sidewall made of an insulating material on the sidewall of the gate electrode through the sidewall;
A method of manufacturing a semiconductor device, comprising performing a step of growing a silicide layer on an exposed surface of the second semiconductor layer. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, comprising forming a silicon layer as the second semiconductor layer. The method of manufacturing a semiconductor device according to claim 7.
After the fifth step,
Forming a second sidewall made of an insulating material on the sidewall of the gate electrode through the sidewall;
The interlayer insulating film is formed so as to cover the sidewall and the second sidewall, and the gate electrode is exposed from the interlayer insulating film, and then the gate electrode and the gate insulating film are removed. Exposing the semiconductor substrate;
And a step of embedding and forming a new gate electrode in the exposed surface of the semiconductor substrate through a new gate insulating film.

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