JP4345445B2 - Image processing apparatus, image display apparatus, and calculation parameter setting method in image processing apparatus - Google Patents

Description

  The present invention relates to an image processing apparatus including a plurality of data processing units that perform calculation processing based on calculation parameters held in a register, an image display apparatus, and a calculation parameter setting method in the image processing apparatus.

  Among various image display devices, for example, in the SXGA system having a display area of 1280 dots × 1024 dots, the video transfer frequency rises to about 130 MHz. For this reason, in an image processing device used for an image display device, a large number of image data is allocated to, for example, a first data processing unit and a second data processing unit so that the large number of image data can be processed in real time. In each data processing unit, operations are performed in parallel. Here, since the first data processing unit and the second data processing unit each perform the same arithmetic processing, IC chips having the same specifications are used.

  However, the calculation parameters for the first image data performed by the first data processing unit and the calculation for the second image data performed by the second data processing apparatus do not always coincide completely. Therefore, normally, the first register is configured in the data processing unit, while the second register is configured in the second data processing unit, and as shown in FIG. 7, the chip select for the first register is performed. An operation of setting data (calculation parameters) supplied in time series from a common data bus to a predetermined address of the first register based on the signal CS1 and the chip select signal CS2 for the second register; A method is employed in which the operation of setting a predetermined address of the second register is performed at different timings.

  However, in the method of setting the calculation parameters supplied in time series from the common data bus to the first register and the second register by shifting the timing, it takes a long time to set the calculation parameters. When starting to display an image, there is a problem that it is necessary to wait for a long time until the image starts to be displayed. In addition, calculation parameters may be set when the type of image to be displayed (input source, etc.) or display form (left / right upside down, etc.) is switched. This causes a problem that an unnatural image is displayed such as the image being temporarily stopped.

  In view of the above problems, an image processing apparatus that includes a plurality of data processing units that perform arithmetic processing based on arithmetic parameters held in a register, and in which an arithmetic parameter can be set in a short time A processing device, an image display device, and a calculation parameter setting method in the image processing device are provided.

  In order to solve the above-described problem, in the present invention, a first operation is performed in which a plurality of calculation processes are performed on the assigned first image data based on a plurality of parameters for each calculation held in the first register. And a calculation process performed by the first data processing unit on the assigned second image data based on a plurality of calculation parameters for each calculation held in the second register, An image processing apparatus comprising: a second data processing unit that performs the same arithmetic processing; and a control unit that sets the arithmetic parameters in the first register and the second register via a common data bus. The control unit includes the first register and the second register for the same calculation parameter in the first data processing unit and the second data processing unit among the calculation parameters. Setting is performed at the same timing, and calculation parameters that are different between the first data processing unit and the second data processing unit are set at different timings in the first register and the second register. It is characterized by.

  Further, in the present invention, a first data processing unit that performs a plurality of arithmetic processes on the assigned first image data based on a plurality of parameters for each calculation held in the first register; The same arithmetic processing as the arithmetic processing performed in the first data processing unit is performed on the assigned second image data based on a plurality of arithmetic parameters for each arithmetic operation held in the second register. A calculation parameter setting method in an image processing apparatus including a second data processing unit, wherein the calculation parameter is set when the calculation parameter is set in the first register and the second register from a common data bus. Of the parameters, the same operation parameters in the first data processing unit and the second data processing unit are the same in the first register and the second register. The calculation parameters that are different between the first data processing unit and the second data processing unit are set at different timings in the first register and the second register. And

  In the present invention, when setting the operation parameter to the first register and the second register from the common data bus, the same operation parameter is used for the first data processing unit and the second data processing unit. Setting is performed at the same timing in the register and the second register, and only the operation parameters that are different between the first data processing unit and the second data processing unit are set at different timings in the first register and the second register. I do. Therefore, calculation parameters can be set in a short time, so that when an image display is started, the image starts to be displayed in a short time. Further, when the type of image to be displayed is switched, an unnatural image such as an image being temporarily stopped is not displayed regardless of the moving image.

  In the present invention, the first data processing unit and the second data processing unit are respectively configured as a first IC chip and a second IC chip having the same specifications, and the control unit When setting operation parameters for the register and the second register at the same timing, the chip select signal for the first IC chip and the chip select signal for the second IC chip are simultaneously turned on, When setting operation parameters for one register and the second register at different timings, the chip select signal for the first IC chip and the chip select signal for the second IC chip are shifted on-level by shifting the timing. To.

  In the present invention, for example, the first image data and the second image data supply image signals to odd-numbered data lines and even-numbered data lines in a common image light forming device, respectively. Image data.

  In the present invention, the first data processing unit and the second data processing unit include at least gamma correction, vertical streak correction, ghost correction, lateral crosstalk correction, and color unevenness correction as the plurality of arithmetic processes. And the first register and the second register include a register that holds a calculation parameter for each correction, and the control unit includes the first calculation parameter among the correction calculation parameters. For the operation parameter to be corrected with the same operation parameter in the data processing unit and the second data processing unit, the first register and the second register are set at the same timing, and the first The calculation parameters that are different between the data processing unit and the second data processing unit are different in the first register and the second register. The settings in the ring.

  In the present invention, the first data processing unit and the second data processing unit include at least gamma correction, vertical streak correction, ghost correction, lateral crosstalk correction, and color unevenness correction as the plurality of arithmetic processes. And the first register and the second register are provided with registers for storing calculation parameters for each correction, and the control unit includes gamma correction and correction calculation parameters among the correction calculation parameters. The calculation parameters used for color unevenness correction are set at the same timing in the first register and the second register, and the calculation parameters used for vertical streak correction, ghost correction, and horizontal crosstalk correction are described above. Settings are made at different timings for the first register and the second register.

  In the present invention, the control unit sets operation parameters to the first data processing unit and the second data processing unit, for example, at the start of image display in the image light forming apparatus, This is performed at at least one of the timing when the type of image displayed on the light forming apparatus is switched and the mode of the image displayed on the image light forming apparatus is switched.

  In the present invention, the image light forming apparatus is, for example, a liquid crystal panel in which liquid crystal is held between a pair of substrates arranged to face each other.

  An image processing apparatus to which the present invention is applied is used in an image display apparatus such as a projection display apparatus.

  Embodiments of the present invention will be described with reference to the drawings.

(Configuration of image display device)
FIG. 1 is a block diagram showing the overall configuration of an image display apparatus to which the present invention is applied.

  As shown in FIG. 1, the image display device 10 is roughly composed of an image processing device 100 and a liquid crystal panel 200 as an image light forming device. In the present invention, the image light forming device is a device that modulates light from a light source by an input image signal, such as a liquid crystal panel or a dynamic mirror device, or the intensity of light emitted by an input image signal. Indicates a device that can be changed, such as an EL or plasma display. The liquid crystal panel 200 includes a thin film transistor array substrate 1 made of, for example, a quartz substrate or hard glass, and a liquid crystal as an electro-optical material is held between the thin film transistor array substrate 1 and a counter substrate (not shown). The On the thin film transistor array substrate 1, a plurality of pixel portions are provided in a matrix. In such a pixel array, a plurality of data lines 35 arranged in the X direction and extending in the Y direction, and a data line 35 extending in the Y direction are provided. A plurality of scanning lines 31 are formed, each extending in the X direction. Each pixel portion is provided corresponding to the intersection of each data line 35 and each scanning line 31. A TFT (thin film transistor) 30 connected to the data line 35 and the scanning line 31, and a pixel electrode 11 connected to the TFT 30. And a storage capacity 12. Here, the data line 35 constitutes a data line group for every 12 adjacent lines, and an image signal is simultaneously supplied to each data line 35 with such a data line group as a unit.

  In the liquid crystal panel 200 configured as described above, the TFT 30 is connected between the data line 35 and the pixel electrode 11, and applies the image signal supplied to the data line 35 to the pixel electrode 11 and the storage capacitor 12 during the conduction period. . At this time, the conducting state and non-conducting state of the TFT 30 are controlled according to the scanning signal supplied via the scanning line 31 to which the gate electrode is connected. On the thin film transistor array substrate 1, a capacitor line 31 ′ (storage capacitor electrode) is formed in parallel to the scanning line 31 as a wiring for the storage capacitor 12 that holds the voltage applied to the pixel electrode 11 for a long time. Thus, the storage capacitor 12 is formed between the pixel electrode 11 and the capacitor line 31 '.

  A liquid crystal driving circuit 202 is formed on the thin film transistor array substrate 1. The liquid crystal driving circuit 202 includes a sampling circuit 210 that samples an image signal and supplies it to the plurality of data lines 35, a data line driving circuit 220, and a scanning line driving circuit 230. The sampling circuit 210 is a circuit for supplying twelve image signals V1 to V12 converted into a parallel format to each data line 35 at a predetermined timing. The sampling circuit 210 includes a sampling TFT 211 constituting an analog switch for each data line 35. Image signals V1 to V12 are input to the source electrode of the TFT 211 via image signal supply lines L1 to L12, a sampling signal line 216 is connected to the gate electrode, and a data line 35 is connected to the drain electrode. . The data line driving circuit 220 includes a shift register. The shift register has a predetermined pulse width and a predetermined width based on the X shift clock and the X shift start pulse and the control signal included in the power supply voltage and the clock signal. Timing sampling signals S 1, S 2,... Sn are generated and sequentially output to the sampling signal line 216 of the sampling circuit 210. Note that the shift register of the data line driving circuit 220 may be configured as a bidirectional shift register. Similarly to the data line driving circuit 220, the scanning line driving circuit 230 also has a shift register, and shifts based on the power supply voltage, the Y shift clock and Y shift start pulse included in the clock signal, and the control signal. A scanning signal having a predetermined pulse width and a predetermined timing is generated by the register, and is supplied to the scanning lines 31 in a line sequential manner. Note that the shift register of the scanning line driver circuit 220 may also be configured as a bidirectional shift register. Note that the liquid crystal driving circuit 202 is not necessarily formed on the thin film transistor array substrate 1 and may be connected to the thin film transistor array substrate 1 in the form of an IC chip or the like.

  In such a configuration, when the sampling signals S1, S2,... Sn are supplied from the data line driving circuit 220 to the sampling circuit 210 via the sampling signal line 216, the sampling circuit 210 simultaneously samples the image signals V1 to V12. Then, the image signals V1 to V12 are simultaneously applied to 12 adjacent data lines 35 constituting each data line group. This is sequentially performed for each of the sampling signals S1, S2,... Sn, and the image signals V1 to V12 are sequentially sampled for each data line group within the horizontal scanning period.

(Configuration of image processing apparatus)
When used in a projection display device (image display device) described later with reference to FIG. 6, the image display device 10 shown in FIG. 1 emits red (R), green (G), and blue (B) color lights. In order to modulate, three lines are used.

  Therefore, the image processing apparatus 100 in the three systems of image display apparatuses 10 is configured as shown in FIG. FIG. 2 is a block diagram showing the configuration of the image processing apparatus in the image display apparatus to which the present invention is applied. FIG. 3 is a block diagram showing a correction circuit for red (R) image data extracted from the correction circuit configured in the image processing apparatus shown in FIG. FIGS. 4A and 4B are explanatory diagrams showing timings when the same calculation parameters are written to the registers in the first correction circuit and the second correction circuit in the image processing apparatus shown in FIG. It is explanatory drawing which shows the timing at the time of writing the operation parameter which is different in 1 correction circuit and 2nd correction circuit to a register | resistor.

  In FIG. 2, the image processing apparatus 100 to which the present invention is applied performs parallel processing such as enlargement and reduction on input image data, and then converts the image data into odd dots for each color in synchronization with the divided clock. The corresponding first image data RD1, GD1, BD1 and the second image data RD2, GD2, BD2 corresponding to even dots are configured to be distributed to the two IC chips 101, 102. In the chips 101 and 102, correction processing (calculation processing) described below is performed. The image data subjected to the correction processing by the IC chips 101 and 102 is developed into six phases by the six-phase development circuit 191 and then converted into an analog signal by the D / A converter 193, and an amplifier. After being amplified in 195, it is output to the three liquid crystal panels (red light liquid crystal panel 200R, green light liquid crystal panel 200G, and blue light liquid crystal panel 200B) described with reference to FIG. Here, the liquid crystal panels 200R, 200G, and 200B adopt the SXGA system having a display area of 1280 dots × 1024 dots, and the video transfer frequency is approximately 130 MHz.

  In the present embodiment, of the two IC chips 101 and 102, the first IC chip 101 (first data processing unit) has a register 116 and an odd dot of red (R) together with the built-in timing generation circuit 110. Three first correction circuits for corresponding first image data RD1, first image data GD1 corresponding to odd dots of green (G), and first image data BD1 corresponding to odd dots of blue (B) 121R, 121G, and 121B are configured, and each of these three correction circuits 121R, 121G, and 121B includes a gamma correction circuit 131 that includes registers 136, 146, 156, 166, and 176, and a vertical stripe correction circuit. 141, a ghost correction circuit 151, a lateral crosstalk correction circuit 161, and a color unevenness correction circuit 171 are configured.

  The second IC chip 102 (second data processing unit) also has a register 127 and a built-in timing generation circuit 120, as well as second image data RD2, green (G) corresponding to red (R) even dots. ), The first image correction circuit 122R, 122G, 122B corresponding to the second image data GD2 corresponding to the even dots and the second image data BD2 corresponding to the even dots of blue (B) are configured. Each of the three correction circuits 122R, 122G, and 122B includes a gamma correction circuit 132, a vertical line correction circuit 142, a ghost correction circuit 152, and a horizontal crosstalk correction circuit each having a register 137, 147, 157, 167, and 177. 162, an uneven color correction circuit 172 is configured.

  The configuration and operation of the gamma correction circuits 131 and 132, vertical stripe correction circuits 141 and 142, ghost correction circuits 151 and 152, horizontal crosstalk correction circuits 161 and 162, and color unevenness correction circuits 171 and 172 are basically the same. The first correction circuit corresponding to odd dots of red (R) is shown in FIG. 3 among red (R), green (G), and blue (B). The second correction circuit 122R and the like corresponding to 121R and red (R) even dots are extracted and illustrated, and the correction circuits 121R and 122R will be mainly described.

  In FIG. 3, the calculation for correction in the first correction circuit 121R and the second correction circuit 122R is held in each register 136, 146, 156, 166, 176, 137, 147, 157, 167, 177. These calculation parameters are obtained by reading data read from the memory 189 by the CPU 188 (control unit) that operates based on a program stored in advance or obtained by calculation. Set by writing to a register. Therefore, the CPU 188 and the registers 116, 136, 146, 156, 166, and 176 are connected by the first chip select signal line 181, the write command signal line 183, the A / D synchronization line 184, and the common data bus 185. Has been. The CPU 188 and the registers 127, 137, 147, 157, 167, and 177 are connected by a second chip select signal line 182, a write command signal line 183, an A / D synchronization line 184, and a common data bus 185. ing.

  In the image processing apparatus 100 configured as described above, in this embodiment, gamma correction circuits 131 and 132, vertical stripe correction circuits 141 and 142, ghost correction circuits 151 and 152, horizontal crosstalk correction circuits 161 and 162, and color unevenness correction circuit. The calculation parameter setting method is switched depending on whether or not the calculation parameters 171 and 172 match between the first correction circuit 101R and the second correction circuit 102R.

  First, the gamma correction circuits 131 and 132 are circuits for correcting the TV characteristics indicated by the relationship between the applied voltage and the transmittance in the liquid crystal panel, unlike the CRT, because they are not linear. That is, the liquid crystal panel 200 has a small change in transmittance with respect to a change in applied voltage in the vicinity of a black level with a low gradation value. As a result, the change in gradation (light transmittance) is small and the resolution in this area is lowered. Therefore, this is corrected to correct the resolution in all areas. Due to the nature that such correction is performed regardless of the dot position of the image, the calculation parameters are the first correction circuit 121R corresponding to odd dots and the second correction circuit 122R corresponding to even dots. The calculation parameters match.

  On the other hand, the vertical streak correction circuits 141 and 142 have different calculation parameters in the first correction circuit 121R corresponding to odd dots and the second correction circuit 122R corresponding to even dots for the following reason. Yes. In this embodiment, a data line group is constituted by twelve adjacent data lines 35, and the image signals V1 to V12 are simultaneously applied to these twelve adjacent data lines 35. All these image signals V1 to V12 are applied. Even when the same level gradation display is performed, the twelfth data line controlled by a certain sampling signal Sn and the first data line controlled by an adjacent sampling signal Sn + 1 interfere with each other due to parasitic capacitance coupling. Since the brightness changes in this portion, vertical stripes occur every 12 columns. Such vertical streaks can be eliminated by correcting the data at the position where the vertical streaks occur by calculation. The vertical streak correction circuits 141 and 142 perform such correction. For this reason, the vertical streak correction circuits 141 and 142 have different calculation parameters between the first correction circuit 121R corresponding to odd dots and the second correction circuit 122R corresponding to even dots.

  Next, the ghost correction circuits 151 and 152 are circuits that correct the occurrence of a ghost at a position shifted by 12 dots. The first correction circuit 121R corresponding to odd dots and the second corresponding to even dots. The calculation parameters are different in the correction circuit 122R.

  Next, the horizontal crosstalk correction circuits 161 and 171 cancel the crosstalk generated in the horizontal direction with a predetermined attenuation coefficient when, for example, black is displayed, and the first correction circuit corresponding to odd dots. The calculation parameters are different between 121R and the second correction circuit 122R corresponding to even dots.

  Next, the uneven color correction circuits 171 and 172 are caused by uneven brightness in the liquid crystal panels 200R, 200G, and 200B for each color, and are usually corrected by complementation between two points separated by several tens of dots. The operation parameters of the first correction circuit 121R corresponding to odd dots and the second correction circuit 122R corresponding to even dots are the same.

  In response to such coincidence or inconsistency of computation parameters, in this embodiment, first, under the control signal output from the CPU 188, computation is performed as in the gamma correction circuits 131 and 132 and the uneven color correction circuits 171 and 172. When the parameters match between the first correction circuit 121R and the second correction circuit 122R, the CPU 188 sets the first chip selector signal CS1 as shown in FIG. And the second chip selector signal CS2 are turned on at the same timing. As a result, common operation parameters are used for the register 136 of the gamma correction circuit 131 configured in the first correction circuit 121R and the register 137 of the gamma correction circuit 132 configured in the second correction circuit 122R. Are set at the same time. Further, a common calculation is performed for the register 176 of the color unevenness correction circuit 171 configured in the first correction circuit 121R and the register 177 of the color unevenness correction circuit 172 configured in the second correction circuit 122R. Parameters are set simultaneously.

  On the other hand, when the calculation parameters are different between the first correction circuit 121R and the second correction circuit 122R, when setting the calculation parameters, the control unit 188, as shown in FIG. The timing at which the first chip selector signal CS1 is turned on is shifted from the timing at which the second chip selector signal CS2 is turned on. Therefore, after the operation parameters are set in the register 146 of the vertical streak correction circuit 141 configured in the first correction circuit 121R, the calculation parameter is stored in the register 147 of the vertical streak correction circuit 142 configured in the second correction circuit 122R. Calculation parameters are set. Further, after the operation parameter is set in the register 156 of the ghost correction circuit 151 configured in the first correction circuit 121R, the operation parameter is stored in the register 157 of the ghost correction circuit 152 configured in the second correction circuit 122R. Is set. Further, after the operation parameters are set in the register 166 of the lateral stroke correction circuit 161 configured in the first correction circuit 121R, the calculation parameter is stored in the register 167 of the lateral stroke correction circuit 162 configured in the second correction circuit 122R. Calculation parameters are set.

  The setting operation in the correction circuits 121R and 122R corresponding to red (R) has been described above, but the setting operation in the correction circuits 121G, 121B, 122G and 122B corresponding to green (G) and blue (B) is the same. The description thereof will be omitted.

  Whether or not the calculation parameters match between the first correction circuit 101R and the second correction circuit 102R is determined in advance by the calculation function (register address) as described above, and the CPU 188 determines the calculation parameters. The determination may be made by comparing each time, or information indicating the attribute of the calculation parameter may be stored in the memory 189 in association with the calculation parameter.

  Further, when the image data is driven while being reversed left and right, the odd-numbered dot and the even-numbered dot are switched, so that the CPU 188 writes information to that effect in the registers 116 and 127 of the timing signal generation circuits 110 and 120. The chip select signals CS1 and CS2 shown in FIGS. 4A and 4B can be replaced and written.

(Effect of this embodiment)
As described above, in this embodiment, the registers 136, 146, 156, 166, and 176 of the first correction circuit 121R corresponding to odd dots, and the registers 137 and 147 of the second correction circuit 122R corresponding to even dots. When the operation parameters are set in the first correction circuit 121R and the second correction circuit 122R when setting the operation parameters in 157, 167, and 177, the operation parameters are set in the registers 136 and 176 and the registers. 137 and 177 are performed at the same timing, and only when the operation parameters are different between the first correction circuit 121R and the second correction circuit 122R, the operation parameters are set in the registers 146, 156 and 166 and the registers 147, 157 and 167. Shift the timing with. Accordingly, since the time required for setting the calculation parameter can be shortened, the time required until the image starts to be displayed can be shortened when the image display is started.

  Even if calculation parameters are set when the type of image to be displayed or the display format is changed, the time required for setting the calculation parameters is short, so the image that should be a movie is temporarily stopped. It is possible to eliminate unnaturalness such as doing.

(Configuration of electronic equipment)
An example of an electronic apparatus using the image display device 10 described above will be described. FIG. 5 is a block diagram showing a configuration of the electronic device. As shown in this figure, the electronic device includes a display information output source 1000, a display information processing circuit 1002, a display drive circuit 1004, a display panel 1006, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 is configured to include a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs a television signal, and outputs display information such as a video signal based on the clock from the clock generation circuit 1008. To do. The display information processing circuit 1002 processes display information based on the clock from the clock generation circuit and outputs it. The display information processing circuit 1002 includes the image processing apparatus 100 described above, and also includes an amplification / polarity inversion circuit, a phase expansion drive circuit, a rotation circuit, a clamp circuit, and the like. The display driving circuit 1004 includes a scanning line driving circuit and a data line driving circuit, and corresponds to the liquid crystal driving circuit 202 described above, and drives the display panel 1006 such as the liquid crystal panel 200 described above. The power supply circuit 1010 supplies power to each of the circuits described above.

(Projector configuration)
Next, a projector (projection display device) using the image display device 10 will be described with reference to FIG.

  As shown in FIG. 6, a projector 2100 includes a lamp unit 2102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2102 is separated into three primary colors of RGB by three mirrors 2106 and two dichroic mirrors 2108 arranged inside, and liquid crystal as a light valve corresponding to each primary color. They are led to panels 200R, 200G and 200B, respectively.

  Here, the configurations of the liquid crystal panels 200R, 200G, and 200B are the same as those of the liquid crystal panel 200 described above, and are driven by R, G, and B primary color signals supplied from the image processing apparatus 100, respectively. In addition, B light has a long optical path compared to other R colors and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

  In the projector 2100 configured as described above, the lights modulated by the liquid crystal panels 200R, 200G, and 200B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam goes straight. Therefore, as a result of the synthesis of the primary color images, a color image is projected onto the screen 2120 via the projection lens 2114.

1 is a block diagram illustrating an overall configuration of an image display device to which the present invention is applied. It is a block diagram which shows the structure of the image processing apparatus with respect to the image display apparatus to which this invention is applied. FIG. 3 is a block diagram showing a correction circuit for red (R) image data extracted from the correction circuit configured in the image processing apparatus shown in FIG. 2. FIGS. 2A and 2B are explanatory diagrams showing timings when the same calculation parameter is written to the shift register in the first correction circuit and the second correction circuit in the image processing apparatus shown in FIG. It is explanatory drawing which shows the timing at the time of writing in the shift register the calculation parameter which is different in the correction circuit and the second correction circuit. It is a block diagram which shows the structure of the electronic device using the image display apparatus to which this invention is applied. It is a top view which shows the structure of the projector using the image display apparatus to which this invention is applied. It is explanatory drawing which shows the timing at the time of writing a calculation parameter in a shift register in the conventional image processing apparatus.

Explanation of symbols

10 image display devices, 31 scanning lines, 35 data lines, 100 image processing devices, 101, 102 IC chips, 110, 120 timing generation circuits, 116, 136, 146, 156, 166, 176, 127, 137, 147, 157 167, 177 registers, 121R, 121G, 121B first correction circuit, 122R, 122G, 122B second correction circuit, 131, 132 gamma correction circuit, 141, 142 vertical stripe correction circuit, 151, 152 ghost correction circuit, 161, 162 Horizontal crosstalk correction circuit, 171, 172 Color unevenness correction circuit, 188 CPU (control unit), 189 Memory, 191 6-phase expansion circuit, 193 D / A converter, 195 amplifier, 200 Liquid crystal panel, 210 Sampling circuit 220 Data line driving circuit, 2 0 scan line driver circuit

Claims (9)

A first data processing unit that performs a plurality of arithmetic processes on the assigned first image data based on a plurality of parameters for each computation held in the first register, and an assigned second image data A second data processing unit that performs the same arithmetic processing as the arithmetic processing performed in the first data processing unit on the image data based on a plurality of arithmetic parameters for each arithmetic operation held in the second register And an image processing apparatus having a control unit for setting the operation parameter in the first register and the second register via a common data bus,
The control unit has the same timing in the first register and the second register for the same calculation parameter in the first data processing unit and the second data processing unit among the calculation parameters. The calculation parameters are set, and the operation parameters that are different between the first data processing unit and the second data processing unit are set at different timings in the first register and the second register. Image processing device. In Claim 1, said 1st data processing part and said 2nd data processing part are respectively constituted by the 1st IC chip and the 2nd IC chip of the same specification,
The control unit sets a chip select signal for the first IC chip and a chip select for the second IC chip when setting operation parameters for the first register and the second register at the same timing. When the signals are simultaneously turned on and the operation parameters for the first register and the second register are set at different timings, the chip select signal for the first IC chip and the chip for the second IC chip An image processing apparatus, wherein a select signal is shifted to an on level by shifting timing.   3. The first image data and the second image data according to claim 1, wherein the first image data and the second image data respectively supply image signals to odd-numbered data lines and even-numbered data lines in a common image light forming apparatus. An image processing apparatus characterized in that the image data is image data. 4. The first data processing unit and the second data processing unit according to claim 3, wherein at least gamma correction, vertical streak correction, ghost correction, horizontal crosstalk correction, and color unevenness are used as the plurality of arithmetic processes. While performing one of the corrections, the first register and the second register include a register that holds an operation parameter for each correction,
The control unit includes the first register and the first calculation parameter that are corrected by using the same calculation parameter in the first data processing unit and the second data processing unit among the correction calculation parameters. The two registers are set at the same timing, and the calculation parameters that differ between the first data processing unit and the second data processing unit are different at the first register and the second register. An image processing apparatus that performs setting. 4. The first data processing unit and the second data processing unit according to claim 3, wherein at least gamma correction, vertical streak correction, ghost correction, horizontal crosstalk correction, and color unevenness are used as the plurality of arithmetic processes. While performing one of the corrections, the first register and the second register include a register that holds an operation parameter for each correction,
The control unit sets the calculation parameters used for gamma correction and color unevenness correction among the calculation parameters of the correction by setting the first register and the second register at the same timing, An image processing apparatus, wherein calculation parameters used for ghost correction and lateral crosstalk correction are set at different timings in the first register and the second register.   6. The control unit according to claim 3, wherein the control unit sets an operation parameter to the first data processing unit and the second data processing unit, and starts displaying an image on the image light forming apparatus. At least one of the timing when the type of image displayed on the image light forming apparatus is switched and the mode of the image displayed on the image light forming apparatus is switched. An image processing apparatus.   7. The image processing apparatus according to claim 3, wherein the image light forming apparatus is a liquid crystal panel in which liquid crystal is held between a pair of substrates arranged to face each other.   An image display device comprising the image processing device defined in any one of claims 1 to 7. A first data processing unit that performs a plurality of arithmetic processes on the assigned first image data based on a plurality of parameters for each computation held in the first register, and an assigned second image data A second data processing unit that performs the same arithmetic processing as the arithmetic processing performed in the first data processing unit on the image data based on a plurality of arithmetic parameters for each arithmetic operation held in the second register A calculation parameter setting method in an image processing apparatus comprising:
When setting the operation parameter to the first register and the second register from a common data bus,
Among the calculation parameters, the same calculation parameters in the first data processing unit and the second data processing unit are set at the same timing in the first register and the second register, and The calculation parameter in the image processing apparatus is characterized in that calculation parameters that differ between the first data processing unit and the second data processing unit are set at different timings in the first register and the second register. How to set parameters.

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