JP4304779B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a power device and BiCMOS are formed on the same semiconductor substrate, and can be applied to, for example, a composite IC used in an automobile controller.
[0002]
[Prior art]
Conventionally, there is a vertical DMOS (hereinafter referred to as VDMOS) as a discrete power MOSFET used for driving a load on an automobile. In the field of so-called composite ICs in which a bipolar transistor and a CMOS are integrated on a single chip. From the viewpoint of easy integration, an up drain type power MOSFET in which the drain on the bottom surface of the VDMOS substrate is brought to the substrate surface, or an LDMOS in which drains and sources are alternately arranged are often used. FIG. 23 shows a longitudinal sectional view when an up-drain MOSFET is used as a power device, and FIG. 24 shows a longitudinal sectional view when an LDMOSFET is similarly used as a power device. FIG. 25 is a longitudinal sectional view of an NPN transistor constituting BiCMOS when a power device and BiCMOS are formed as a composite IC, and FIG. 26 is a longitudinal sectional view of a case where a PNP transistor is similarly used to constitute BiCMOS. The figure is shown.
[0003]
However, in order to form a power device having a breakdown voltage and an on-resistance necessary for a composite IC, a channel p-well region 200 (see FIGS. 23 and 24) and an n-well region 210 for up-drain MOSFETs (see FIG. 23) not in the CMOS process. For example, it is necessary to form a well region dedicated to a power device, such as an LDMOSFET well region 220 (see FIG. 24). Further, in order to form a bipolar transistor, dedicated processes such as a base region 230 and an emitter region 240 (see FIGS. 25 and 26) are required, which causes a problem that the number of processes is large and the manufacturing cost is high.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the cost with a novel configuration.
[0005]
[Means for Solving the Problems]
According to the invention described in claim 1, in the double well CMOS, n and p Well region is used and this n and p The well region is a power device formation region and NPN, PNP It is also formed in each bipolar transistor formation region. In addition, the n-well region of the double well CMOS is also formed between the source cells where the p-well region of the power device is formed, between the collector of the NPN bipolar transistor and between the collector and emitter of the PNP bipolar transistor. A power device and a bipolar transistor are formed in this well region.
[0006]
Therefore, the power device and the bipolar transistor can be formed on the semiconductor substrate without using the dedicated mask for the power device and the dedicated mask for the bipolar transistor. As a result, the cost can be reduced in the semiconductor device in which the power device and the BiCMOS are formed on the same semiconductor substrate.
[0007]
According to invention of Claim 5, it has arrange | positioned on the semiconductor substrate. p-well Using the mask, the power device, the NPN / PNP bipolar transistor, and the double well CMOS are formed simultaneously. p A well region is formed. Furthermore, placed on the semiconductor substrate n-well Using the mask, each formation region of the power device, NPN, PNP bipolar transistor and double well CMOS In addition, And the p-well region of the power device is formed. Ru Between source cells, the collector of an NPN bipolar transistor, and between the collector and emitter of a PNP bipolar transistor, at the same time An n-well region of a double well CMOS is formed. Thereafter, a gate electrode is simultaneously disposed in the formation region of the power device and the double well CMOS.
[0008]
As described above, the power device and the bipolar transistor can be formed on the semiconductor substrate without using the dedicated mask for the power device and the dedicated mask for the bipolar transistor. As a result, the cost can be reduced in the semiconductor device in which the power device and the BiCMOS are formed on the same semiconductor substrate.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a longitudinal sectional view of a composite IC in the present embodiment. This composite IC is used as a member constituting an automobile controller, and is for driving a load such as a fuel injector (solenoid valve).
[0010]
Up-drain (UpDrain) MOSFET 8, NPN transistor 9, and CMOS 10 are integrated in the composite IC. The specifications of the up-drain MOSFET 8 which is a power device having a MOS structure are on the order of several amperes and several tens of volts, the specifications of the NPN transistor 9 and CMOS 10 (BiCMOS specifications) are on the order of milliamperes, and the applied voltage is about 10 volts. is there. The CMOS 10 is a double well CMOS in which both nMOS and pMOS are formed in the well.
[0011]
In FIG. 1, an SOI substrate 1 is used as a semiconductor substrate, and the SOI substrate 1 has a structure in which a thin silicon layer 4 is disposed on a p-type silicon substrate 2 with a silicon oxide film 3 interposed therebetween. In the silicon layer 4, n ^- N under the silicon layer 6 ⁺ A mold silicon layer 5 is embedded. n ⁺ The type silicon layer 5 is doped with antimony (Sb).
[0012]
A trench 7 is formed in the silicon layer 4, a silicon oxide film is formed on the inner wall surface thereof, and the trench 7 is filled with polysilicon. A large number of islands are defined by the trenches 7. On each island, an up drain MOSFET 8, an NPN transistor 9, and an nMOS and a pMOS constituting the CMOS 10 are formed.
[0013]
A detailed configuration of the up-drain MOSFET 8 is shown in FIG. A detailed configuration of the NPN transistor 9 of FIG. 1 is shown in FIG. Further, FIG. 4 shows a detailed configuration of the CMOS 10 of FIG.
[0014]
First, the CMOS 10 of FIG. 4 will be described.
nMOS formation island, n ^- A p-well region 50 is formed in the surface layer portion of the mold silicon layer 6. n ^- A polysilicon gate electrode 52 is formed on the mold silicon layer 6 via a gate oxide film 51. Inside the p-well region 50, the surface layer portion has n ⁺ Mold region 53 and n ⁺ The mold region 54 is formed at a spaced position. n ^- A source electrode (aluminum layer) 56 and a drain electrode (aluminum layer) 57 are arranged on the LOCOS oxide film 55 on the type silicon layer 6, and the source electrode (aluminum layer) 56 is n ⁺ The mold region 53 and the drain electrode (aluminum layer) 57 are n ⁺ In contact with the mold region 54.
[0015]
In the pMOS formation island of FIG. ^- An n-well region 58 is formed in the surface layer portion of the silicon layer 6, and the n-well region 58 is n ^- N from the surface layer of the silicon layer 6 ⁺ The type silicon layer 5 is reached. A polysilicon gate electrode 60 is formed on the n well region 58 through a gate oxide film 59. Inside the n-well region 58, the surface layer portion has p ⁺ Mold region 61 and p ⁺ The mold region 62 is formed at a spaced position. n ^- A drain electrode (aluminum layer) 63 and a source electrode (aluminum layer) 64 are disposed on the LOCOS oxide film 55 on the p-type silicon layer 6. ⁺ The mold region 61 and the source electrode (aluminum layer) 64 are p ⁺ In contact with the mold region 62.
[0016]
The up drain MOSFET 8 of FIG. 2 will be described. A polysilicon gate electrode 12 is disposed on the silicon layer 4 via a gate oxide film 11. N at the end of the polysilicon gate electrode 12 ^- A p-well region 13 is formed in the surface layer portion of the mold silicon layer 6. This p well region 13 is formed simultaneously with the p well region 50 of the double well CMOS 10 (FIG. 4). Inside the p-well region 13, the surface layer portion has n ⁺ Type region 14 and p ⁺ A mold region 15 is formed. The polysilicon gate electrode 12 is covered with a silicon oxide film 16. A source electrode (aluminum layer) 17 is disposed on the silicon oxide film 16, and the source electrode (aluminum layer) 17 is n ⁺ Type region 14 and p ⁺ In contact with the mold region 15.
[0017]
An n well region 18 is formed between the p well regions 13, that is, between the source cells. ^- N from the surface layer of the silicon layer 6 ⁺ The type silicon layer 5 is reached. This n-well region 18 is formed simultaneously with the n-well region 58 of the double well CMOS 10 (FIG. 4). Further, the n-type silicon layers 5 and 6 have deep n ⁺ The mold region 19 is formed deeper than the n-well region 18. Deep n ⁺ Inside the mold region 19, the surface layer portion has n ⁺ A mold region 20 is formed. A drain electrode (aluminum layer) 22 is disposed on the LOCOS oxide film 21 on the n-type silicon layers 5 and 6. ⁺ It is in contact with the mold region 20. A silicon oxide film 23 is formed on the drain electrode (aluminum layer) 22 and the source electrode (aluminum layer) 17.
[0018]
In such an up-drain MOSFET 8, a current is applied from the source electrode (aluminum layer) 17 by applying a voltage to the polysilicon gate electrode 12. ⁺ Type region 14 and p ⁺ Mold region 15 → surface layer portion of p well region 13 → n well region 18 → n ⁺ Type silicon layer 5 → deep n ⁺ Mold region 19 → n ⁺ It flows from the mold region 20 to the drain electrode (aluminum layer) 22.
[0019]
The NPN transistor 9 in FIG. 3 will be described. n ^- A p-well region 31 is formed in the surface layer portion of the mold silicon layer 6. This p well region 31 is formed simultaneously with the p well region 50 of the double well CMOS 10 (FIG. 4). Inside the p-well region 31, the surface layer portion has n ⁺ Type region 32 and p ⁺ The mold region 33 is formed at a spaced position. n ^- An emitter electrode (aluminum layer) 35 and a base electrode (aluminum layer) 36 are disposed on the LOCOS oxide film 34 on the type silicon layer 6. ⁺ The mold region 32 and the base electrode (aluminum layer) 36 are p ⁺ It is in contact with the mold region 33.
[0020]
N ^- An n-well region 37 is formed in the surface layer portion of the type silicon layer 6, and the n-well region 37 has n ^- N from the surface layer of the silicon layer 6 ⁺ The type silicon layer 5 is reached. This n-well region 37 is formed simultaneously with the n-well region 58 of the double well CMOS 10 (FIG. 4). Further, the n-type well region 37 has an n-type surface layer. ⁺ A mold region 38 is formed and is in contact with a collector electrode (aluminum layer) 39 on the LOCOS oxide film 34.
[0021]
Next, a method for manufacturing the composite IC will be described with reference to FIGS.
First, as shown in FIG. 5, an SOI wafer (SOI substrate) 1 is prepared. The thickness of the silicon layer 4 is about 13 μm and the embedded n ⁺ Layer 5 has a thickness of about 3 μm and a concentration of about 1 × 10 ¹⁵ cm ^-3 , Ρs is about 20Ω / □. Then, a trench 7 for element isolation is formed on the wafer 1. Specifically, the isolation trench is dug to a depth reaching the buried oxide film 3 by dry etching, chemical dry etching (CDE) is performed, and further, annealing is performed to recover the damage. Thereafter, side wall oxidation is performed, polysilicon is embedded, and further, chemical mechanical polishing (CMP) is performed to remove unnecessary polysilicon. Thereafter, the upper portion of the trench is flattened and the surface of the buried polysilicon is oxidized.
[0022]
Then, as shown in FIG. ⁺ For the formation of the mold region 19, phosphorus (P) is implanted (1 × 10 ¹⁵ cm ^-2 And heat treatment is performed at 1170 ° C. for about 3 hours.
[0023]
Further, as shown in FIG. 7, in order to form an n-well region (18, 37, 58), a mask M1 is disposed on the wafer 1 and phosphorus (P) is implanted (1 × 10 6). ¹² cm ^-2 Further, heat treatment is performed at 1170 ° C. for about 3 hours.
[0024]
Subsequently, as shown in FIG. 8, in order to form p-well regions 13, 31, and 50, a mask M2 is disposed on the wafer 1 and boron (B) is implanted (1 × 10 6). ¹³ cm ^-2 And heat treatment is performed at 1170 ° C. for about 3 hours. In this process, in the up drain MOSFET formation region, as shown in FIG. 15, impurities are implanted into the silicon layer 6 by ion implantation from the region 70a opened in each source cell with the mask 70 disposed.
[0025]
Thereafter, as shown in FIG. 9, LOCOS oxide films 21, 34, and 55 having a thickness of 1 μm are simultaneously formed. Further, as shown in FIG. 10, gate oxidation is performed to form gate oxide films 11, 51 and 59 having a film thickness of about 30 nm. Then, the threshold adjustment implant (Boron is 1 × 10 ¹² cm ^-2 Doze) and heat treatment. Thereafter, a polysilicon film to be a gate is deposited (thickness is about 300 nm), and this is patterned to form gate electrodes 12, 52, 60.
[0026]
Subsequently, as shown in FIG. 11, arsenic (As) is about 5 × 10 5. ¹⁵ Implant and n ⁺ Mold regions 14, 20, 32, 38, 53, 54 are formed. Further, as shown in FIG. 12, boron (B) is implanted (5 × 10 ¹⁵ cm ^-2 Doze) and p ⁺ Mold regions 15, 33, 61, 62 are formed. This completes all device processes of the power MOS, bipolar transistor, and CMOS.
[0027]
Further, as shown in FIG. 13, a BPSG film is deposited and reflowed, and contact holes 71 are formed by etching. Thereafter, as shown in FIG. 14, an aluminum layer (first layer) having a thickness of about 0.5 μm is formed by sputtering aluminum, and this is patterned to form aluminum layers 22, 17, 35, 36, 39, 56, 57, 63, 64 are formed.
[0028]
Thereafter, as shown in FIG. 1, an insulating film (TEOS film) 24 having a thickness of about 1 μm is deposited on the first aluminum layer (22, etc.), and via hole forming etching is performed on the film 24. A via hole 25 is formed. Further, an aluminum layer (second layer) having a thickness of about 1 μm is formed thereon by sputtering aluminum, and this is patterned to form a second aluminum layer 26. Thereafter, a SiN film having a thickness of about 1.5 μm is deposited to form a surface protective film 27. Then, by etching the pad portion with respect to the surface protective film 27, the pad portion of the second aluminum layer 26 is exposed to complete the wiring.
[0029]
Although the manufacture of the composite IC is thus completed, the trench 7 formation process may be performed after the device formation process.
In place of the up-drain MOSFET 8 shown in FIG. 2, an LDMOSFET that is also a lateral MOSFET may be used. An example of this is shown in FIG. In FIG. 16, a polysilicon gate electrode 102 is disposed on the silicon layer 4 via a gate oxide film 101. N at the end of the polysilicon gate electrode 102 ^- A p-well region 103 is formed in the surface layer portion of the p-type silicon layer 6, and n in the surface layer portion inside the p-well region 103. ⁺ Mold region 104 and p ⁺ A mold region 105 is formed. The above-mentioned polysilicon gate electrode 102 is covered with a silicon oxide film 106. A source electrode (aluminum layer) 107 is disposed on the silicon oxide film 106, and the source electrode (aluminum layer) 107 is n ⁺ Mold region 104 and p ⁺ It is in contact with the mold region 105. The p well region 103 is formed simultaneously with the p well region 50 of the double well CMOS 10 (FIG. 4).
[0030]
Also, an n-well region 108 is formed between the p-well regions 103 in FIG. 16, that is, between the source cells. ^- N from the surface layer of the silicon layer 6 ⁺ The type silicon layer 5 is reached. The surface layer inside the n-well region 108 has n ⁺ A mold region 109 is formed and n ⁺ The mold region 109 is in contact with the drain electrode (aluminum layer) 110. N well region 108 is formed simultaneously with n well region 58 of double well CMOS 10 (FIG. 4).
[0031]
In the manufacturing process of the LDMOSFET 100, as shown in FIG. 17, impurities are implanted into the silicon layer 6 by ion implantation from the region 111a opened in each source cell with the mask 111 disposed.
[0032]
Further, instead of the NPN transistor of FIG. 3, the PNP transistor shown in FIG. 18 may be formed. That is, n ^- P well regions 121 and 122 are formed in the surface layer portion of the type silicon layer 6. The p well regions 121 and 122 are formed simultaneously with the p well region 50 of the double well CMOS 10 (FIG. 4). In the p well region 121, the surface layer portion has p ⁺ A mold region 123 is formed. A collector electrode (aluminum layer) 125 is disposed on the LOCOS oxide film 124 on the silicon layer 4. ⁺ It is in contact with the mold region 123. Inside the p-well region 122, the surface layer portion has p ⁺ A mold region 126 is formed and is in contact with the emitter electrode 127.
[0033]
N ^- An n-well region 128 is formed in the surface layer portion of the silicon layer 6, and the n-well region 128 is n ^- N from the surface layer of the silicon layer 6 ⁺ The type silicon layer 5 is reached. Further, the n-type well region 128 has n on its surface layer. ⁺ A mold region 129 is formed and is in contact with the base electrode (aluminum layer) 130 on the LOCOS oxide film 124. Similarly, n ^- An n-well region 131 is formed between the p-well region 121 and the p-well region 122 in the surface layer portion of the type silicon layer 6. The n well regions 128 and 131 are formed simultaneously with the n well region 58 of the double well CMOS 10 (FIG. 4).
[0034]
Thus, the p-well region 50 of the double well CMOS 10 of FIG. 4 is formed in the channel p-well region 13 of the power device 8 of FIG. 2, the n-well region 18 of the up-drain MOSFET 8 of FIG. 2, and the well region 108 of the LDMOSFET of FIG. In order to optimize the required withstand voltage and on-resistance, the n-well region 58 of the double well CMOS shown in FIG. For example, in the conventional DSAMOS (Double diffused Self Aligned MOS) shown in FIGS. 23 and 24, the channel p-well region 200 is formed by thermal diffusion using a gate polysilicon as a mask as shown in FIG. In the previous step of polysilicon arrangement, p well regions 13, 31, 50 are implanted from the polysilicon arrangement planned region (from the polysilicon window), for example, by expanding by about 1 μm, thereby forming a well equivalent to a conventional channel p well. To do. Further, as shown in FIG. 24, the n-well region 18 of the up-drain MOSFET of FIG. 2 is conventionally formed by being implanted and diffused over the entire element region. However, as shown in FIG. If the n-well region 58 is replaced, the concentration is too high and the breakdown voltage is reduced. Therefore, only between the source cells of FIG. 2 is implanted at the same time as the formation of the n-well region 58 in the CMOS, and the underlying buried n is formed by thermal diffusion. ⁺ By reaching the diffusion layer 5, the channel resistance and the epi-substrate resistance can be reduced, and only the on-resistance of the element can be lowered without lowering the breakdown voltage.
[0035]
Similarly, in the LDMOSFET of FIG. 16, as shown in FIG. 24, the optimum design of withstand voltage and on-resistance was conventionally made by placing the n well over the entire element region. By simultaneously implanting the n well region 108 at the time of formation, the withstand voltage and the on-resistance can be optimized even in the case of a dense well.
[0036]
For the NPN transistor of FIG. 3, the conventional base / emitter shown in FIG. 25 is replaced with the p-well region 50, n of the CMOS of FIG. ⁺ The regions 53 and 54 are formed simultaneously. 18, the emitter / collector regions (121, 122) are formed by a CMOS p-well region 50, and the base region (128) is formed by a CMOS n-well region 58. By doing so, process reduction and size reduction can be performed.
[0037]
Next, the p well and n well regions will be described.
First, the p-well region will be described.
Conventionally, a power MOSFET (up drain, LDMOS) in a composite IC process performs ion implantation for forming a channel region using a well dedicated to a power device (channel p well) as a gate polysilicon as a mask, and performs heat treatment, Furthermore, n is masked using the same polysilicon. ⁺ A device was formed by performing ion implantation for forming a source region. The reason why double diffused MOS (DMOS) using such gate polysilicon as the diffusion window for implants was originally developed was that IC processing technology at the time of development (around 1970) used exposure equipment and device processing accuracy. (Minimum processing size at the time of development is about 10 μm), and the channel resistance is small, that is, the gate channel length is sufficiently short (about 1 μm), it is not possible to make a MOS. Region and n ⁺ A double diffusion method has been devised for region formation. This technique can automatically align the ion implantation layer for forming the channel region and the gate polysilicon mask, determine the channel length by diffusion of impurities by heat treatment, and can be stably manufactured even with a short channel length. It is still used in discrete power devices such as IGBTs. In addition, the conventional power MOS device design and gate channel processing method have been followed in the composite IC process for forming power devices.
[0038]
However, recent VLSI processing technology has progressed to the point where sub-micron (about 0.1 μm) gate lengths can be formed, and the mask alignment accuracy is so high that it cannot be compared with the 1970s (standard deviation 3σ is high). 0.1 μm or less). The compound IC process that forms bipolar transistors, CMOS, and power devices on a single chip now uses the same high-precision processing and exposure equipment as the LSI process, so double diffusion using polysilicon as a mask is not necessary. There is no need to do that. In other words, the DMOS channel region is replaced with a CMOS p-well layer, and a LOCOS process, a polysilicon formation process, and a source n ⁺ Even if the DMOS is processed in the CMOS process sequence such as the region forming process, it is possible to produce a power MOS having a channel length of about 1 μm, that is, having a small channel resistance, as in the conventional double diffusion method.
[0039]
However, since the order of the gate formation and the channel region formation is reversed from the conventional one, the layout of the p-well region needs to be devised. In other words, in order to design the channel length to about 1 μm, it is necessary to implant the p-well (reference numeral 13 in FIG. 2) into a size that overlaps the polysilicon window by 1 μm or less (the conventional channel in FIG. 23). Was ion-implanted all over the source cell).
[0040]
In other words, the channel length, which has been conventionally adjusted by the heat treatment temperature and time, is determined by the p-well formation mask and the polysilicon mask. Mask accuracy (alignment, minimum dimension) is 0.1 μm or less, and channel length and symmetry within the cell can be sufficiently secured.
[0041]
Next, how to insert an n-well (CMOS) will be described.
When a CMOS n-well is inserted for the purpose of lowering the epi-resistance (in the case of up-drain MOSFET) and drift resistance (in the case of LDMOS), if ion implantation is performed on the entire surface of the power device formation region as in the prior art, the p-well concentration in the channel portion is Decreasing by overlapping with the n-well (for example, the p-region 13 in FIG. 2 is overlapped by the n-well region 18 formed on the entire surface), and it is easy to punch through in the channel portion, resulting in a decrease in drain breakdown voltage. . Because the threshold voltage Vth (about 1 volt) of CMOS is generally lower than the Vth value (about 2 volts) of DMOS, the p-well concentration is conventionally lower than the channel p-well concentration of DMOS (about 1/5 in dose). On the other hand, the density of the n-well of the CMOS is higher (approximately twice) than that of the conventional n-well of the DMOS (n-well in the up-drain MOS, n-well in the LDMOS) in which ions are implanted into the entire surface. is there. Therefore, the n-well (CMOS) is ion-implanted so as not to cover the channel well portion but the entire surface of the power MOS. Specifically, the up-drain MOS in FIG. 2 is only between the channel p-well region 13 and the channel p-well region 13 (that is, between adjacent source cells), and the LDMOS in FIG. 16 is only in the drain cell adjacent to the source cell. It is devised to put it in.
[0042]
By doing so, the power MOS channel p-well, the n-well region of the up-drain MOSFET, and the n-well region of the LDMOSFET can be substituted in the n- and p-well regions of the CMOS, and photo, implantation process and mask reduction can be achieved.
[0043]
Next, the bipolar transistor will be described.
In the conventional lateral PNP transistor structure shown in FIG. 26, in order to maintain the breakdown voltage between the emitter and the collector, it is necessary to increase the distance L to some extent. Specifically, in order to ensure the collector breakdown voltage of the NPN transistor (collector breakdown voltage Vceo is 25 volts or more in the case of an automotive composite IC specification), n ^- Substrate concentration is about 1 × 10 ¹⁵ cm ^-3 N because it is lowered ^- In the conventional PNP transistor structure of FIG. 26 in which the substrate is used as a base layer of a lateral PNP transistor as it is, it is easy to punch through between the collector and the emitter, so it is necessary to separate the gap (about 10 μm if Vceo is 25 volts or more). There is a limit to reducing the size for these pressure-resistant design reasons. For the same reason, n ^- Special arrangements such as suppressing the extension of the depletion layer and ensuring a withstand voltage by arranging polysilicon (reference numeral 250 in FIG. 26) on the base layer and making the polysilicon potential common to the emitter are required. In the method using the polysilicon 250 as the reverse field plate, the breakdown voltage between the collector and the emitter when the collector voltage is larger than the emitter voltage can be secured (Vceo is about 60 volts), but conversely, the emitter voltage is larger than the collector voltage. In this case, since the breakdown voltage between the emitter and the collector decreases (Veco is about 6 volts), attention must be paid to the circuit design such that the potential relationship is not reversed.
[0044]
Therefore, in this example of FIG. ^- By placing a CMOS n-well region 131 in a part of the base region, ^- Partially increase the concentration to prevent the depletion layer from extending. As a result, the circuit can be designed because the structure is such that the breakdown voltage between the emitter and the collector is secured at a narrower interval (L dimension in FIG. 18) than the conventional one, and has no breakdown voltage polarity as in the case of the polysilicon reverse field plate method. A simple and small PNP transistor can be realized. As for the current amplification factor, the n-well region 131 is arranged almost at the center between the emitter and the collector to prevent the emitter-base interface concentration from decreasing, thereby reducing the emitter injection efficiency and reducing the emitter-collector spacing. Since the transport efficiency of holes injected from the emitter is substantially unchanged, the current amplification factor hfe is hardly lowered.
[0045]
Similarly, even if the p-type well region 50 and the source / drain regions 53, 54, 61, 62 of the CMOS of FIG. 4 are used as the base / emitter of the NPN transistor of FIG. 3, the conventional dedicated base / emitter process of FIG. The base active layer (the portion obtained by subtracting the emitter layer 240 overlaid from the base layer 230) and the p-well concentration of the CMOS are close (about 1 × 10 ¹⁶ cm ^-3 ) And emitter layer 240, n ⁺ Source / drain concentration is also about 1 × 10 ²⁰ cm ^-3 Therefore, the injection efficiency and the transport efficiency do not change, and the current amplification factor hfe hardly decreases. Also, the diffusion depth of the conventional emitter layer 240 of FIG. 25 is about 2 μm, which is the n-thickness of CMOS in FIG. ⁺ The region 32 having a diffusion depth of about 0.2 μm is used to reduce the distance between the base contact and the emitter contact (L dimension in FIG. 3), thereby reducing the element size.
[0046]
Regarding the switching speed, the delay time from ON to OFF operation is dominant in the SOI / trench isolation structure, but this is due to the residual holes accumulated in the device region that was originally separated from the oxide film, and the element size is reduced. By doing so, the absolute number of residual holes can be reduced, and the switching speed increases.
[0047]
As described above, the channel wells necessary for forming the power device, the n-well in the up-drain MOSFET, and the well in the LDMOSFET are all replaced with CMOS wells, thereby reducing the number of dedicated steps for the power device. The base and emitter of the bipolar transistor are also CMOS p-well, n ⁺ Instead, the manufacturing cost can be reduced by reducing the number of steps dedicated to bipolar transistors.
[0048]
Thus, the present embodiment has the following features.
(A) In order to manufacture a semiconductor device in which at least the up-drain MOSFET 8, the NPN transistor 9, and the double well CMOS 10 are formed on the same SOI substrate 1, as shown in FIG. Using the mask M1, n-well regions (first conductivity type well regions) 18, 37, 58 are simultaneously formed in the formation regions of the up drain MOSFET 8, the NPN transistor 9, and the double well CMOS 10, respectively, as shown in FIG. As described above, using the second mask M2 disposed on the SOI substrate 1, a p-well region (second conductivity type well region) is simultaneously formed in each of the formation regions of the up drain MOSFET 8, the NPN transistor 9, and the double well CMOS 10. 13, 31 and 50, and as shown in FIG. ET8 and a formation region of the double well CMOS10 placing the polysilicon gate electrode 12,52,60 simultaneously.
[0049]
That is, as shown in FIG. 1, the n and p well regions 50 and 58 used in the double well CMOS 10 are also formed in the formation region of the up drain MOSFET 8 and the formation region of the NPN transistor 9, respectively. 18, 31, 37) constitute the up drain MOSFET 8 and the NPN transistor 9.
[0050]
Therefore, power MOSFETs used in automotive controllers generally require low cost, low on-resistance, and high withstand capability. However, power devices can be applied to the SOI substrate 1 without using dedicated masks for the up-drain MOSFET 8 and the NPN transistor 9. 8. A bipolar transistor 9 can be formed. As a result, the cost can be reduced in the composite IC in which the power device 8 and BiCMOS are formed on the same SOI substrate 1.
[0051]
Although the N channel type MOS has been described above, the same effect can be expected for the P channel MOS if the n well and the p well are exchanged.
The power device is not limited to the MOSFET, and the same applies to power devices such as IGBTs and thyristors.
[0052]
Specifically, with respect to the IGBT, as shown in FIG. 19, the p-well region 140 is locally formed in the emitter and the n-well region 141 is locally formed in the collector. As shown in FIG. 20, the conventional IGBT is made of SiO. ₂ A p-well region 150 is formed on the surface layer side of the upper silicon layer, and an n-well region 151 is formed on the entire surface layer portion, but in the case of FIG. 19, it is formed simultaneously with the well in the CMOS. The p well region 140 and the n well region 141 are used to form an IGBT. As for the thyristor, as shown in FIG. 21, a p-well region 160 is locally formed at the gate and the cathode, and an n-well region 161 is locally formed between the gate and the cathode and the anode. As shown in FIG. 22, the conventional thyristor is made of SiO. ₂ A p-well region 170 is formed on the surface layer side of the upper silicon layer, and an n-well region 171 is formed on the entire surface layer portion, but in the case of FIG. 21, it is formed simultaneously with the well in the CMOS. A thyristor is configured using the n-well region 161 and the p-well region 160.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a composite IC in an embodiment.
FIG. 2 is a configuration diagram of an up-drain MOSFET.
FIG. 3 is a configuration diagram of an NPN transistor.
FIG. 4 is a configuration diagram of a double well CMOS.
FIG. 5 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 6 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 7 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 8 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 9 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 10 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 11 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 12 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 13 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 14 is a longitudinal sectional view showing a manufacturing process of the composite IC in the embodiment.
FIG. 15 is a view for explaining a manufacturing process of the composite IC.
FIG. 16 is a configuration diagram of an LDMOSFET.
FIG. 17 is a view for explaining a manufacturing process of the composite IC.
FIG. 18 is a configuration diagram of a PNP transistor.
FIG. 19 is a configuration diagram of the IGBT of this example.
FIG. 20 is a configuration diagram of a conventional IGBT.
FIG. 21 is a configuration diagram of a thyristor of this example.
FIG. 22 is a configuration diagram of a conventional thyristor.
FIG. 23 is a configuration diagram of a conventional up-drain MOSFET.
FIG. 24 is a configuration diagram of a conventional LDMOSFET.
FIG. 25 is a configuration diagram of a conventional NPN transistor.
FIG. 26 is a configuration diagram of a conventional PNP transistor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... SOI substrate, 8 ... Up drain MOSFET, 9 ... NPN transistor, 10 ... Double well CMOS, 12 ... Polysilicon gate electrode, 13 ... p well region, 18 ... p well region, 31 ... p well region, 37 ... n Well region 50 ... p well region 52 ... polysilicon gate electrode 58 ... n well region 60 ... polysilicon gate electrode M1 mask M2 mask

Claims (7)

A semiconductor device in which a power device, an NPN / PNP bipolar transistor and a double well CMOS are formed on the same semiconductor substrate,
The n and p well regions used in the double well CMOS are also formed in the power device forming region and the NPN / PNP bipolar transistor forming region, respectively, and between the source cells in which the p well region of the power device is formed, the NPN bipolar transistor A semiconductor device characterized in that an n-well region used in the double well CMOS is also formed between the collector and the collector and emitter of a PNP bipolar transistor to constitute a power device and a bipolar transistor. The power device is an LDMOSFET, a source channel is formed by a CMOS p-well region, and a CMOS n-well region is formed so as to partially overlap the drain to source channel. A semiconductor device according to 1. The power device is an IGBT , an emitter channel is formed of a CMOS p-well region, and a CMOS n-well region is formed so as to partially overlap the collector to the emitter channel. A semiconductor device according to 1. The power device is a thyristor, and is formed locally in a CMOS p-well region in a gate / cathode channel, and a CMOS n-well region is formed locally between a gate / cathode channel and an anode channel. The semiconductor device according to claim 1. A method of manufacturing a semiconductor device in which a power device having an MOS structure, an NPN / PNP bipolar transistor, and a double well CMOS are formed on the same semiconductor substrate,
Using a p-well mask disposed on a semiconductor substrate to simultaneously form a p- well region in each of the power device, the NPN / PNP bipolar transistor, and the double-well CMOS formation region;
Using a mask of n-well disposed on a semiconductor substrate, between the power devices and NPN, PNP bipolar transistors and the respective formation regions of the double-well CMOS, and the power device of the p source cell well region Ru is formed, Simultaneously forming the n-well region of the double well CMOS between the collector of the NPN bipolar transistor and the collector and emitter of the PNP bipolar transistor;
Simultaneously arranging a gate electrode in a region where the power device and the double well CMOS are formed;
A method for manufacturing a semiconductor device, comprising: 6. The power device is an LDMOSFET, a source channel is formed by a CMOS p-well region, and a CMOS n-well region is formed so as to partially overlap the drain to source channel. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 6. The power device is an IGBT , an emitter channel is formed by a CMOS p-well region, and a CMOS n-well region is formed so as to partially overlap the collector to the emitter channel. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

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