JP4262274B2 - Display device - Google Patents

Description

  The present invention relates to a hold-type display device typified by a TFT liquid crystal display, and relates to a display device that realizes an improvement in image quality when a moving image is displayed.

  Active matrix display devices such as TFT liquid crystal displays are widely used as display devices in mobile devices such as mobile phones and personal digital assistants because of their thinness, high definition, and low power consumption. In particular, mobile phones have become more sophisticated, and the number of scenes in which moving images are used in one-segment broadcasting, playback of recorded videos, and applications including games has increased. However, TFT liquid crystal is a hold-type drive that continues to display the same image for one frame period. When a moving image is displayed, the image remains as an afterimage on the retina, and the phenomenon that the outline of the displayed image appears blurred (hereinafter referred to as “moving image blur”). ") Occurs.

  As a countermeasure against image quality degradation that occurs in such a hold-type display device, Patent Document 1 below cancels retinal afterimages and improves video blurring by inserting a black display period into one frame period. A method has been proposed. However, with such black insertion, a method of using an impulse-type drive such as a CRT (cathode ray tube) in a pseudo manner causes a reduction in the maximum luminance and contrast of a display image.

On the other hand, in Patent Document 2 described below, although one frame is divided into several subframes and the luminance reduced by black insertion is compensated by other subframes, the pseudo impulse type drive is used. There has been proposed a method that does not cause a decrease in luminance or contrast when viewed over a period. In this method, it is necessary to create low-intensity subframe data for pseudo impulse driving and high-intensity subframe data for luminance compensation from one frame data input to the system. A lookup table (hereinafter referred to as “LUT”) is used. Hereinafter, this method is referred to as “LUT method”. In order to realize such an LUT method, a storage device having a large capacity is required as an LUT for storing data after conversion processing, but the circuit area when mounted on hardware such as an LSI increases. This not only leads to an increase in cost, but is difficult to apply to mobile devices with severe restrictions on circuit area.
JP 2000-122596 A JP 2005-173387 A

  When pseudo impulse driving is performed in order to improve the motion blur of the hold-type display device in such an LUT method, when one frame is time-divided into a plurality of subframes, For example, if the number of gradations is 256 gradations and the gradation data is 8 bits, an LUT having a size of “256 gradations × 8 bits × 2 subframes = 4096 bits” is necessary, and there is a concern about an increase in cost.

  Also, instead of the LUT method, at least two types of gradation voltages can be set in the gradation voltage generation circuit, and one frame is time-divided into a plurality of fields, and at least two types of gradation voltages are switched for each field. There is a current method of outputting to a display device. However, since the gradation voltage generation circuit in this current method generates a gradation voltage by, for example, dividing the reference voltage by resistance, when the voltage dropped by the resistance division is Vd, for example, V1 The gradation voltage has a relationship of V1 = V0−Vd, and the same relationship is applied to other gradation voltages (V2 to V63). Accordingly, the gradation voltages (V1 to V63) are all different, and any of the gradation voltages (V1 to V63) cannot be made the same.

  FIGS. 11A and 11B show gradation number-gradation voltage characteristics when pseudo impulse driving is performed when the LUT is used and when the LUT is not used. 11A shows the gradation number-gradation voltage characteristics at the time of the positive electrode, and FIG. 11B shows the gradation number-gradation voltage characteristics at the time of the negative electrode. Further, in FIGS. 11 (a) and 11 (b), when the counter electrode applied voltage is 0V at the positive electrode and 4V at the negative electrode, the luminance of the liquid crystal panel is increased by increasing the gradation voltage at the positive electrode. When the negative electrode is used, the brightness of the liquid crystal panel is lowered by increasing the gradation voltage.

  In the gradation number-gradation voltage characteristics when the LUT is used as shown in FIG. 11A, the low potential gradation voltage continues for a while in the dark field, whereas the pseudo impulse generated by the LUT unused gradation voltage generation circuit. In the current method in which mold driving is performed, the gradation voltage increases as the gradation number increases, but the luminance of the liquid crystal panel is higher than that in the LUT method.

  Also in FIG. 11B, as in FIG. 11A, the luminance of the liquid crystal panel is lower in the current method than in the LUT method. For this reason, the current method cannot obtain the effect of improving the motion blur as much as the LUT method.

  In the present invention, at least two kinds of gradation voltages can be set in the gradation voltage generation circuit, and one frame is divided into at least two fields, and at least two kinds of gradation voltages are switched for each field in the display device. By outputting, the gray scale requested from the external system is displayed in a pseudo manner.

  Here, the two types of gradation voltages are a gradation voltage that becomes a dark luminance display field (hereinafter referred to as “dark field”) as close to black display as possible and a luminance reduced by the dark field by high gradation display. It is a gradation voltage that becomes a bright luminance display field to be compensated (hereinafter referred to as “bright field”). These two kinds of gradation voltages are output to the display device.

  In the present invention, when generating a gradation voltage by a gradation voltage generation circuit during pseudo impulse driving, the gradation voltage of the same voltage can be obtained by arbitrarily passing a resistance between gradations and not dividing the resistance. Since the luminance characteristics similar to those of the LUT method can be obtained by generating, a large-capacity LUT is not required other than the registers necessary for storing the operation parameters.

  As described above, according to the present invention, pseudo-impulse drive that improves the moving image display performance of the hold-type display device without lowering the brightness and contrast is displayed using the drive method that does not use the LUT, and the low-cost display. The device can be realized.

  The present invention can be used regardless of the size of the display device with respect to the hold-type display device, and is particularly suitable for display devices such as mobile phones and portable information terminals that are severely limited in cost and circuit area. .

  Embodiments of the present invention will be described below with reference to the drawings.

  A driving method for improving motion blur of the hold type display device according to the first embodiment of the present invention will be described. FIG. 1 shows a configuration diagram of a liquid crystal display device according to the present embodiment. Note that a liquid crystal display device is given as an example of the hold type display device, but the present invention can be applied to other hold type drive display devices. In this embodiment, 64 gradation control is performed. Therefore, the information amount of the input display data is 18 (6 × 3) bits per color pixel.

  In FIG. 1, 100 is a CPU, 101 is a signal line driver circuit, 102 is a system interface, 103 is a control register, 104 is a timing controller, 105 is a γ adjustment register, 108 is a gradation voltage generation circuit, and 114 is a memory control circuit. 115 is a display RAM, 116 is a latch circuit, 117 is an output control circuit, 118 is a scanning line driving circuit, and 119 is a liquid crystal panel.

  Here, the signal line driver circuit 101 is a so-called display memory built-in controller / driver, and includes means for realizing the present invention. Hereinafter, the configuration and operation of the internal block of the signal line driver circuit 101 will be described.

  The system interface 102 receives display data and instructions output from the CPU 100 that is an external system, and outputs them to the control register 103. Here, the instruction is information for determining the internal operation of the signal line driver circuit 101 and includes various parameters such as a frame frequency, the number of drive lines, and a drive voltage.

  The control register 103 is a block that stores instruction data and outputs it to each block. For example, instructions related to the frame frequency, the number of drive lines, and the data voltage switching timing are output to the timing controller 104, and instructions related to the potential of the gradation voltage are output to the γ adjustment register 105. The display data is also temporarily stored in the control register 103, and is output to the memory control circuit 114 together with instructions for indicating the display position.

  The memory control circuit 114 is a block that performs write and read operations of the display RAM 115. First, during a write operation, a signal for selecting an address of the display RAM 115 is output based on the display position instruction transferred from the control register 103. At the same time, display data is transferred to the display RAM 115. With this operation, display data can be written to a predetermined address in the display RAM 115. On the other hand, during the read operation, the operation of sequentially selecting a predetermined word line group in the display RAM 115 one by one is repeated. With this operation, the display data on the selected word lines can be read all at once via the bit lines. It should be noted that setting of the range of the word line to be read, one selection period (equivalent to one scanning period), selection operation repetition period (equivalent to one frame period), and the like are instructed by the instruction.

  The display RAM 115 has word lines and bit lines corresponding to the scanning lines and signal lines of the liquid crystal panel 119, and performs display data write operations and read operations. Note that the read display data is temporarily held by the latch circuit 116 and then output to the output control unit 117.

  The timing controller 104 self-generates and outputs a signal group indicating one scanning period, one frame period, and the like based on a reference clock generated by a built-in oscillator.

  The γ adjustment register 105 includes a positive register 106 and a negative register 107. The instruction input from the control register 103 is held in the positive register 106 and the negative register 107 and is output to the gradation voltage generation circuit 108.

  The gradation voltage generation circuit 108 includes a positive ladder circuit 109 and a negative ladder circuit 110 as a reference ladder circuit, a selection circuit 111, a buffer circuit 112, and a gradation voltage ladder circuit 113. First, based on the γ adjustment signal inputted from the γ adjustment register 105, the differential voltage between the reference high voltage and the reference low voltage is resistance-divided by the positive ladder circuit 109 and the negative ladder circuit 110 to obtain 12 levels. And a reference voltage (hereinafter referred to as “reference voltage”).

  The selection circuit 111 selects one of the reference voltages generated by the positive ladder circuit 109 and the negative ladder circuit 110 based on the alternating signal and outputs the selected reference voltage to the buffer circuit 112. The buffer circuit 112 buffers the input reference voltage by a voltage follower circuit and outputs the buffered voltage to the gradation voltage ladder circuit 113.

  The gradation voltage ladder circuit 113 divides the resistance based on the inputted 12-level reference voltage, generates a gradation voltage of 64 levels, and outputs it to the output control circuit 117.

  The output control circuit 117 selects one level among the 64 levels of gradation voltages input from the gradation voltage generation circuit 108 based on the display data input from the latch circuit 116, and the signal line 121 of the liquid crystal panel 119. Output to.

  The scanning line driving circuit 118 is a block for outputting the scanning voltage (“high” level in this embodiment) indicating the selected state in line-sequentially to the scanning line 120 of the liquid crystal panel 119 in synchronization with one scanning period. is there. Here, the timing of outputting the “high” level to the head scanning line is synchronized with the timing of reading the head word line in the display RAM 115.

  The liquid crystal panel 119 is a so-called active matrix type flat panel in which a switching transistor 122 is disposed in each pixel portion located at the intersection of the signal line 121 and the scanning line 120. The source terminal of the transistor 122 is connected to the output of the output control circuit 117 through the signal line 121, and the gate terminal is connected to the output of the scanning line driving circuit 118 through the scanning line 120. The drain terminal of the transistor 122 is connected to the display element 123. Note that a common electrode is connected to the opposite side of the display element 123, and a Vcom voltage is output to the common electrode. Therefore, in the scanning line 120 in the selected state, the voltage difference between the gradation voltage and the Vcom voltage becomes the voltage applied to the display element 123.

  Further, in this embodiment, the Vcom potential at the positive electrode is 0 V, and the Vcom potential at the negative electrode is 4 V. Therefore, at the positive electrode, the luminance is increased by increasing the gradation voltage (by reducing the gradation voltage). When the negative electrode is negative, the luminance is increased by decreasing the gradation voltage (the luminance is decreased by increasing the gradation voltage). Note that the type of the display element 123 is typically liquid crystal or organic EL, but other elements may be used as long as the display luminance can be controlled by voltage.

  Next, the internal block configuration and operation of the timing controller 104 will be described with reference to FIG. In FIG. 2A, 200 is a register, 201 is an internal clock generation circuit, 202 is a clock counter, 203 is a horizontal synchronization signal generation circuit, 204 is an AC signal generation circuit, 205 is a line counter, and 206 is a vertical synchronization signal generation. A circuit, 207 is a γ set value switching signal generation circuit, and 208 is an odd / even frame signal generation circuit.

  One scan period, one frame period, one field period, and the like input from the control register 103 shown in FIG. 1 are held in the register 200 and output to the clock counter 202 and the line counter 205.

  The internal clock generation circuit 201 generates a reference operation clock CLK and outputs it to each circuit. Each circuit operates based on the reference clock CLK generated by the internal clock generation circuit 201.

  The clock counter 202 counts the reference clock up to the CLK value of one scanning period input from the register 200, and outputs the clock count value to the horizontal synchronization signal generation circuit 203. Note that the clock count value of the clock counter 202 exceeds the CLK value in one scanning period, or is cleared at the falling edge of the input horizontal synchronization signal Vsync (“low” active in this embodiment) (count value = “0”).

  The horizontal synchronization signal generation circuit 203 generates and outputs a horizontal synchronization signal CL1 based on the clock count value input from the clock counter 202. The horizontal synchronization signal CL1 rises when the clock count value is “0” (“high” active in this embodiment) and is output “high” until the active period of the horizontal synchronization signal input from the register 200. .

  The line counter 205 counts up to the number of lines in one field period input from the register 200 in synchronization with the rising edge of the horizontal synchronization signal CL1, and outputs the line count value to the vertical synchronization signal generation circuit 206. Note that the line count value of the line counter 205 is cleared (count value = “0”) at the falling edge of the horizontal synchronization signal Vsync that exceeds the number of lines in one field period.

  The vertical synchronization signal generation circuit 206 generates and outputs a vertical synchronization signal FLM based on the count value input from the line counter 205. The vertical synchronization signal FLM rises when the line count value is “0” (“high” active in this embodiment), and is output “high” until the active period of the vertical synchronization signal input from the register 200. .

  The AC signal generation circuit 204 generates and outputs an AC signal M based on the AC signal input from the register 200 (in this embodiment, “0” during frame AC driving and “1” during line AC driving).

  The γ set value switching signal generation circuit 207 generates a γ set value switching signal based on the vertical synchronization signal FLM. The odd / even frame signal generation circuit 208 generates and outputs an odd / even frame signal based on the inputted Vsync.

  Next, the operation timing of the signal group generated by the timing controller 104 will be described with reference to FIG. In the case of performing the pseudo impulse driving, the vertical synchronization signal FLM is activated twice (one frame period is divided into two subfields) during one frame period of the input Vsync. Thereby, it is possible to provide a field period of two fields in one frame period. Note that when pseudo impulse driving is not performed, the waveform is the same as that of the input Vsync.

  The horizontal synchronization signal CL1 is activated by the number of lines set in the register 200. In this embodiment, since one frame is divided into two fields, one scanning period when the pseudo impulse type driving is performed is half of the one scanning period when the pseudo impulse driving is not performed. It will be time.

  The alternating signal M repeatedly outputs “high” and “low” according to the alternating method set in the register 200. In this embodiment, since line AC driving is set, “high” or “low” is output in one scanning period.

  The γ set value switching signal repeatedly outputs “high” or “low” for one field period according to the vertical synchronization signal FLM.

  The odd / even frame signal repeatedly outputs “high” or “low” for one frame period according to the inputted Vsync.

  Note that the display data held in the display RAM 115, when performing pseudo impulse driving, reads display data for one frame in one field period, and is odd when the odd / even frame signal is “high” output. When the frame display data and the odd / even frame signal are “low”, the even frame display data is output. In this embodiment, the odd / even frame signal indicates an odd number when "high" is output and an even number when "low" is output. When pseudo impulse driving is not performed, display data for one frame is read and output in one frame period.

  Next, the configuration of the internal block of the positive electrode register 106 shown in FIG. 1 will be described with reference to FIG. The circuit configuration and operation of the negative register 107 are the same as those of the positive register 106.

  In FIG. 3A, 300 is a normal γ register, 301 is a bright field register, 302 is a dark field register, 303 is an amplitude register, 304, 306 and 308 are tilt registers, 305, 307 and 309 are fine adjustment registers, 310 Reference numeral 311 denotes a selection circuit.

  The normal γ register 300 is a register that holds the γ register value when the pseudo impulse type drive is not used, and the bright field γ register 301 is a register that holds the γ register value for the bright field at the time of the pseudo impulse type drive. The dark field γ register 302 is a register that holds a γ register value for the dark field at the time of pseudo impulse driving.

  The γ register values input from the control register 103 shown in FIG. 1 are classified into amplitude register values, slope register values, and fine adjustment register values. By outputting these register values to the gradation voltage generation circuit 108, By adjusting the variable resistors in the positive ladder circuit 109 and the negative ladder circuit 110 in the regulated voltage generation circuit 108, the potential of the gradation voltage can be set.

  The amplitude register value is a setting value for adjusting the amplitude of the gradation voltage, and the inclination adjustment register value is for adjusting the inclination near the center of the gradation number-gradation voltage characteristics without greatly changing the dynamic range. The fine adjustment register value is a setting value for fine adjustment of the gradation voltage level.

  These amplitude adjustment register value, inclination register value, and fine adjustment register value are stored in the amplitude register 303 in the normal γ register 300, the bright field γ register 301, and the dark field γ register 302, and in the inclination registers 304, 306, and 308, respectively. They are held in the adjustment registers 305, 307, and 309, respectively.

  Note that the amplitude register value is held only in the amplitude register 303 of the normal γ register 300 because the amplitude register value is the same value (the amplitude of the gradation voltage is constant) regardless of whether the pseudo impulse drive is used or not. Even when using the pseudo impulse drive, the amplitude register value held in the amplitude register 303 is output to the gradation voltage generation circuit 108, thereby suppressing an increase in circuit scale.

  When the FBI on-register data input from the control register 103 is “low” in this embodiment, the selection circuit 310 indicates that the pseudo impulse drive is used when “high” and the pseudo impulse drive is not used when “low”. The slope register value held in the slope register 304 of the normal γ register 300 is selected and output to the gradation voltage generation circuit 108. Further, when the FBI ON register data is “high” and the γ set value switching signal (in this embodiment, the bright field is indicated at “high” level and the dark field is indicated at “low” level), the dark field is indicated at “high” level. The slope register value held in the slope register 306 of the bright field γ register 301 is selected, and held in the slope register 308 of the dark field γ register 302 when the FBI on register data is “high” and the γ set value switching signal is “low” level. The selected slope register value is selected and output to the gradation voltage generation circuit 108.

  When the FBI on-register data input from the control register 103 is “low”, the selection circuit 311 selects the fine adjustment register value held in the fine adjustment register 305 of the normal γ register 300, and sends it to the gradation voltage generation circuit 108. Output. When the FBI on register data is “high” and the γ set value switching signal is “high” level, the fine adjustment register value held in the fine adjustment register 307 of the bright field γ register 301 is selected, and the FBI on register data is selected. Is “high” and the γ set value switching signal is “low” level, the fine adjustment register value held in the fine adjustment register 309 of the dark field γ register 302 is selected and output to the gradation voltage generation circuit 108.

  Next, the internal configuration of each register in the normal γ register 300 will be described with reference to FIG. The amplitude register 303 is composed of two registers VRP0 to VRP1, and adjusts the amplitude value of the gradation voltage according to register values held in the two registers VRP0 to VRP1. The slope register 304 is composed of two registers SRP0 to SRP1, and adjusts the slope near the center of the gradation number-gradation voltage characteristics by the register values held in the two registers SRP0 to SRP1. . The fine adjustment register 305 includes ten registers PRP0 to PRP9, and finely adjusts the gradation voltage level according to register values held in the ten registers PRP0 to PRP9. Note that the internal configurations of the bright field γ register 301 and the dark field γ register 302 are the same as the internal configurations of the inclination register 304 and the fine adjustment register 305.

  Next, the configuration of the internal block of the positive ladder circuit 109 will be described with reference to FIG. In FIG. 4, 400 to 409 are switches (hereinafter referred to as “SW”), 410 to 421 are fixed resistors, and 422 to 435 are variable resistors. The variable resistor 422 and the variable resistor 435 set resistance values according to the amplitude register value input from the γ adjustment register 105. The variable resistor 428 and the variable resistor 429 set resistance values according to the slope register value input from the γ adjustment register 105. The variable resistors 423 to 427 and the variable resistors 430 to 434 set resistance values according to the fine adjustment register value input from the γ adjustment register 105.

  Note that the minimum value of the resistances of the variable resistors 422 to 435 is set to a resistance value (ideal 0Ω) that does not cause a potential difference between gradations by resistance voltage division. Further, when the SWs 400 to 409 are “ON”, the ON resistances of the SWs 400 to 409 are sufficiently smaller than the fixed resistors 410 to 420. When the SWs 400 to 409 are “OFF”, the OFF resistances of the SWs 400 to 409 are fixed resistors. It is large enough for 410-420.

  When the FBI on-register data is “low” (when the pseudo impulse drive is not used), the SWs 400 to 409 are turned off, and a current flows through the fixed resistors 410 to 414 and the fixed resistors 416 to 420, whereby the resistance of each fixed resistor The reference voltage V0P / V1P / V2P / V4P / V8P / V20P / V43P / V55P / V59P / V61P / V62P / V63P is generated by dividing by the value and the resistance value of each variable resistor.

  V0P is the positive potential of gradation number 0, V1P is the positive potential of gradation number 1, V2P is the positive potential of gradation number 2, and V4P is the positive potential of gradation number 4. V8P is the positive potential of gradation number 8, V20P is the positive potential of gradation number 20, V43P is the positive potential of gradation number 43, V55P is the positive potential of gradation number 55, and V59P is The positive potential of gradation number 59, V61P is the positive potential of gradation number 61, V62P is the positive potential of gradation number 62, and V63P is the positive potential of gradation number 63.

  These 12-level reference voltages are buffered by the buffer circuit 112 and then output to the gradation voltage ladder circuit 113. The gradation voltage ladder circuit 113 divides the resistance based on the 12-level reference voltage, and outputs 64 bits. In the case of gradation display, the remaining gradation number 3, gradation number 5-7, gradation number 9-19, gradation number 21-42, gradation number 44-54, gradation number 56-58, A gradation voltage of gradation number 60 is generated. The gradation number-gradation voltage characteristic at this time is as shown in FIG.

  When the FBI on register data is “high” (when using the pseudo impulse drive) and the γ set value switching signal is “low” (in the dark field), the SWs 400 to 404 are “on”, so the fixed resistors 410 to 414 are connected. No current flows, current flows through SW 400 to 404 and SW 405 to 409 are “off”, so that current flows through fixed resistors 416 to 420. At this time, when the register values of the fine adjustment registers PRP0 to 4 of the dark feel γ register 302 are set to the minimum value of the resistance values of the variable resistors 423 to 427, the potentials of the reference voltages V0P to V20P are not divided. A high voltage VDH from a reference high voltage source (not shown) is output and has the same potential. Note that V43P to V63P do not have the same potential because they are voltage-divided because current flows through the fixed resistors 416 to 420.

  When the FBI on register data is “high” (when using the pseudo impulse drive) and the γ set value switching signal is “high” (during bright field), the SWs 400 to 404 are “off” so that the fixed resistors 410 to 414 are connected. Since the current flows and the SWs 405 to 409 are “ON”, the current flows to the SWs 405 to 409, and no current flows to the fixed resistors 416 to 420. At this time, when the register values of the fine adjustment registers PRP5 to 9 of the bright field γ register 301 are set to the minimum value of the resistance values of the variable resistors 430 to 434, the potentials of the reference voltages V43P to V63P are A low voltage GND from a reference low voltage source (not shown) is output to have the same potential. Note that V0P to V20P do not have the same potential because they are voltage-divided because current flows through the fixed resistors 410 to 414.

  With the above operation, the same voltage can be output in the gradations of V43 to V63 in the bright field and V0 to V20 in the dark field, as in the gradation number-gradation voltage characteristics shown in FIG. It becomes.

  Next, the configuration of the internal block of the negative ladder circuit 110 will be described with reference to FIG. In FIG. 5, 500 to 509 are SWs, 510 to 521 are fixed resistors, and 522 to 535 are variable resistors. Note that the resistance values of the fixed resistors 510 to 521 and the variable resistors 522 to 535 are the same as the resistance values of the fixed resistors 410 to 421 and the variable resistors 422 to 435 of the positive ladder circuit 109.

  The variable resistor 522 and the variable resistor 535 set resistance values according to the amplitude register value input from the γ adjustment register 105. The variable resistance 528 and the variable resistance 529 set resistance values according to the slope register value input from the γ adjustment register 105. The variable resistors 523 to 527 and the variable resistors 530 to 534 set resistance values according to the fine adjustment register value input from the γ adjustment register 105.

  Note that the minimum value of the resistances of the variable resistors 522 to 535 is set to a resistance value (ideal 0Ω) that does not cause a potential difference between gradations by resistance voltage division. Further, when the SWs 500 to 509 are “ON”, the ON resistances of the SWs 500 to 509 are sufficiently smaller than the fixed resistances 510 to 520, and when the SWs 500 to 509 are “OFF”, the OFF resistances of the SWs 500 to 509 are fixed. It is sufficiently larger than the resistors 510 to 520.

  When the FBI on register data is “low” (when the pseudo impulse drive is not used), the SWs 500 to 509 are turned off, and a current flows through the fixed resistors 510 to 514 and the fixed resistors 516 to 520, so that the resistance of each fixed resistor is The voltage is divided by the value and the resistance value of each variable resistor to generate a 12-level reference voltage V0N / V1N / V2N / V4N / V8N / V20N / V43N / V55N / V59N / V61N / V62N / V63N.

  V0N is the negative potential of gradation number 0, V1N is the negative potential of gradation number 1, V2N is the negative potential of gradation number 2, and V4N is the negative potential of gradation number 4. V8N is the negative potential of gradation number 8, V20N is the negative potential of gradation number 20, V43N is the negative potential of gradation number 43, V55N is the negative potential of gradation number 55, and V59N is The negative potential of gradation number 59, V61N is the negative potential of gradation number 61, V62N is the negative potential of gradation number 62, and V63N is the negative potential of gradation number 63.

  These 12-level reference voltages are buffered by the buffer circuit 112 and then output to the gradation voltage ladder circuit 113. The gradation voltage ladder circuit 113 divides the resistance based on the 12-level reference voltage, and outputs 64 bits. In the case of gradation display, the remaining gradation number 3, gradation number 5-7, gradation number 9-19, gradation number 21-42, gradation number 44-54, gradation number 56-58, and floor A gradation voltage of the key number 60 is generated. The gradation number-gradation voltage characteristics at this time are shown in FIG.

  When the FBI on register data is “high” (when using pseudo impulse drive) and the γ set value switching signal is “high” (during bright field), the SWs 500 to 504 are “on”, so the fixed resistors 510 to 514 No current flows, current flows through SW500 to 504, and SW505 to 509 are “off”, so that current flows through fixed resistors 516 to 520. At this time, if the register values of the fine adjustment registers PRP0 to PRP4 in the negative register 107 are set to the minimum values of the resistance values of the variable resistors 523 to 527, the resistance is not divided, so that a 6-level reference is provided. The potentials of the voltages V0N to V20N are the same as the high voltage VDH output from a reference high voltage source (not shown). The other six-level reference voltages V43N to V63N do not have the same potential because they are voltage-divided because current flows through the fixed resistors 516 to 520.

  When the FBI on register data is “high” (when using pseudo impulse drive) and the γ set value switching signal is “low” (during dark field), the SWs 500 to 504 are “off”, so the fixed resistors 510 to 514 Since the current flows and the SWs 505 to 509 are “ON”, the current flows to the SWs 505 to 509, and no current flows to the fixed resistors 516 to 520. At this time, if the register values of the fine adjustment registers PRP5 to 9 of the dark field γ register in the negative register 107 are set to the minimum value of the resistance values of the variable resistors 530 to 534, they are not divided by the resistance, so that the level is 6 levels. The reference voltages V43N to V63N have the same potential as the low voltage GND from the reference low voltage source (not shown) is output. The other six-level reference voltages V0N to V20N do not have the same potential because they are voltage-divided because current flows through the fixed resistors 510 to 514.

  With the above operation, the same voltage can be output in the gradations of V43 to V63 in the bright field and V0 to V20 in the dark field as in the gradation number-gradation voltage characteristic shown in FIG. It becomes.

  In this way, by outputting the grayscale voltages of FIGS. 6B and 6D to the liquid crystal panel 119 shown in FIG. 1, the liquid crystal panel 119 is not limited during the dark field period as shown in FIG. The luminance is low, close to black display, and the liquid crystal panel 119 has high luminance during the bright field period.

  When the display brightness of the liquid crystal panel 119 when the pseudo impulse drive is not used is γ = 2.2, the average brightness of the display brightness of the liquid crystal panel 119 in the dark field and the bright field shown in FIG. 7 is γ = 2. .2 is set, the luminance and hue of the display image on the liquid crystal panel 119 do not change.

  As described above, according to this embodiment, it is possible to realize a driving method for improving moving image blurring without causing a decrease in luminance and contrast with a low-cost configuration that does not use an LUT.

  In this embodiment, the information amount of the display data is 18 bits per pixel, but it is not limited to this. In this embodiment, the potential of the counter electrode applied voltage Vcom is set to 0 V for the positive electrode and 4 V for the negative electrode, but is not limited thereto.

  A drive system for improving the motion blur of the hold type display device according to the second embodiment of the present invention will be described. The signal line drive circuit 101 in this embodiment has the configuration shown in FIG. Further, the gradation voltage generation circuit 108 having the configuration shown in FIG. 1 is provided as in the first embodiment, but the circuit configurations of the positive ladder circuit 109 and the negative ladder circuit 110 are different from those of the first embodiment. The negative ladder circuit 110 has the same circuit configuration and operation as the positive ladder circuit 109.

  Next, the positive ladder circuit 109 in this embodiment will be described with reference to FIG. In FIG. 8, 800 to 810 are SW, 811 to 822 are fixed resistors, and 823 to 836 are variable resistors. The variable resistor 823 and the variable resistor 836 set resistance values according to the amplitude register value input from the γ adjustment register 105. The variable resistor 829 and the variable resistor 830 set resistance values according to the slope register value input from the γ adjustment register 105. The variable resistors 824 to 828 and the variable resistors 831 to 835 set resistance values according to the fine adjustment register value input from the γ adjustment register 105.

  Note that the minimum value of the resistances of the variable resistors 823 to 836 is set to a resistance value (ideal 0Ω) that does not cause a potential difference between gradations due to the resistance voltage division. Further, when SW 800 to 810 is “ON”, the ON resistance of SW 800 to 810 is sufficiently smaller than the fixed resistance 811 to 821, and when SW 800 to 810 is “OFF”, the OFF resistance of SW 800 to 810 is fixed. It is sufficiently larger than the resistors 811 to 821.

  When the FBI on register data is “low” (when pseudo impulse drive is not used), SW 800 to 810 are turned off, and current flows through the fixed resistors 811 to 821, so that the resistance value of each fixed resistor and each variable resistor Divided by the resistance value, 12-level reference voltages V0P / V1P / V2P / V4P / V8P / V20P / V43P / V55P / V59P / V61P / V62P / V63P are generated.

  V0P is the positive potential of gradation number 0, V1P is the positive potential of gradation number 1, V2P is the positive potential of gradation number 2, and V4P is the positive potential of gradation number 4. V8P is the positive potential of gradation number 8, V20P is the positive potential of gradation number 20, V43P is the positive potential of gradation number 43, V55P is the positive potential of gradation number 55, and V59P is The positive potential of gradation number 59, V61P is the positive potential of gradation number 61, V62P is the positive potential of gradation number 62, and V63P is the positive potential of gradation number 63.

  These 12-level reference voltages are buffered by the buffer circuit 112 and then output to the gradation voltage ladder circuit 113. The gradation voltage ladder circuit 113 divides the resistance based on the 12-level reference voltage, and outputs 64 bits. In the case of gradation display, the remaining gradation number 3, gradation number 5-7, gradation number 9-19, gradation number 21-42, gradation number 44-54, gradation number 56-58, A gradation voltage of gradation number 60 is generated. At this time, the reference voltages V0P to V63P do not have the same potential.

  When the FBI on-register data is “high” (when using the pseudo impulse drive), the SWs 800 to 810 are “on”, so that no current flows through the fixed resistors 811 to 821 and current flows through the SWs 800 to 810. At this time, if the register values of the fine adjustment registers PRP0 to 4 and the inclination registers SRP0 to 1 of the dark feel γ register 302 are set to the minimum values of the resistance values of the variable resistors 823 to 830, they are not divided by the resistance. The reference voltages V0P to V43P output the same potential VDH. The other five-level reference voltages V55P to V63P do not flow through the fixed resistors 817 to 821, but are divided by adjusting the variable resistors 832 to 835 according to the settings of the fine adjustment registers PRP6 to P9. Therefore, they are not at the same potential.

  By such an operation, as shown in FIG. 9A, the same low gradation voltage can be output in a wide gradation number range. As shown in FIG. 9B, the negative ladder circuit 110 can output the same high gradation voltage in a wide range of gradation numbers as in the positive ladder circuit 109 of this embodiment. Become.

  As described above, since the luminance of the liquid crystal panel in the dark field period can be brought close to black display as much as compared with the first embodiment, the driving method for improving the motion blur without lowering the luminance or contrast. Is feasible.

  In this embodiment, the potentials V0 to V43 are set to the same potential. However, the present invention is not limited to this, and is the same depending on the set values of the amplitude registers VRP0 to 1, the slope registers SRP0 to 1 and the fine adjustment registers PRP0 to 9. The range of the gradation number for outputting the potential can be arbitrarily set.

  A drive system for improving the motion blur of the hold type display device according to the third embodiment of the present invention will be described. The signal line drive circuit 101 in this embodiment has the configuration shown in FIG. Further, the grayscale voltage generation circuit having the configuration shown in FIG. 1 is provided as in the first embodiment, but the configuration of the internal blocks is different.

  Next, the gradation voltage generation circuit 1000 in this embodiment will be described with reference to FIG. In FIG. 10, 1000 is a gradation voltage generation circuit, reference ladder circuits 1001 to 1004, 1001 is a positive (1) ladder circuit, 1002 is a negative (1) ladder circuit, 1003 is a positive (2) ladder circuit, 1004 is a negative (2) ladder circuit, 1005 is a selection circuit, 1006 is a buffer circuit, and 1007 is a gradation voltage ladder circuit.

  When performing pseudo impulse driving, the γ adjusting register 105 stores the register value held in the bright field γ register of the positive register 106 in the positive (1) ladder circuit 1001 and the bright field γ in the negative register 107. The register value held in the register is stored in the negative (1) ladder circuit 1002, the register value held in the dark field γ register of the positive register 106 is stored in the positive (2) ladder circuit 1003, and the negative register 107. The register value held in the dark field γ register is output to the negative (2) ladder circuit 1004.

  When the pseudo impulse drive is not performed, the γ adjustment register 105 stores the register value held in the normal field γ register of the positive register 106 into the positive (1) ladder circuit 1001 and the negative register 107. The register value held in the normal field γ register is output to the negative (1) ladder circuit 1002.

  These ladder circuits generate a reference voltage corresponding to the input register value and output the reference voltage to the selection circuit 1005. The selection circuit 1005 selects one type of reference voltage from among the four types of reference voltages input from these ladder circuits in accordance with the γ set value switching signal and the AC signal M input from the timing controller, and a buffer Output to the circuit 1006. The buffer circuit 1006 buffers the input reference voltage by the voltage follower circuit and outputs the buffered voltage to the gradation voltage ladder circuit 1007. The gradation voltage ladder circuit 1007 divides the input reference voltage by resistance, generates a gradation voltage of 64 levels, and outputs it to the output control circuit 117.

  As described above, in the case of performing the pseudo impulse driving, it is not necessary to generate the reference voltage according to the light / dark field period by providing four positive / negative ladder circuits corresponding to the light / dark field. Compared with the first embodiment and the second embodiment, it is possible to improve the driving capability of the gradation voltage (reduction of the gradation voltage fluctuation time).

  The circuit configurations of the positive electrode (1) ladder circuit 1001, the negative electrode (1) ladder circuit 1002, the positive electrode (2) ladder circuit 1003, and the negative electrode (2) ladder circuit 1004 in this embodiment are the same as those in the first embodiment. The positive ladder circuit 109 and the negative ladder circuit 110 may be used, or the positive ladder circuit 109 and the negative ladder circuit 110 according to the second embodiment may be used.

Configuration diagram of peripheral circuit of liquid crystal panel in the present invention Configuration diagram and timing chart of timing controller in the present invention Configuration of γ adjustment register in the present invention FIG. 1 is a configuration diagram of a positive ladder circuit according to a first embodiment of the present invention. 1 is a configuration diagram of a negative-side ladder circuit according to a first embodiment of the present invention. FIG. 6 is a relationship diagram of gradation number-gradation voltage characteristics in the first embodiment of the present invention. Relationship diagram of γ characteristics of Example 1 in the present invention Configuration diagram of ladder circuit for positive electrode of embodiment 2 in the present invention FIG. 6 is a relationship diagram of gradation number-gradation voltage characteristics in the second embodiment of the present invention. Configuration diagram of a gradation voltage generation circuit according to a third embodiment of the present invention. Relationship diagram between gradation number and gradation voltage characteristics when performing pseudo impulse drive in LUT method and current method

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... Signal line drive circuit, 102 ... System interface, 103 ... Control register, 104 ... Timing controller, 105 ... Gamma adjustment register, 106 ... Positive register, 107 ... Negative register, 108 ... Gradation voltage Generation circuit 109... Positive ladder circuit 110 110 Negative ladder circuit 111 Selection circuit 112 Buffer circuit 113 Gradation voltage ladder circuit 114 Memory control circuit 115 Display RAM 116 Latch Circuit 117, output control circuit 118, scanning line drive circuit, 119 ... liquid crystal panel, 120 ... scanning line, 121 ... signal line, 122 ... TFT, 123 ... liquid crystal element, 200 ... register, 201 ... internal clock generation circuit, 202 ... Clock counter, 203 ... Horizontal synchronization signal generation circuit, 204 ... AC signal Generation circuit, 205 ... line counter, 206 ... vertical synchronization signal generation circuit, 207 ... γ set value switching signal generation circuit, 208 ... odd / even frame signal generation circuit, 300 ... normal γ register, 301 ... bright field γ register, 302 ... dark Field γ register, 303 ... Amplitude register, 304, 306, 308 ... Slope register, 305, 307, 309 ... Fine adjustment register, 310, 311 ... Select circuit, 400-409 ... SW, 410-421 ... Fixed resistor, 422 435 ... variable resistance, 500-509 ... SW, 510-521 ... fixed resistance, 522-535 ... variable resistance, 800-810 ... SW, 811-822 ... fixed resistance, 823-836 ... variable resistance, 1000 ... gradation voltage Generation circuit, 1001... Ladder circuit for positive electrode (1), 1002... Ladder circuit for negative electrode (1), 1003. Pole (2) ladder circuit, 1004 ... ladder circuit negative electrode (2), 1005 ... selection circuit, 1006 ... buffer circuit, 1007 ... gradation voltage ladder circuit

Claims (6)

A display panel having a plurality of pixels and a drive circuit for driving the display panel;
The drive circuit is
A register for storing a setting value for generating and outputting a gradation voltage corresponding to display data input from an external system;
A reference ladder circuit that generates a reference voltage according to the set value;
A buffer circuit for buffering and outputting the reference voltage;
A gradation voltage ladder circuit for generating a gradation voltage based on the reference voltage;
An output control circuit that selects and outputs a gradation voltage corresponding to display data from the gradation voltage;
The reference ladder circuit includes a fixed resistor and a variable resistor whose resistance value is controlled by the set value, and the fixed resistor includes a switch ,
In the first case where the luminance corresponding to the display data is displayed in one frame period, the driving circuit divides one frame period into fields, and one of the divided fields is a dark field for low luminance display, and the other is As a bright field for high luminance display, the second case for displaying the luminance corresponding to the display data with the average luminance of the dark field and the bright field is switched by a control signal input from an external system,
The register stores a first register for storing a setting value for generating a gradation voltage corresponding to the first case, and a setting value for generating a gradation voltage corresponding to the bright field. A second register and a third register for storing a setting value for generating a gradation voltage corresponding to the dark field;
In the first case, the reference ladder circuit is controlled by a first register;
In the second case, the reference ladder circuit is controlled by a second register in a bright field and controlled by a third register in a dark field . In claim 1,
The reference ladder circuit is
In series between the reference high voltage source and the reference low voltage source,
A first variable resistor, a first fixed resistor and a first switch connected in parallel;
A second variable resistor, a second fixed resistor and a second switch connected in parallel;
A third variable resistor, a third fixed resistor and a third switch connected in parallel;
A fourth variable resistor, a fourth fixed resistor and a fourth switch connected in parallel;
A fifth variable resistor, a fifth fixed resistor and a fifth switch connected in parallel;
Sixth and seventh variable resistors, a sixth fixed resistor,
An eighth variable resistor;
A ninth variable resistor, a seventh fixed resistor and a sixth switch connected in parallel;
A tenth variable resistor, an eighth fixed resistor and a seventh switch connected in parallel;
An eleventh variable resistor, a ninth fixed resistor and an eighth switch connected in parallel;
A twelfth variable resistor, a tenth fixed resistor and a ninth switch connected in parallel;
A thirteenth variable resistor, an eleventh fixed resistor and a tenth switch connected in parallel;
A fourteenth variable resistor and a twelfth fixed resistor;
Generating a first reference voltage from a connection point between the first variable resistor and the first fixed resistor;
Generating a second reference voltage from a connection point between the second variable resistor and the second fixed resistor;
A third reference voltage is generated from a connection point between the third variable resistor and the third fixed resistor;
A fourth reference voltage is generated from a connection point between the fourth variable resistor and the fourth fixed resistor;
A fifth reference voltage is generated from a connection point between the fifth variable resistor and the fifth fixed resistor;
A sixth reference voltage is generated from a connection point between the sixth variable resistor and the seventh variable resistor;
A seventh reference voltage is generated from a connection point between the eighth variable resistor and the ninth variable resistor;
An eighth reference voltage is generated from a connection point between the seventh fixed resistor and the tenth variable resistor,
A ninth reference voltage is generated from a connection point of the eighth fixed resistor and the eleventh variable resistor;
A tenth reference voltage is generated from a connection point of the ninth fixed resistor and the twelfth variable resistor;
An eleventh reference voltage is generated from a connection point between the tenth fixed resistor and the thirteenth variable resistor,
Display device and generates the twelfth reference voltage from the eleventh fixed resistor and the fourteenth connection point of the variable resistor of the. In claim 2,
The drive circuit is
In the dark field (or bright field), the first to fifth switches are short-circuited, and the second to sixth variable resistors are set to zero, whereby the first to fifth reference voltages are set. Approximately equal,
In the bright field (or dark field), the sixth to tenth switches are short-circuited, and the ninth to thirteenth variable resistors are set to zero, whereby the seventh to twelfth reference voltages are set. A display device characterized by being substantially equal. In claim 1,
The reference ladder circuit is
In series between the reference high voltage source and the reference low voltage source,
A first variable resistor, a first fixed resistor and a first switch connected in parallel;
A second variable resistor, a second fixed resistor and a second switch connected in parallel;
A third variable resistor, a third fixed resistor and a third switch connected in parallel;
A fourth variable resistor, a fourth fixed resistor and a fourth switch connected in parallel;
A fifth variable resistor, a fifth fixed resistor and a fifth switch connected in parallel;
A sixth variable resistor;
A seventh variable resistor, a sixth fixed resistor and a sixth switch connected in parallel;
An eighth variable resistor;
A ninth variable resistor, a seventh fixed resistor and a seventh switch connected in parallel;
A tenth variable resistor, an eighth fixed resistor and an eighth switch connected in parallel;
An eleventh variable resistor, a ninth fixed resistor and a ninth switch connected in parallel;
A twelfth variable resistor, a tenth fixed resistor and a tenth switch connected in parallel;
A thirteenth variable resistor, an eleventh fixed resistor and an eleventh switch connected in parallel;
A fourteenth variable resistor and a twelfth fixed resistor;
Generating a first reference voltage from a connection point between the first variable resistor and the first fixed resistor;
Generating a second reference voltage from a connection point between the second variable resistor and the second fixed resistor;
A third reference voltage is generated from a connection point between the third variable resistor and the third fixed resistor;
A fourth reference voltage is generated from a connection point between the fourth variable resistor and the fourth fixed resistor;
A fifth reference voltage is generated from a connection point between the fifth variable resistor and the fifth fixed resistor;
A sixth reference voltage is generated from a connection point between the sixth variable resistor and the seventh variable resistor;
A seventh reference voltage is generated from a connection point between the eighth variable resistor and the ninth variable resistor;
An eighth reference voltage is generated from a connection point between the seventh fixed resistor and the tenth variable resistor,
A ninth reference voltage is generated from a connection point of the eighth fixed resistor and the eleventh variable resistor;
A tenth reference voltage is generated from a connection point of the ninth fixed resistor and the twelfth variable resistor;
An eleventh reference voltage is generated from a connection point between the tenth fixed resistor and the thirteenth variable resistor,
Display device and generates the twelfth reference voltage from the eleventh fixed resistor and the fourteenth connection point of the variable resistor of the In claim 4,
The drive circuit is
The first to eleventh switches are short-circuited,
In the dark field, the first to seventh reference voltages are made substantially equal, and the resistance values of the tenth to thirteenth variable resistors are controlled based on a set value from the third register, The display device characterized in that the eighth to twelfth reference voltages are different. In claim 1,
The reference ladder circuit is
A positive ladder circuit for generating a positive gradation voltage for a bright field;
A negative ladder circuit for generating a negative gradation voltage for a bright field;
A positive ladder circuit for generating a positive gradation voltage for a dark field;
A negative ladder circuit for generating a negative gradation voltage for a dark field,
In the first case, a positive voltage ladder circuit and a negative polarity ladder circuit for a bright field (or dark field) are used to generate a reference voltage,
The second case, in the light field (or dark field), using a positive electrode (or negative electrode) ladder circuit in response to the positive polarity (or negative polarity), and generates a reference voltage Liquid crystal display device.

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