JP4220484B2 - Integrated circuit resistor array - Google Patents

Description

  The present invention relates generally to integrated circuit resistor arrays used to construct a number of resistors that affect the voltage dependence of a given parameter, such as the gain of an analog integrated circuit, and more particularly to digital-to-analog. The present invention relates to a resistor array suitable for use as such a large number of resistors in an analog integrated circuit requiring high performance such as a summing amplifier in a converter.

Conventional technology

  A conventional oversampling multi-bit digital-to-analog converter (DAC), for example, the DAC of model number PCM1710 manufactured by the present applicant, generally includes a noise shaper that oversamples a digital input, It consists of a plurality of CMOS inverters that are switched to high or low in response to an oversampled multi-bit digital modulation output and a summing amplifier that combines the outputs of these inverters to generate an analog output. Further, the summing amplifier has a plurality of conversion resistors (that is, unit load resistors having equal weights) connected to the outputs of the inverters, and terminals on the opposite side of the inverter outputs of the conversion resistors. It has a configuration including a connected CR filter and a differential instrumentation amplifier connected to the output of the filter.

  In the integrated circuit of DAC of model number PCM1710, a first resistor group including a conversion resistor in the summing amplifier and a filter resistor of the CR filter, and a second resistor including an input resistor and a feedback resistor of the instrumentation amplifier are provided. The resistor groups are formed by polysilicon resistors laid out in appropriate locations near the circuits to which each group is related, and thus in first and second regions that are separated from each other. In the present specification, the “polysilicon resistor” includes not only a resistor made of only a polysilicon material but also a resistor of a polycide structure.

  The polysilicon resistor in each region is composed of comb-shaped stripes. The comb configuration consists of a plurality of long comb-tooth polysilicon stripe portions and a short connecting polysilicon stripe portion connecting one end of the comb-tooth portion to one end of the other comb-tooth portion. The short connection portion extends in a direction perpendicular to the comb portion. In each of the first and second regions, the comb portion and the connecting portion have the same thickness, width, and length. However, the width, that is, the cross-sectional area of the stripe is different between the first region and the second region. In the first region and the second region, the comb portions are arranged orthogonal to each other. Further, since the required resistance value of the resistor is determined by the total length of the comb-shaped stripes obtained by connecting the comb teeth portions adjacent to each other in the connection stripe portion, the different resistance values in the same region are: This is realized by connecting different numbers of comb stripe portions in series at connecting stripe portions.

  The above polysilicon resistors are superior to metal thin film resistors such as silicon chrome / nichrome from the viewpoint of process contamination and process consistency in submicron integrated circuit technology, but the voltage dependency (or voltage coefficient) of the resistance value. However, there is a problem that it is higher than the metal thin film resistance. Further, as shown in FIG. 5, the polysilicon resistance has a characteristic that the voltage coefficient becomes lower as the width (however, the same thickness) becomes narrower, and thus the cross-sectional area becomes smaller.

  Furthermore, in the integrated circuit process technology, particularly etching processing of polysilicon or the like, there is a problem that the etching rate changes depending on the location, direction, and etching area on the chip. Therefore, if an attempt is made to form and process polysilicon resistors having the same width in different locations, directions, or etching areas, the widths differ as a result, resulting in polysilicon resistors having different voltage dependencies. As a result, the parameter of the summing amplifier, for example, the gain also has a voltage dependency having a magnitude corresponding to the voltage dependency of the polysilicon resistance. This affects the analog characteristics such as linearity and dynamic range in terms of the characteristics of the entire DAC.

The above problem applies not only to analog integrated circuits such as DAC summing amplifiers, but also to analog integrated circuits of other devices.
Accordingly, it is an object of the present invention to provide an integrated circuit resistor array suitable for use as a resistor for high performance analog integrated circuits.

Another object of the present invention is to provide an integrated circuit resistor array that can be used to minimize the voltage dependence of certain parameters, such as the gain of an analog integrated circuit.
Yet another object of the present invention is to provide a summing amplifier for a digital-to-analog converter constructed using the integrated circuit resistor array described above.

  To achieve the above object, according to the present invention, an analog integrated circuit formed on an integrated circuit substrate has a plurality of resistors in the analog integrated circuit that affect the voltage dependence of predetermined parameters of the analog integrated circuit. An integrated circuit resistor array for constructing (a) is a plurality of resistor elements separated from one another, which are collectively arranged in one region on the substrate, and are formed of the same material and have a cross-sectional shape A plurality of resistor elements comprising a plurality of stripes having the same area; and b) conductor means for forming the plurality of resistors by electrically connecting the plurality of resistor elements; It comprises so that it may be provided.

  According to the present invention, the plurality of stripes can have the same width, can be arranged close to each other in the one region, and extend parallel to each other in the same direction. It can also be arranged. The conductor means may form each of the plurality of resistors by using at least two resistor elements. Furthermore, each of the plurality of resistor elements can have a resistance value lower than the resistance value of the smallest resistor of the plurality of resistors.

  According to the present invention, the plurality of resistors may include a plurality of resistor groups, and each resistor group may be composed of a plurality of resistors that should have resistance values matched to each other. In this case, each of the resistor groups can be composed of resistor elements adjacent to each other in one section in the one region. A) the one area is composed of a plurality of sub-areas adjacent to each other; and b) the conductor means is configured to connect each of the plurality of resistors in each of the resistor groups to the plurality of the one area. At least one of the plurality of resistor elements in each of the sub-areas may be selected and formed. Alternatively, a) the one area is a first area composed of a plurality of sub-areas including non-adjacent sub-areas; and b) the conductor means includes a plurality of sub-areas in each resistor group. Each of the resistors may be formed by selecting at least one of a plurality of resistor elements in each sub-section of the plurality of sub-sections of the first section. In this case, a) the plurality of resistor groups include a first resistor group and a second resistor group that should have resistance values matched to each other, and b) the one area different from the first area. And the second area includes at least one sub-area located between the two non-adjacent sub-areas of the first area, and c) the first resistor group is formed in the first area. The second resistor group may be formed in the second area.

  According to the present invention, the resistor element may be a polysilicon resistor or a diffused resistor. The analog integrated circuit may be a circuit including at least one operational amplifier. Furthermore, the predetermined parameter may be a gain of the analog integrated circuit.

  In order to achieve the above object, according to the present invention, a summing amplifier including a plurality of load resistors and an operational amplifier including at least one input resistor and at least one feedback resistor includes the plurality of load resistors. The load resistor, the input resistor, and the feedback resistor are formed by the integrated circuit resistor array.

  According to the present invention, a) the summing amplifier further includes a CR filter having a filter resistor, and b) the filter resistor is also formed by the integrated circuit resistor array. The summing amplifier can be used in an oversampling digital-analog converter.

BEST MODE FOR CARRYING OUT THE INVENTION

  Next, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, an example in which the integrated circuit resistor array of the present invention is used as an oversampling multi-bit digital-analog converter (DAC) summing amplifier for audio will be described.

  First, referring to FIGS. 1 to 3, FIG. 1 shows a circuit layout diagram on the IC chip 2 of the oversampling digital-analog converter (DAC) 1, and FIG. FIG. 3 is a plan view showing a layout of an embodiment of the integrated circuit resistor array 4 used in the summing amplifier 3.

  As shown in FIG. 1, the IC chip 2 of the DAC 1 has a digital circuit region 20 and an analog circuit region 22, and the analog circuit region 22 is a circuit for an L channel (ch) and an R channel (ch). It is divided into regions 22L and 22R. Each of the regions 22L and 22R has a substantially square resistor array region 220L, 220R (the size of the square region is approximately 200 μm × 200 μm) provided with the integrated circuit resistor array 4 according to the present invention. A summing amplifier 3 is located.

  As shown in FIG. 2, the summing amplifier 3 is roughly divided into a conversion resistor unit 30, a CR filter unit 32, and a differential buffer unit 34. Since the DAC 1 is a differential type, the conversion resistor unit 30 has four conversions on the positive phase side, one end of which is connected to receive the outputs IN0 to IN3 of four positive phase CMOS inverters (not shown). Resistors R1 to R4 and respective outputs IN0￣ to IN3￣ of four CMOS inverters (not shown) on the opposite phase side (where symbol “￣” indicates inversion of the logic signal represented by the preceding symbol) And four conversion resistors R5 to R8 on the opposite phase side, one end of which is connected to receive. All of the conversion resistors R1 to R8 have the same resistance value, that is, 42 KΩ, in order to perform unit weighting equally. The other ends of the positive phase side resistors R1 to R4 are connected to the junction point J1, and the other ends of the negative phase side resistors R5 to R8 are connected to the junction point J2.

  Next, the CR filter unit 32 is connected between the junction points J1 and J2, and is combined with the resistors R1 to R8 to form a differential low-pass filter, and between the junction point J1 and the ground GND. Are connected in series to form a low-pass filter, a resistor R9 and a capacitor C3, and are connected in series between a junction J2 and a ground GND to form a low-pass filter, a resistor R11 and a capacitor C4, and a junction J3 (resistor The junction is connected between the junction R4 and the capacitor C3) and the junction J4 (the junction between the resistor R11 and the capacitor C4) and is combined with the resistors R9 and R11 to form a differential low-pass filter. And capacitor C2. Resistors R9 and R11 are each 21 KΩ, capacitors C1 and C2 are 47.4 pF, and C3 and C4 are 4.74 pF.

  The next differential buffer unit 34 includes first and second inversion buffers IBF1 and IBF2, and the first inversion buffer IBF1 includes an operational amplifier (also referred to as an operational amplifier) OPA1 and an antiphase input terminal thereof. And the junction resistor J4, the input resistor R12 connected between the negative phase input terminal and the operational amplifier output terminal R13, and the operational amplifier output terminal and the junction J5. Output resistor R14. The positive phase input terminal of the operational amplifier OPA1 is connected to the junction J6 between the resistors R16 and R17, and the other end of R17 is connected to the power supply terminal VCC and the other end of R16 is connected to the ground GND. . Junction point J6 is connected to terminal DCC, which is for connection to the positive phase input terminal of the operational amplifier (see FIG. 3). The second inverting buffer IBF2 includes an operational amplifier OPA2 having a negative phase input terminal connected to the junction point J5 and a positive phase input terminal connected to the junction point J6, and an input resistor R10 connected between the junction points J3 and J5. A feedback resistor R15 connected between the negative phase input terminal and the output terminal of the operational amplifier OPA2. The output terminal of the operational amplifier OPA2 is connected to the voltage output terminal VOUT of the summing amplifier 3. Resistors R10, R12, R15-R17 are 21 KΩ, and R13 and R14 are 42 KΩ. VCC is 5 volts.

  FIG. 4 is a diagram showing an equivalent circuit of the summing amplifier 3 in FIG. 2, and is simplified by focusing on the resistances (a) → (b) → (c). In the figure, Vin is a voltage source that collectively represents the inverter outputs IN0 to IN3, and Vin * is a voltage source that collectively represents IN0 to IN3. R is a unit resistance of 21 KΩ, which represents R1 to R17. As can be seen from FIG. 4A, each of the resistors R1 to R4 and R5 to R8 is (1/2) R because of four parallel connections of 2R. In FIG. 4B, the positive-phase side including Vin supplies (2 / 5R) Vin current to the negative-phase input terminal of the operational amplifier OPA2, and includes Vin * and the first inversion buffer IBF1. Since the negative phase side supplies a current of-(2 / 5R) Vin *, (2 / 5R) Vin- (2 / 5R) Vin * = (4 / 5R) Vin, and accordingly, FIG. As shown, the input circuit to the negative phase input terminal of the operational amplifier OPA2 is equivalently connected in series with Vin and (5/4) R.

  As can be seen from FIG. 4C, when the input resistance is Rin and the feedback resistance is Rf, the voltage gain G of the summing amplifier 3 is G = −Rf / Rin, which is −R / {(5 / 4) R} = − 4/5. Therefore, theoretically, the analog output voltage Vout = − (4/5) Vin. However, when implemented by polysilicon resistors, Rin and Rf actually have significant voltage dependencies, and therefore, the summing amplifier indicates that the voltage dependency of Rin and the voltage dependency of Rf are matched to each other. In order to minimize the voltage dependence of the gain G of the DAC 3, it is important to improve the analog characteristics of the DAC 3.

  FIG. 5 is a graph showing the voltage dependence of the polysilicon resistance, the horizontal axis is the magnitude of the voltage applied to both ends of the polysilicon resistance, and the vertical axis (logarithmic scale) is the resistance value of the polysilicon resistance. The voltage coefficient of VOLTCO (ppm / V). The curve with rhombus marks is for a single stripe with a width of 25 μm and a length of 100 μm, and the curve with a rectangle mark is a multiple stripe form consisting of 5 stripes with a width of 5 μm and a length of 100 μm connected in parallel And the curve with triangular marks is of a single stripe with a width of 3 μm and a length of 100 μm. However, each stripe is the same thickness of 5000 angstroms. As can be seen, the voltage coefficient increases as the applied voltage increases, and the voltage coefficient decreases as the width of the polysilicon resistor decreases, i.e., as the cross-sectional area decreases. For this reason, when a large number of polysilicon resistors are used, it is preferable to form them with the same width (or cross-sectional area) as much as possible and to apply the same voltage as much as possible in order to maximize the voltage coefficients of each other.

  In the present invention, in order to minimize the voltage dependency of the gain G of the summing amplifier 3 in FIG. 2, the equivalent input resistance Rin and the feedback resistance Rf of the operational amplifier OPA2 are set as described above by devising the circuit configuration. By setting the ratio to 5/4: 1, the equivalent input resistance Rin connected between the voltage source Vin and the virtual ground and the feedback resistance Rf connected between the virtual ground and the output voltage are almost equal. The same voltage is constantly applied. In addition to this, the integrated circuit resistor array 4 shown in FIG. 3 is used as a resistor of the summing amplifier 3.

  Next, the integrated circuit resistor array 4 will be described with reference to FIGS. 3, 6 and 7. 6 is a cross-sectional view taken along line VI-VI in FIG. 3, and FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. The resistor array 4 is provided in one of the array regions 220L and 220R in FIG. 1, for example, a substantially square region 220L. First, the horizontal structure of the array 4 will be described. As can be seen from FIGS. 3 and 6, 100 straight polysilicon lines extending in parallel with each other in the N + active region 41 in the N well region 40. Layer stripes 42 are included (two at each end are not used). Also, as shown in FIG. 6, the array 4 includes an aluminum first metal layer 43a having a substantially U-shaped planar shape, and an end portion of the first metal layer 43a and the stripe for interconnecting the stripes 42. And a contact 44 made of a tungsten plug for connecting the end of 42. Also, as shown in FIG. 7, the array 4 has stripes 42 arranged on external circuits, that is, outputs IV0 to IV3 and IV0 to IV3 in FIG. 2, junction points J1 to J4, terminals DCC, and outputs of operational amplifiers OPA1 and OPA2. The second metal layer 45 of aluminum, the end of the second metal layer 45, and the first metal layer 43b are connected to the terminal and the negative-phase input terminal, the bias terminals of both the operational amplifiers, the terminal VCC, and the ground GND. And vias 46 made of tungsten plugs for connecting the ends of the two. The other end of the first metal layer 43 b is connected to the end of the stripe 42 by a contact 44.

  The stripes 42 are all designed to have the same width (e.g., 1.4 [mu] m), length (e.g., 200 [mu] m) and thickness (e.g., 1500 angstroms) and thus have the same cross-sectional area, And it is designed so as to be separated from adjacent stripes at the same interval (eg, 0.6 μm). On each stripe, symbols “R1” to “R17” are attached, and the stripe used for each of the resistors R1 to R17 in the circuit of FIG. 2 is shown. Each stripe has a resistance value of 7 KΩ, and thus resistors R1 to R8 and R13 and R14 (each 42 KΩ) use six stripes connected in series, and resistors R9 to R12, R16 and R17 ( Each 21 KΩ) uses a series connection of three stripes. On the other hand, the resistor R15 (21 KΩ) uses 12 stripes, and each of the 6 resistors in series (each 42 KΩ) is connected in parallel. In addition, the six stripes at the right end of the array 4 are not shown in the circuit of FIG. 2, but are used for the resistor R1 (OPA1) inside the operational amplifier OPA1 and the resistor R1 (OPA2) inside the operational amplifier OPA2. To do.

  Next, the vertical structure of the array 4 will be described with reference to FIGS. 6 and 7. The array 4 includes, in order from the bottom, the silicon substrate 2200 of the IC chip 2, the diffusion layer 2202 defining the N well 40, A first insulator layer 2204; a second insulator layer 2206 in which the polysilicon layer 42 and the contact 44 are embedded; a third insulator layer 2208 in which the first metal layers 43a and 43b and the via 46 are embedded; And a second metal layer 45 provided on the insulator layer.

Next, referring to FIG. 8, a method of averaging the resistance value for each stripe in the resistor array 4 of the summing amplifier 3 and the variation of the voltage coefficient thereof will be described.
First, as can be seen from the circuit configuration of the summing amplifier 3 in FIG. 2, the group of resistors whose resistance values and their voltage coefficients should be matched to each other is
R1-R8 conversion resistor group RG1,
R9 and R11 filter resistor group RG2,
R10 and R12 operational amplifier input resistor group RG3,
Op-amp feedback / output resistor group RG4 of R13 to R15,
Operational amplifier resistor group RG5 of R10, R12 to R15,
R16 and R17 resistor group RG6,
It is.

Therefore, as shown in FIG. 8, the region SR of 90 stripes 42 for the resistors R1 to R17 in FIG.
Area A1, for resistor group RG1 (R1-R8),
Area A2 for resistor group RG2 (R9, R11),
Separate area A3 for resistor group RG3 (R10, R12),
Section A4 for resistor group RG4 (R13-R15),
Area A5 for resistor group RG6 (R16, R17),
It is divided into. Furthermore, area A1 is divided into six adjacent subareas A1S1 to A1S6, and each subarea includes eight adjacent stripes, each one being assigned to each one of R1 to R8, And each of R1 to R8 is constituted by connecting each one of each sub-section in series. As a result, the influence of variations among stripes is minimized by averaging.

  Similarly, the area A2 is divided into three sub-areas A2S1 to A2S3 adjacent to each other, each sub-area includes two stripes, and each of the sub-areas is connected in series to connect each of R9 and R11. Is configured. Area A3 consists of two adjacent sub-areas A3S1, A3S2 and one non-adjacent sub-area A3S3 away from each other, each sub-area including two stripes. Each of these sub-areas is connected in series to constitute each of R10 and R12. The area A4 is composed of six sub-areas A4S1 to A4S6 adjacent to each other in the area A3, and each area includes four stripes, and each of the sub-areas is connected in series to form R13. And R14, on the other hand, two sub-sections connected in parallel are connected in series to form R15. By arranging the area A4 in the area A3, the consistency of the resistor group RG5 is enhanced. Further, by increasing the number of stripes (= 12) used as R15 (functioning as the feedback resistor Rf in FIG. 4C), an equivalent input resistance (FIG. 4C) composed of the other resistors R1 to R14 is increased. And the equivalent input resistance Rin shown in FIG. Finally, area A5 consists of three adjacent sub-areas A5S1 to A5S3, which sub-areas contain two stripes, and each one of each sub-area is connected in series to each of R16, R17 Is configured.

  In the summing amplifier 3 having the resistor array 4 described above, the voltage dependency of the voltage gain is lowered, so that in the DAC 1 using the summing amplifier 3, compared to the conventional DAC of the same type, There was a significant improvement in the dynamic range of the DAC. As an example, the dynamic range has increased by approximately 4 dB from 92 dB (conventional) to 96 dB (invention). This 4 dB is a considerably large value as an improvement in the vicinity of 100 dB.

Next, with reference to FIGS. 9 to 12, various modifications to the above-described embodiment will be described.
First, as shown in FIG. 9, the shape of the region in which the resistor array 4 is provided can be changed as necessary in circuit design. 9A is a substantially square region 220a as shown in FIG. 9A, but as another example, for example, as shown in FIGS. 9B, 9C, and 9D. In addition, the L-shaped region 220b, the horizontally long rectangular region 220c, and the vertically long rectangular region 220d can be formed in such a manner that resistance stripes such as the stripes 42 can be collectively arranged in such regions. In the example shown in FIG. 9, the resistance stripe groups 42a, 42b, 42c, and 42d provided in the same region have the same stripe extending direction, and the stripe aspect ratio (length to width). Are the same. Such a change in the region shape also produces the same effect as the resistor array of the first embodiment.

  FIG. 10 shows, as an example, a modification example in which two or more different directions are provided as extending directions of stripes provided in the same region. However, the aspect ratios of the stripes in the same region are the same. Specifically, the square region 220a ′ in FIG. 10A has a stripe group 42a ′ composed of a group of stripes whose extending direction is the vertical direction and two groups of stripes whose extending direction is the horizontal direction. The L-shaped region 220b ′ in FIG. 10B has one stripe group 42b ′ in the vertical direction and the horizontal direction. The stripe group 42c 'in the rectangular region 220c' in FIG. 10C is the same as that in FIG. 10B except that the number of stripes in the vertical direction is reduced. Even if such a change is made, the same effect as in the first embodiment can be obtained except for the effect obtained by making the extending direction of all stripes the same (that is, the contribution to uniform stripe width). be able to.

  FIG. 11 shows, as an example, a modification in which stripes having different values of two or more as the aspect ratio of the stripe (however, the width is constant) are arranged in addition to the modification in which the extending direction in FIG. 10 is not the same. It is shown. That is, the stripe group 42a '' of the square region 220a '' shown in FIG. 11A has an aspect ratio, that is, one group has a higher aspect ratio than the other two groups among the three groups of stripes whose extending direction is the vertical direction. The length is large. The stripe group 42a ′ ″ of the square region 220a ′ ″ in FIG. 11B is different from FIG. 11A in that the two groups of stripes having a small aspect ratio are different from each other in the vertical and horizontal directions. It is in the extending direction. In the stripe group 42b ″ of the L-shaped region 220b ″ shown in FIG. 11C, the aspect ratio of the stripe group whose horizontal direction extends is smaller than that of the stripe group whose vertical direction extends. Even if such a change is made, the effects obtained by making the extending direction of all the stripes the same and the effects obtained by making the aspect ratios of all the stripes the same (that is, contribution to uniform stripe width) are excluded. The same effects as those in the first embodiment can be obtained.

  Furthermore, in the above-described one embodiment, the use of a polysilicon resistor as the resistor stripe has been described. However, other types or materials of integrated circuit resistors having a voltage dependency, for example, diffused resistors may be used. An integrated circuit resistor of a type or material in which the voltage coefficient of the resistance value is related to the cross-sectional area of the stripe can also be used for the resistor array of the present invention.

  Next, a modification example of the averaging method by dividing the region into a plurality of sections will be described with reference to FIG. In the first embodiment, the matching in the resistor group RG5, that is, the matching between the input resistor group RG3 (resistors R10, R12) and the feedback / output resistor group RG4 (resistors R13 to R15) is separated. This is done by arranging the area A4 in a non-separated area A3 consisting of the sub-areas. However, if it is desired to provide the resistor group RG3 and the resistor group RG4 with higher matching, the sub-zones of the two zones can be changed to be alternately arranged. As an example, as shown in FIG. 12, areas A3 and A4 are made A3 'and A4'. That is, the sub-areas A3S1 ′ to A3S3 ′ of the area A3 ′ are all separated from each other, and a half of the sub-areas A4S1 ′ to A4S6 ′ of the area A4, that is, A4S1 ′ to A3S2 ′. A4S3 ′ is placed, and the other half, A4S4 ′ to A4S6 ′, is placed between sub-areas A3S2 ′ and A3S3 ′. With such a staggered arrangement, a higher averaging effect between the plurality of resistor groups can be obtained.

  In addition, as an averaging method using the stripe allocation method in the sub-areas, in the above-described embodiment, the stripes are assigned to the resistors in a “folded” format for each sub-area. For example, in the sub-areas A1S1 to A1S6, as can be seen from FIG. 3, R8-R7 -...- R2-R1-R1-R2 ...- R7-R8-R8-R7. Assigned. As shown in FIG. 6, this assignment method is advantageous because the interconnection between stripes can be completed using a plurality of U-shaped first metal layers 43a arranged as the same layer. However, when it is desired to further increase the averaging effect), a non-folding type, for example, R8-R7 -...- R2-R1-R8-R7 ...- R2-R1-R8-R7 ... You may make it allocate in the condition.

  Furthermore, in the above-described one embodiment, the electrical connection form between the stripes is only series connection or series connection of parallel connection, but any combination of electrical connection methods is possible.

  In the first embodiment, the circuit of the summing amplifier 3 uses two inverting buffers. However, it can be changed to a circuit configuration using a differential instrumentation amplifier. Further, since the DAC 1 is a differential type, the summing amplifier 3 is also a differential type. However, when the DAC 1 is a non-differential type or may be a non-differential type depending on the application. The present invention is also applicable to other types of DACs including summing amplifiers. Even in such a case, if the resistor array of the present invention is used, the same effect as described above can be obtained.

  Furthermore, the resistor array of the present invention can be applied to any other analog integrated circuit as long as the circuit parameters are affected by the voltage dependence of the resistors in the circuit. For example, operational amplifiers or various circuits including amplifiers. In addition, as a circuit parameter, there are a voltage gain, a current gain, and other arbitrary parameters representing circuit characteristics such as linearity.

Finally, in summary, in the resistor array of the present invention, in order to reduce the voltage dependency difference between the plurality of resistance stripes, the collective arrangement in the same region, the same material of the resistance stripe, the same cross-sectional area of the stripe, The element of is important. Furthermore, in order to achieve the same cross-sectional area, the same extending direction and proximity of stripes are preferable. This proximity arrangement is also effective in minimizing changes due to the stress in the resistivity of each stripe (on the chip during packaging). Also, the same stripe length is effective for enhancing the averaging effect. Next, in order to minimize the difference in voltage dependency between a plurality of resistors, it is effective to arrange the resistors close to each other and require averaging that require high matching. Next, in order to reduce the voltage dependency of a predetermined parameter of an analog circuit, when there are a plurality of resistor groups, it is effective to dispose resistor groups that require high matching close to each other. .
[The invention's effect]

  According to the present invention described in detail above, it is possible to reduce the voltage dependency of a predetermined parameter of the analog integrated circuit, and therefore, it can be effectively used to improve the performance and accuracy of the analog integrated circuit.

It is a figure which shows the circuit arrangement | positioning on the IC chip of an oversampling type digital-analog converter (DAC), and has shown the arrangement position of the integrated circuit resistor array of this invention. The circuit diagram which shows the circuit of the addition amplifier using the resistor array of this invention contained in DAC of FIG. The top view which shows the layout about one Embodiment of the integrated circuit resistor array of this invention used for the addition amplifier of FIG. FIG. 3 is a circuit diagram showing an equivalent circuit of the summing amplifier of FIG. 2, and is a simplified diagram focusing on resistance in the order of (a) → (b) → (c). FIG. 5 is a graph showing the voltage dependence of the polysilicon resistance, the horizontal axis is the magnitude of the voltage applied to both ends of the polysilicon resistance, and the vertical axis (logarithmic scale) is the resistance value of the polysilicon resistance. The voltage coefficient of VOLTCO (ppm / V). FIG. 5 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. The figure which shows the form which divided | segmented 90 stripe area | region SR for resistors R1-R17 of FIG. 3 into several area / sub area. The figure which shows the various example of a change of the shape of the area | region which provides a resistor array. The figure which shows the example of a change which has a 2 or more different direction as an extending direction of the stripe provided in the same area | region about a resistor array. The figure which shows the example of a change which has arrange | positioned the stripe which has 2 or more different values as an aspect-ratio of a stripe in addition to the change which makes extension direction non-identical about a resistor array. The figure which shows the example of a change with respect to the division | segmentation method of the area | region which provides the resistor array of FIG.

Explanation of symbols

1: Oversampling digital-analog converter (DAC)
2: IC chip 3: Summing amplifier 4: Integrated circuit resistor array 22: Analog circuit region 30: Conversion resistor unit 32: CR filter unit 34: Differential buffer unit J1-J6: Junction points IN0-IN3, IN0￣ ~ IN3￣: inverter outputs IBF1, IBF2: inverting buffer VOUT: analog output voltage VCC: power supply voltage 40: N well region 41: N + active region 42: polysilicon layer stripes 43a, 43b: first metal layer 44: contact 45: Second metal layer 46: Via 220: Resistor array region 2200: Silicon substrate 2202: Diffusion layer 2204: First insulator layer 2206: Second insulator layer 2208: Third insulator layers A1 to A5: Sections A1S1 to A1S6 : A1 sub-area A2S1 to A2S3: A2 sub-area A3S1 to A3S3: A3 sub-area A S1~A4S6: A4 of the sub-zone A5S1~A5S3: A5 sub-area of

Claims (11)

An integrated circuit resistor array comprising:
a) an area on the integrated circuit chip;
b) A plurality of individual elongated resistive stripes dispersed in the one region, all of the same thickness and width, each having a first end and a second The plurality of different stripes, the voltage dependence of each of the various resistive stripes depending on the location of the resistive stripe in the region. With an elongated resistive stripe,
c) the one region includes a plurality of adjacent sub-regions including a first sub-region, each sub-region being further divided into at least three adjacent elongated non-overlapping sub-areas; thing,
d) each resistive stripe is included in only one sub-section, and each sub-section includes a plurality of said resistive stripes;
e) a first group of metal conductors, each metal conductor being one of the first and second ends of one resistive stripe of the first group of resistive stripes. Are connected to one end of another resistive stripe of the first group of resistive stripes to form a first resistor, and the first group of resistive stripes At least some of which are distributed in the first sub-region by being placed in separate sub-areas of the first sub-region, thereby forming the first resistor Said first group of metal conductors, which averages variations in voltage dependence of:
f) a second group of metal conductors, each metal conductor of the first and second of the resistive stripes of the second group other than the first group of resistive stripes. One end of the two ends is connected to the one end of another resistive stripe of the second group of resistive stripes to form a second resistor; At least some of the two groups of the resistive stripes are distributed in the first sub-region by being disposed in separate sub-areas of the first sub-region, thereby the second resistance The second group of metal conductors averaging the variation in voltage dependence of the resistive stripes forming the vessel;
g) In order to match the voltage dependence of the first resistor to the voltage dependence of the second resistor, the various stripes of the first group are arranged within the one region in the second group. In close proximity to the various stripes of
h) two of the first group of resistive stripes connected to each other by the first group of metal conductors are included in two adjacent sub-areas, respectively, and the two resistive stripes are adjacent Being arranged symmetrically with respect to the boundary of the two sub-regions,
i) Two of the second group of resistive stripes connected to each other by the second group of metal conductors are included in two adjacent sub-areas, respectively, and the two resistive stripes are adjacent Being arranged symmetrically with respect to the boundary of the two sub-regions,
j) each of the first and second resistors includes at least three or more resistive stripes disposed in the first sub-region;
k) The at least three or more resistive stripes disposed in the first sub-region of each of the first and second resistors are the first group or the second group of metal conductors. Connected in series by a metal conductor provided in the first sub-region,
An integrated circuit resistor array having the following requirements.   2. The array of claim 1, comprising first and second resistor groups, each group of the first and second resistor groups comprising a plurality of resistors having resistance values matched to each other. Each of the resistors includes a plurality of the resistive stripes, the resistive stripes forming the resistors respectively disposed in a plurality of sub-areas of a sub-region. Resistor array.   The array of claim 1, wherein the resistive stripes are evenly spaced from one another.   The array of claim 1, wherein the resistive stripes are rectangular and parallel to each other.   The integrated circuit resistor array of claim 1, wherein the one region is rectangular.   2. The array of claim 1, wherein the voltage dependency of the first resistor and the voltage dependency of the second resistor are the first resistor and the second resistor, respectively. An integrated circuit resistor array, characterized in that it depends on the width of the resistive stripe to be formed.   2. The integrated circuit resistor array of claim 1, wherein the resistive stripes are of the same length.   The integrated circuit resistor array of claim 1, wherein the sub-region is rectangular and the sub-area is rectangular.   9. The integrated circuit resistor of claim 8, comprising a sub-region including a sub-area, the sub-area not adjacent to any other sub-area within the sub-area. array.   The array of claim 6, wherein the resistive stripe is made of polycrystalline silicon. An integrated circuit resistor array comprising:
a) an area on the integrated circuit chip;
b) A plurality of individual elongated resistive stripes dispersed in the one region, all of the same thickness and width, each having a first end and a second The plurality of different stripes, the voltage dependence of each of the various resistive stripes depending on the location of the resistive stripe in the region. With an elongated resistive stripe,
c) the one region includes a plurality of adjacent sub-regions including first and second sub-regions, each sub-region further comprising at least three adjacent elongated non-overlapping sub-regions; Being divided,
d) each resistive stripe is included in only one sub-section, and each sub-section includes a plurality of said resistive stripes;
e) a first group of metal conductors, each metal conductor being one of the first and second ends of one resistive stripe of the first group of resistive stripes. Are connected to one end of another resistive stripe of the first group of resistive stripes to form a first resistor, and the first group of resistive stripes At least some of which are distributed in the first sub-region by being placed in separate sub-areas of the first sub-region, thereby forming the first resistor Said first group of metal conductors, which averages variations in voltage dependence of:
f) a second group of metal conductors, each of which is one of the first and second ends of one resistive stripe of the second group of resistive stripes. Are connected to one end of another resistive stripe of the second group of resistive stripes to form a second resistor, and the second group of resistive stripes At least some of which are distributed in the first sub-region by being disposed in separate sub-areas of the first sub-region, thereby forming the second resistor Said second group of metal conductors, which averages variations in voltage dependence of:
g) a third group of metal conductors, each of the metal conductors of the one of the resistive stripes of the third group other than those of the first group and the second group; One end of the first and second ends is connected to the one end of another resistive stripe of the third group of resistive stripes to form a third resistor. And at least some of the resistive stripes of the third group are distributed in the second sub-region by being disposed in separate sub-areas of the second sub-region, thereby A third group of metal conductors that averages variations in voltage dependence of the resistive stripe forming a third resistor;
h) In order to match the voltage dependence of the first resistor to the voltage dependence of the second resistor, the various stripes of the first group are arranged within the one region in the second group. In close proximity to the various stripes of
i) Two of the first group of resistive stripes connected to each other by the first group of metal conductors are included in two adjacent sub-areas, respectively, and the two resistive stripes are adjacent Being arranged symmetrically with respect to the boundary of the two sub-regions,
j) Two of the second group of resistive stripes connected to each other by the second group of metal conductors are included in two adjacent sub-areas, respectively, and the two resistive stripes are adjacent Being arranged symmetrically with respect to the boundary of the two sub-regions,
k) each of the first and second resistors includes at least three or more resistive stripes disposed in the first sub-region;
l) The at least three or more resistive stripes disposed in the first sub-region of each of the first and second resistors are connected to the first group or the second group of metal conductors. An integrated circuit resistor array comprising: a metal conductor provided in the first sub-region connected in series.

Images