JP2011086750A - Thin-film chip resistor - Google Patents

Abstract

Provided is a thin film chip resistor that can disperse load heat generation, can cope with higher power, and can correct a resistance value with higher accuracy.
A thin film resistor layer formed so as to be electrically connected to a pair of upper surface electrode layers formed on both ends of an upper surface of an insulating substrate is electrically connected to one of the pair of upper surface electrode layers. The first parallel resistance pattern 24a for coarse adjustment of the ladder shape that is electrically connected and the folded portion 24c that is electrically connected to the first parallel resistance pattern 24a and that is adjacent to the zigzag resistance pattern 24b are substantially connected. The second parallel resistance pattern 24e for rough adjustment, which is connected by the resistor pattern 24d having a square shape, is electrically connected between the second parallel resistance pattern 24e and the other of the pair of upper surface electrode layers 22. The second parallel resistance pattern 24e for coarse adjustment is arranged in a substantially central portion of the insulating substrate 21 in series.
[Selection] Figure 2

Description

  The present invention relates to a thin film chip resistor used in various electronic devices.

In recent years, in the field of car electronics, with increasing precision control of equipment, there is an increasing demand for higher precision for electronic components to be mounted. Thin film chip with high precision (resistance tolerance ± 0.1%, resistance temperature characteristics ± 10 × 10 ^-6 / ° C) and even higher power than chip resistors There is an increasing demand for resistors.

  FIG. 4 is a cross-sectional view of a conventional thin film chip resistor, and FIG. 5 is a flowchart showing a method for manufacturing the thin film chip resistor.

  As shown in FIG. 4, a conventional thin film chip resistor has a pair of metal organic materials mainly composed of gold formed on both ends of an upper surface of a rectangular insulating substrate 1 made of an alumina substrate having an alumina purity of about 96%. A pair of top electrode layers 2, a pair of back electrode layers 3 made of a metal-organic material mainly composed of gold formed on both ends of the back surface of the insulating substrate 1, and a pair of top surfaces A thin film resistor layer 4 made of a nickel-chromium alloy or the like formed so as to be electrically connected to the electrode layer 2, and covering the thin film resistor layer 4 and formed at both ends of the upper surface of the insulating substrate 1 The protective film layer 6 made of an epoxy resin covering the re-top electrode layer 5 made of a pair of conductive resins and the thin film resistor layer 4 and partially covering the pair of re-top electrode layers 5, The top electrode layer 5 and the back electrode layer 3 are electrically connected. A pair of end face electrode layers 7 formed on both end faces of the insulating substrate 1 so as to be connected to each other, and an electrode plating layer 8 made of a nickel plating layer and a tin plating layer formed by plating on the exposed electrode portion. It was composed.

  Next, a conventional thin film chip resistor manufacturing method is shown in the flowchart of FIG. 5, FIGS. 6 (a) to (c), FIGS. 7 (a) to (c), FIGS. 8 (a) to (c) and FIG. A description will be given based on the manufacturing process diagrams (a) to (d).

  First, as shown in FIG. 6A, a sheet-like insulating substrate 1 having an primary substrate having a primary division groove 1a and a secondary division groove 1b and having an alumina purity of about 96% is prepared.

  Next, as shown in FIG. 6 (b), the electrode paste made of a metal organic material mainly composed of gold is screen-printed across the primary division grooves 1a on the upper surface and back surface of the insulating substrate 1 and dried. Thereafter, in order to remove only the organic component of the electrode paste made of the metal organic material and to burn only the metal component onto the insulating substrate 1, the upper electrode layer 2 and the back electrode layer 3 (not shown) are baked by a belt-type continuous baking furnace. (Rear surface / upper surface electrode layer forming step in FIG. 5).

  Next, as shown in FIG. 6C, a thin film resistor layer 4 made of a nickel chromium alloy or the like is formed on the entire upper surface of the insulating substrate 1 by sputtering (resistor deposition step of FIG. 5).

  Next, as shown in FIGS. 7A to 7C, a photolithography process step for forming the thin film resistor layer 4 in a predetermined resistor pattern 4a (photoresist coating / drying, pattern exposure, development, etching, After each step of resist stripping, heat treatment is performed in an atmosphere of 300 to 400 ° C. (step of forming the thin film resistor layer in FIG. 5) in order to make the resistor pattern 4a a stable film.

  Next, as shown in FIG. 8A, a re-upper surface electrode layer 5 made of a conductive resin is formed so as to cover the thin film resistor layer 4 on the upper surface electrode layer 2 (re-upper surface electrode layer forming step of FIG. 5). ).

  Next, as shown in FIG. 8B, in order to correct the resistance value of the resistor pattern 4a to a predetermined value, the resistance value is corrected by laser trimming to obtain a resistor pattern 4b whose resistance value has been corrected. (Resistance value correcting step in FIG. 5).

  Next, as shown in FIG. 8C, in order to protect the resistor pattern 4b whose resistance value has been corrected, a protective film layer 6 made of a thermosetting epoxy resin is formed (the protective film in FIG. 5). Layer forming step).

  Next, as shown in FIG. 9A, the strip-shaped substrate 1e is obtained by dividing the sheet-like insulating substrate 1 along the primary dividing grooves 1a (primary dividing step in FIG. 5).

  Next, as shown in FIG. 9B, the end face electrode layer 7 is formed on the end face of the strip-shaped substrate 1e by sputtering or resin electrode coating (end face electrode layer forming step in FIG. 5).

  Next, as shown in FIG. 9C, the strip-shaped substrate 1e is divided along the secondary division grooves 1b to obtain the individual substrate 1f (secondary division step in FIG. 5).

  Finally, as shown in FIG. 9 (d), in order to ensure reliability during soldering, a step of forming an electrode plating layer 8 composed of a nickel plating layer and a tin plating layer on the exposed electrode portion by plating ( A conventional thin film chip resistor has been manufactured by performing the electrode plating layer forming step in FIG.

  Since the conventional thin film chip resistor configured as described above uses the thin film resistor layer 4 made of a nickel chromium alloy or the like, it can achieve high accuracy and low TCR characteristics.

  In the conventional thin film chip resistor described above, since the thickness and length of the thin film resistor layer 4 are determined for each target thin film resistor layer 4, the thin film resistor that determines the thickness of the thin film resistor layer 4 is determined. The combination of the sputtering process conditions for the resistor layer 4 and the resistance pattern that determines the length of the thin film resistor layer 4 must be determined. For example, the thin film resistor layer 4 for covering a wide range of 10Ω to 1MΩ. When the sputtering process conditions and the resistor pattern combinations are determined separately, a large number of combinations are required, and as a result, the manufacturing process becomes very complicated.

  In order to eliminate the complexity as described above, in the conventional thin film chip resistor, as shown in FIG. 10, the portion contributing to the resistance value is not damaged by the laser, and a large resistance value is rounded up. A resistor of the thin film resistor layer 9 in which a parallel circuit of resistor patterns to be realized is formed, and a part of the resistor pattern is cut with a laser to form a trimming portion, whereby a large resistance value can be obtained with one resistor pattern A pattern was used. That is, as shown in FIG. 10, the thin film resistor layer 9 electrically connected to the pair of upper surface electrode layers 11 formed at both ends of the upper surface of the insulating substrate 10 is, of the pair of upper surface electrode layers 11, A fine adjustment resistor pattern 9b formed at the tip of a zigzag resistance pattern 9a electrically connected to one upper surface electrode layer 11, and a ladder shape electrically connected to the fine adjustment resistor pattern 9b The first parallel resistance pattern 9c for coarse adjustment, and the first parallel resistance pattern 9c and the other upper surface electrode layer 11 of the pair of upper surface electrode layers 11 are electrically connected and have a zigzag resistance. A resistor pattern 9f is sequentially connected to the folded portion 9e of the pattern 9d to form a second parallel resistor pattern 9g for coarse adjustment, and the resistor pattern 9b for fine adjustment and a ladder-shaped coarse adjustment A part of each of the first parallel resistance pattern 9c and the second parallel resistance pattern 9g for coarse adjustment is cut with a laser to form trimming portions 12a, 12b, and 12c, thereby forming a single resistor pattern. The resistor pattern of the thin-film resistor layer 9 from which many resistance values are obtained was used.

  For example, Patent Documents 1 and 2 are known as prior art document information relating to the invention of this application.

Japanese Patent Laid-Open No. 1-108703 JP-A-1-251601

  In the resistor pattern of the thin film resistor layer in the conventional thin film chip resistor shown in FIG. 10 described above, in order to realize a wide range of resistance values, a ladder-shaped first parallel resistor pattern 9c for coarse adjustment, If the trimming portion 12a is formed by cutting only the fine adjustment resistance pattern 9b with a laser without cutting each of the second parallel resistance patterns 9g for coarse adjustment with a laser, the resistance value is reduced. In the resistor pattern of the thin film resistor layer in the conventional thin film chip resistor shown in FIG. 10, the ladder-shaped first parallel resistance pattern 9c for coarse adjustment and the coarse adjustment first resistor pattern 9c can be rounded up. When each of the two parallel resistance patterns 9g is not cut at all by the laser, the current path distribution is indicated by the hatched portion in FIG. Of will be concentrated on one half side, thereby, the load heat generation is biased, has a problem that more correspond to high power is prevented.

  Further, in the fine adjustment resistance pattern 9b, when the trimming portion 12a is formed by cutting with a laser, the resistance value increases as the laser enters the traveling direction. There was a problem that it was difficult to realize resistance value correction.

  The present invention has been made in order to solve the above-described conventional problems, and is a thin film that can disperse the heat generated by the load, can cope with higher power, and can correct the resistance value with higher accuracy. An object of the present invention is to provide a chip resistor.

  In order to achieve the above object, the present invention has the following configuration.

  According to a first aspect of the present invention, an insulating substrate, a pair of upper surface electrode layers formed at both ends of the upper surface of the insulating substrate, and a pair of upper surface electrode layers are formed so as to be electrically connected. And a protective film layer covering the thin film resistor layer, and the thin film resistor layer is electrically connected to one upper surface electrode layer of the pair of upper surface electrode layers The coarse parallel adjustment first parallel resistance pattern and a rough connection formed by connecting the adjacent folded portions of the zigzag resistance pattern with a substantially U-shaped resistance pattern and the first parallel resistance pattern. A second parallel resistance pattern for adjustment and a fine adjustment resistance pattern electrically connected between the second parallel resistance pattern and the other upper surface electrode layer of the pair of upper surface electrode layers And the second coarse adjustment second A plurality of sets of parallel resistance patterns are connected in series and arranged at a substantially central portion of the insulating substrate. According to this configuration, the thin film resistor formed to be electrically connected to the pair of upper surface electrode layers A ladder-shaped first parallel resistance pattern for coarse adjustment that is electrically connected to one upper surface electrode layer of the pair of upper surface electrode layers, and a first parallel resistance pattern that is electrically connected to the first parallel resistance pattern And a second parallel resistance pattern for coarse adjustment in which adjacent folded portions of the zigzag resistance pattern are connected by a substantially U-shaped resistance pattern, and the second parallel resistance pattern and the pair of upper surface electrode layers A fine adjustment resistor pattern electrically connected to the other upper surface electrode layer, and a plurality of coarse adjustment second parallel resistor patterns are connected in series to form an abbreviation of an insulating substrate. Placed in the center Therefore, the first parallel resistance pattern for coarse adjustment of the ladder and the second parallel resistance pattern for coarse adjustment are cut with a laser without cutting the resistance pattern for fine adjustment with a laser. As a result, even when the resistance value is rounded up, the current path is distributed over the entire resistor pattern of the thin film resistor layer, so that the load heat generation is biased as in the prior art. Therefore, it becomes possible to cope with higher power. Further, in the resistance value correction in the ladder-shaped first parallel resistance pattern for coarse adjustment and the second parallel resistance pattern for coarse adjustment, if these are corrected to a resistance value close to the target resistance value, fine adjustment is performed. Since the laser cutting with the resistance pattern is minimized, damage to the resistor by the laser can be minimized. In addition, when the laser approach distance in the resistance pattern for fine adjustment to be finally performed is the same as the conventional one, the resistance value increases compared to the conventional resistance pattern shape, so that the resistance value can be corrected with higher accuracy. It has a working effect.

  As described above, the thin film chip resistor of the present invention includes the thin film resistor layers formed so as to be electrically connected to the pair of upper surface electrode layers formed on both ends of the upper surface of the insulating substrate. A ladder-shaped first parallel resistance pattern for coarse adjustment, which is electrically connected to one upper surface electrode layer in the electrode layer, and an electrical connection to the first parallel resistance pattern and adjacent to the zigzag resistance pattern A second parallel resistance pattern for coarse adjustment formed by connecting folded portions to each other with a substantially U-shaped resistance pattern, and the second parallel resistance pattern and the other upper surface electrode layer of the pair of upper surface electrode layers And a plurality of the second parallel resistance patterns for coarse adjustment are connected in series and arranged at a substantially central portion of the insulating substrate. Because of the ladder shape By cutting only the resistance pattern for fine adjustment with a laser without cutting each of the first parallel resistance pattern for adjustment and the second parallel resistance pattern for coarse adjustment with a laser, the resistance value is reduced. Even when rounded up, the current path is distributed over the entire resistor pattern of the thin-film resistor layer, so that the load heat generation is not biased as in the prior art, so higher power can be achieved. Is possible. Further, in the resistance value correction in the ladder-shaped first parallel resistance pattern for coarse adjustment and the second parallel resistance pattern for coarse adjustment, if these are corrected to a resistance value close to the target resistance value, fine adjustment is performed. Since the laser cutting with the resistance pattern is minimized, damage to the resistor by the laser can be minimized. In addition, when the laser approach distance in the resistance pattern for fine adjustment to be finally performed is the same as the conventional one, the resistance value that increases compared to the conventional resistor pattern shape is small, so that the resistance value can be corrected with higher accuracy. This is an excellent effect.

Sectional drawing of the thin film chip resistor in one embodiment of this invention Top view showing a resistor pattern of a thin film resistor layer of the thin film chip resistor Top view showing current path without trimming in resistor pattern of same thin film resistor layer Cross-sectional view of a conventional thin film chip resistor Flow chart showing the manufacturing method of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(c) Manufacturing process diagram of the thin film chip resistor (A)-(d) Manufacturing process diagram of the thin film chip resistor Top view showing a resistor pattern of a thin film resistor layer of the thin film chip resistor Top view showing current path without trimming in resistor pattern of same thin film resistor layer

  Hereinafter, a thin film chip resistor according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a sectional view of a thin film chip resistor according to an embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a rectangular insulating substrate made of an alumina substrate having an alumina purity of about 96%. A pair of upper surface electrode layers 22 made of a metal organic material mainly composed of gold are formed at both ends of the upper surface of 21. Reference numeral 23 denotes a pair of back surface electrode layers made of a metal organic material mainly composed of gold, formed at both ends of the back surface of the insulating substrate 21, and 24 covers the pair of top surface electrode layers 22 and a pair of top surface electrodes. It is a thin film resistor layer made of a nickel chromium alloy or the like formed so as to be electrically connected to the layer 22. Reference numeral 25 denotes a re-upper surface electrode layer made of a pair of conductive resins that covers the thin film resistor layer 24 and is formed at both ends of the upper surface of the insulating substrate 21, and 26 covers the thin film resistor layer 24, and It is a protective film layer made of an epoxy resin that covers a part of the pair of upper surface electrode layers 25. Reference numeral 27 denotes a pair of end face electrode layers formed on both end faces of the insulating substrate 21 so as to electrically connect the re-upper surface electrode layer 25 and the back face electrode layer 23, and 28 denotes an exposed electrode portion formed by plating. The nickel plating layer. Reference numeral 29 denotes a tin plating layer formed by plating so as to cover the nickel plating layer 28.

  In addition, the manufacturing method of the thin film chip resistor in one embodiment of the present invention is shown in FIGS. 5, 6 </ b> A to 6 </ b> C, 7 </ b> A to 7 </ b> C, and FIGS. ), And the manufacturing method of the conventional thin film chip resistor shown in FIGS.

  FIG. 2 shows a resistor pattern of the thin film resistor layer 24 of the thin film chip resistor according to the embodiment of the present invention. The thin film resistor layer 24 is formed on the upper surface of the insulating substrate 21 as shown in FIG. The thin film resistor layer 24 is electrically connected to one upper surface electrode layer 22 of the pair of upper surface electrode layers 22. The first parallel resistance pattern 24a for coarse adjustment, which is connected electrically, and the folded portion 24c which is electrically connected to the first parallel resistance pattern 24a and adjacent to the zigzag resistance pattern 24b are substantially connected. A second parallel resistance pattern 24e for coarse adjustment connected by a square-shaped resistance pattern 24d, and the other upper surface electrode layer 2 of the second parallel resistance pattern 24e and the pair of upper surface electrode layers 22 Those that are composed of the resistor pattern 24f for fine adjustment that is electrically connected between the. In addition, a plurality of the second parallel resistance patterns 24e for coarse adjustment are connected in series and arranged at a substantially central portion of the insulating substrate 21.

  Further, the ladder-shaped first parallel resistance pattern 24a for coarse adjustment, the second parallel resistance pattern 24e for coarse adjustment, and the resistance pattern 24f for fine adjustment in the thin film resistor layer 24 are each one. By cutting the portion with a laser to form the trimming portions 30a, 30b, and 30c, many resistance values can be obtained with one resistor pattern.

  In the embodiment of the present invention described above, the resistance value that increases when all the parallel portions of the ladder-shaped first parallel resistance pattern 24a for coarse adjustment are cut is the first value for coarse adjustment. The resistance value is equal to or greater than the resistance value that increases when one substantially U-shaped resistance pattern 24d in the two parallel resistance patterns 24e is cut. In order to achieve this condition, the length L1 of the ladder-shaped first parallel resistance pattern 24a for coarse adjustment and the length of the zigzag resistance pattern 24b in the second parallel resistance pattern 24e for coarse adjustment are used. In relation to L2, L1 and L2 are made equal or L1 is made longer than L2.

  Furthermore, in the above-described embodiment of the present invention, the resistance value that increases when the trimming portion 30c is formed by cutting the fine adjustment resistor pattern 24f with a laser is the same as that of the ladder-shaped coarse adjustment. This is equal to or more than the resistance value that increases when one ladder portion in one parallel resistance pattern 24a is cut.

  Further, the fine adjustment resistor pattern 24f is formed by scanning the laser by shifting it by a few μm perpendicular to the laser traveling direction from the first trimming portion 30c for fine adjustment formed by cutting with a laser. When the second trimming portion 30d for re-adjustment is inserted, the resistance value correction accuracy on the order of 0.01% can be improved to a conventional level on the order of 0.001%. The resistance value correction accuracy can be increased.

  In the embodiment of the present invention, the ladder-shaped first parallel resistance pattern 24a for coarse adjustment and the second parallel resistance pattern 24e for coarse adjustment are completely cut with a laser. In addition, the resistance value can be increased by cutting only the fine adjustment resistance pattern 24f with a laser to form the trimming portion 30c. In this case, the current path is indicated by the hatched portion in FIG. In addition, since the resistor pattern of the thin film resistor layer 24 is distributed over the entire resistor pattern, the load heat generation is not biased as in the prior art shown in FIG. It will be.

  In the embodiment of the present invention described above, in the resistance value correction in the ladder-shaped first parallel resistance pattern 24a for coarse adjustment and the second parallel resistance pattern 24e for coarse adjustment, these are set as target resistances. If the resistance value close to the value is corrected, cutting by the laser at the fine adjustment resistor pattern 24f can be minimized, so that damage to the resistor by the laser can be minimized.

  Further, in the embodiment of the present invention, when the laser approach distance in the final fine adjustment resistor pattern 24f is the same as the conventional one, the resistance value increased compared to the conventional resistor pattern shape. Since the number is small, the resistance value can be corrected with higher accuracy.

  Furthermore, in the above-described embodiment of the present invention, the fine adjustment resistor pattern 24f is electrically connected between the second parallel resistor pattern 24e and the other upper electrode layer 22 in the pair of upper electrode layers 22. Since the fine adjustment resistor pattern 24f is cut with a laser to form the first trimming portion 30c for fine adjustment, the remaining width space of the resistor on one side is secured. Therefore, it is possible to provide a margin for laser alignment. On the other hand, conventionally, as shown in FIG. 10, the tip of the zigzag resistance pattern 9a in which the fine adjustment resistance pattern 9b is electrically connected to one upper surface electrode layer 11 of the pair of upper surface electrode layers 11 is used. Therefore, when the trimming portion 12a is formed by cutting the fine adjustment resistor pattern 9b with a laser, it is necessary to secure the remaining width space of the resistors on both sides in the longitudinal direction. Laser alignment is difficult.

  The thin film chip resistor according to the present invention can disperse the heat generated by the load, can cope with higher power, and has the effect that the resistance value can be corrected with higher accuracy. The present invention is useful when applied to various electronic devices.

DESCRIPTION OF SYMBOLS 21 Insulating substrate 22 Upper surface electrode layer 24 Thin film resistor layer 24a 1st parallel resistance pattern 24b Zigzag resistance pattern 24c Folding part 24d Substantially U-shaped resistance pattern 24e 2nd parallel resistance pattern 24f Fine adjustment resistance pattern 26 Protection Membrane layer

Claims (1)

An insulating substrate, a pair of upper surface electrode layers formed on both ends of the upper surface of the insulating substrate, a thin film resistor layer formed so as to be electrically connected to the pair of upper surface electrode layers, and the thin film resistor A ladder-shaped first parallel resistance pattern for coarse adjustment, wherein the thin film resistor layer is electrically connected to one upper surface electrode layer of the pair of upper surface electrode layers; A second parallel resistance pattern for coarse adjustment, which is electrically connected to the first parallel resistance pattern and is formed by connecting adjacent folded portions of the zigzag resistance pattern with a substantially U-shaped resistance pattern; A second parallel resistance pattern and a fine adjustment resistance pattern electrically connected between the other upper surface electrode layer of the pair of upper surface electrode layers and the second parallel adjustment for coarse adjustment Multiple resistor patterns in series Thin film chip resistor disposed in a substantially central portion of the insulating substrate continue to.

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