JP4218476B2 - レジストパターン形成方法とデバイス製造方法 - Google Patents
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- 238000010894 electron beam technology Methods 0.000 claims description 27
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- 230000009477 glass transition Effects 0.000 claims description 16
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- 230000008901 benefit Effects 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 2
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
- G03F7/0007—Filters, e.g. additive colour filters; Components for display devices
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/949—Energy beam treating radiation resist on semiconductor
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Materials For Photolithography (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Description
図1(a)に示すように、Si基板1の表面に厚さ110nm程度の反射防止膜(BARC)11を塗布する。更にその上層に、電子ビームの照射によってガラス転移温度が上昇するレジスト剤(例えば、信越化学製、化学増幅型ポジレジスト剤SEPR411)12を1000nm程度の厚さに塗布し、100℃程度でベーク処理を行う。次に、KrFエキシマレーザー露光装置(開口数=0.60、σ=0.75)を用いて、0.28μmコンタクト図形を含む所望の設計回路を有するマスクMのパターンを、95mJ/cm2程度の露光で焼き付ける。
露光されたレジスト剤12を、テトラメチル・アンモニウム・ハイドロオキサイト(TMAH)2.38%現像液によって現像処理を行う。これにより、図1(b)に示すように、レジスト剤12の露光部が垂直に除去され、280nm設計のホールパターンを有するレジストパターン12aが形成される。
図1(c)に示すように、レジストパターン12aが形成されたSi基板1の全面に、電子ビーム(EB)を照射する。ここでは、レジストパターン12aの上層部を選択的に電子ビーム処理するために、1keV,500μC/cm2で照射処理を行う。これにより、電子ビーム処理が行われたレジストパターン12bの上層部のガラス転移温度が150℃程度に上昇し、耐熱性が向上する。
ホットプレートを用いて、レジストパターン12bに対して155℃、90秒のベーク処理を行う。これにより、レジストパターン12bの下層部で、電子ビーム処理が行われていない箇所(ガラス転移温度が低い部分)に熱だれが生じ、図1(d)に示すようにホールパターンの形状がテーパー状になったレジストパターン12cが得られる。即ち、レジストパターン12cの上層部におけるホール径は、初めに形成したとおりの0.28μmに維持され、このレジストパターン12cの下層部におけるホール径は、最初の寸法よりも縮小して、例えば0.10μmとなる。
まず、シリコンウエハに対して、素子分離工程、ゲート形成工程等を行って形成されたシリコン基板1の表面に、シリコン酸化膜(NSG)等の層間絶縁膜2を1000nm程度の厚さに形成する。更に、層間絶縁膜2の表面に厚さ110nm程度の反射防止膜11を塗布した後、その上層に電子ビームの照射によってガラス転移温度が上昇するレジスト剤12を1000nm程度の厚さに塗布し、100℃程度でベーク処理を行う。
露光されたレジスト剤12を、テトラメチル・アンモニウム・ハイドロオキサイト2.38%現像液によって現像処理を行う。これにより、図2(b)に示すように、レジスト剤12の露光部が垂直に除去され、280nm設計のホールパターンを有するレジストパターン12aが形成される。
図2(c)に示すように、レジストパターン12aが形成されたSi基板1の全面に、電子ビームを照射する。ここでは、レジストパターン12aの上層部を選択的に電子ビーム処理するために、1keV,500μC/cm2で照射処理を行う。これにより、電子ビーム処理が行われたレジストパターン12bの上層部のガラス転移温度が150℃程度に上昇し、耐熱性が向上する。
ホットプレートを用いて、レジストパターン12bに対して155℃、90秒のベーク処理を行う。これにより、レジストパターン12bの下層部で、電子ビーム処理が行われていない箇所に熱だれが生じ、図2(d)に示すようにホールパターンの形状がテーパー状になったレジストパターン12cが得られる。即ち、レジストパターン12cの上層部におけるホール径は、初めに形成したとおりの0.28μmに維持され、このレジストパターン12cの下層部におけるホール径は、最初の寸法よりも縮小して、例えば0.10μmとなる。
このように形成されたテーパー状のレジストパターン12cをエッチングマスクとして、通常の方法で加工対象の層間絶縁膜2をエッチングする。これにより、レジストパターン12cと層間絶縁膜2が同時にテーパー状にエッチングされ、図2(e)に示すように、上部のホール径が0.28μm、下部のホール径が0.1μmのテーパー形状になった、目的とするコンタクトホール2hが形成された層間絶縁膜2aが得られる。その後、通常のコンタクトホール埋め込み工程、及びメタル配線工程等によってデバイスの製造を行う。
1h,2h コンタクトホール
2,2a 層間絶縁膜
11 反射防止膜
12 レジスト剤
12a〜12c レジストパターン
Claims (2)
- 電子ビームの照射によってガラス転移温度が上昇するレジスト剤を加工対象の基板上に塗布する処理と、
前記レジスト剤に対して露光及び現像を行うことにより所定のレジストパターンを形成する処理と、
前記レジストパターンの表面に一定量の電子ビームを照射してその表面のガラス転移温度を上昇させる処理と、
前記電子ビームが照射されたレジストパターンを所定の温度でベーク処理することにより、該レジストパターンの下層部を流動化させて断面をテーパー状にする処理とを、
順次施すことを特徴とするレジストパターン形成方法。 - 電子ビームの照射によってガラス転移温度が上昇するレジスト剤を加工対象の基板上に塗布する処理と、
前記レジスト剤に対して露光及び現像を行うことにより所定のレジストパターンを形成する処理と、
前記レジストパターンの表面に一定量の電子ビームを照射してその表面のガラス転移温度を上昇させる処理と、
前記電子ビームが照射されたレジストパターンを所定の温度でベーク処理することにより、該レジストパターンの下層部を流動化させて断面をテーパー状にする処理と、
前記断面がテーパー状になったレジストパターンをマスクとして、前記加工対象の基板をエッチングしてテーパー形状の穴または溝を形成する処理とを、
順次施すことを特徴とするデバイス製造方法。
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JP2003320779A JP4218476B2 (ja) | 2003-09-12 | 2003-09-12 | レジストパターン形成方法とデバイス製造方法 |
US10/829,450 US6900141B2 (en) | 2003-09-12 | 2004-04-22 | Method of forming a resist pattern and fabricating tapered features |
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US7585616B2 (en) * | 2005-01-31 | 2009-09-08 | Hewlett-Packard Development Company, L.P. | Method for making fluid emitter orifice |
US7927991B2 (en) * | 2006-08-25 | 2011-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP4801550B2 (ja) | 2006-09-26 | 2011-10-26 | 富士通株式会社 | レジスト組成物、レジストパターンの形成方法、及び半導体装置の製造方法 |
JP5409247B2 (ja) * | 2009-10-13 | 2014-02-05 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP5659872B2 (ja) | 2010-10-22 | 2015-01-28 | 富士通株式会社 | レジストパターン改善化材料、レジストパターンの形成方法、及び半導体装置の製造方法 |
JP5659873B2 (ja) | 2010-12-16 | 2015-01-28 | 富士通株式会社 | レジストパターン改善化材料、レジストパターンの形成方法、及び半導体装置の製造方法 |
JP5708071B2 (ja) | 2011-03-11 | 2015-04-30 | 富士通株式会社 | レジストパターン改善化材料、レジストパターンの形成方法、及び半導体装置の製造方法 |
US8649153B2 (en) | 2011-04-28 | 2014-02-11 | International Business Machines Corporation | Tapered via and MIM capacitor |
US9182662B2 (en) * | 2012-02-15 | 2015-11-10 | Rohm And Haas Electronic Materials Llc | Photosensitive copolymer, photoresist comprising the copolymer, and articles formed therefrom |
US9293414B2 (en) * | 2013-06-26 | 2016-03-22 | Globalfoundries Inc. | Electronic fuse having a substantially uniform thermal profile |
CN106105263B (zh) * | 2014-01-06 | 2019-05-10 | 沃尔音频公司 | 线性动圈磁驱动系统 |
JP6733163B2 (ja) * | 2015-12-03 | 2020-07-29 | 大日本印刷株式会社 | インプリントモールド及びその製造方法、並びにインプリント方法 |
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US5096802A (en) * | 1990-11-09 | 1992-03-17 | Hewlett-Packard Company | Holes and spaces shrinkage |
JPH1098162A (ja) * | 1996-09-20 | 1998-04-14 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2000182940A (ja) | 1998-12-17 | 2000-06-30 | Sony Corp | レジストパターン形成方法 |
KR100557585B1 (ko) * | 1999-10-29 | 2006-03-03 | 주식회사 하이닉스반도체 | 레지스트 플로우 공정용 포토레지스트 조성물 및 이를 이용한 컨택홀의 형성방법 |
US6358670B1 (en) * | 1999-12-28 | 2002-03-19 | Electron Vision Corporation | Enhancement of photoresist plasma etch resistance via electron beam surface cure |
JP4308407B2 (ja) | 2000-04-26 | 2009-08-05 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
JP2001326153A (ja) | 2000-05-12 | 2001-11-22 | Nec Corp | レジストパターンの形成方法 |
JP2001332484A (ja) | 2000-05-24 | 2001-11-30 | Toshiba Corp | パターン処理方法 |
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2003
- 2003-09-12 JP JP2003320779A patent/JP4218476B2/ja not_active Expired - Fee Related
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2004
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US6900141B2 (en) | 2005-05-31 |
US20050059256A1 (en) | 2005-03-17 |
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