JP4176385B2 - Image display device - Google Patents

Description

【００４５】
信号線が表１に示した順序で選択された場合に、画素にアナログ映像信号が書き込まれる順序を、図３（Ａ）に模式図で示す。なお比較のため、画素にアナログ映像信号が書き込まれる一般的な順序を、図３（Ｂ）に模式図で示す。
【００４６】
図３（Ａ）に示すとおり、表１に示す順序で信号線を選択した場合、アナログ映像信号が最初に書き込まれる信号線が、１水平走査期間毎に異なる。一方、図３（Ｂ）に示すとおり、信号線の選択順が固定されている場合は、各水平走査期間において常に同じ信号線に最初にアナログ映像信号が書き込まれる。
【００４７】
よって、表１に示した駆動方法では、最初に映像信号が書き込まれる信号線の電位が変化しても、１水平走査期間毎に変調を受けた電位が書き込まれる画素の水平方向における位置が変わるため、人間の目に縦縞が視認されにくい。なお、図３（Ａ）の駆動例において、アナログ映像信号が最初に書きこまれる信号線が、複数の水平走査期間毎に異なっていても良い。
【００４８】
なお本発明の信号線の選択順は、表１に示した順序に限定されない。表１に示すようにある一定の規則性を有していても良いし、ランダムであっても良い。表２に、本発明の信号線の選択順の、表１とは異なる例を示す。
【００４９】
【表２】

【００５０】
表２では表１と異なり、１水平走査期間毎に、最初に選択される信号線の番号が異なっており、なおかつ、全ての信号線が、必ずいずれかの水平走査期間において最初に選択されている。上記構成では、最初に選択される期間が全ての信号線において設けられているので、表１の駆動方法に比べ、フレーム周波数が同じでも縦縞がより視認されにくくなる。
【００５１】
また、１水平走査期間毎または複数の水平走査期間毎に信号線の選択順を変え、さらに各フレーム期間毎に信号線の選択順を変えるようにしても良い。例えば、先のフレーム期間においては表１に示した順序で信号線を選択し、次に出現するフレーム期間においては、表２に示した順序で信号線を選択するようにしても良い。この構成により、単に水平走査期間毎に順序を変える駆動方法に比べて、フレーム周波数が同じでも縦縞がより視認されにくくなる。
【００５２】
なお、本発明の実施の形態では、デジタル映像信号を入力し、各信号線に対応するアナログ映像信号を出力する信号線駆動回路（いわゆるデジタル信号線駆動回路）を例に挙げて示しているが、本発明はこれに限定されない。例えば、アナログ映像信号を入力し、各信号線に対応するアナログ映像信号を出力する信号線駆動回路（いわゆるアナログ信号線駆動回路）を用いていても良い。
【００５３】
本発明は上記構成により、信号線駆動回路内の回路素子の数を従来例のｎ分の１にすることが可能である。また、階調の異なる画素の水平方向における位置が変わるため、フレーム周波数を変えなくとも人間の目に縦縞が視認されにくくなる。
【００５４】
また、以上の実施の形態の説明において、第１の記憶回路を制御する回路としてシフトレジスタを用いたが、シフトレジスタではなく、デコーダ回路を使用しても良い。また、Ｄ／Ａ変換回路はランプ型Ｄ／Ａ変換回路を用いても良い。その場合、Ｄ／Ａ変換回路の個数はｋ／ｎとは限定されない。
【００５５】
【実施例】
以下、本発明の実施例を示す。
【００５６】
（実施例１）
本実施例では、本発明の画像表示装置において用いられる信号線選択回路の詳しい構成について説明する。
【００５７】
図４（Ａ）に本実施例の信号線選択回路（ＳＥＬ）の回路図を示す。なお本実施例では、１つのＤ／Ａ変換回路を共用している信号線の数を示すパラメータとしてｎを用いる。ただし図４では説明を簡単にするために、１つのＤＡＣが４つの信号線に対応している場合について示す。以下、一般的な説明にｎを用いるが、〔 〕内にｎ＝４の場合の具体的な数字を示す。
【００５８】
本実施例では、アナログスイッチがｐチャネル型トランジスタとｎチャネル型トランジスタを有している。しかし本発明はこれに限定されず、ｐチャネル型トランジスタのみを用いたアナログスイッチでも良いし、ｎチャネル型トランジスタのみを用いたアナログスイッチであってもい。
【００５９】
本実施例の信号線駆動回路（ＳＥＬ）は、ｎ個〔４個〕のアナログスイッチ４００＿１〜４００＿ｎ〔４００＿１〜４００＿４〕を有している。そして各アナログスイッチには、スイッチングを制御する選択信号が入力されている。
【００６０】
スイッチングを制御する選択信号は、選択信号線を介してアナログスイッチ４００＿１〜４００＿ｎ〔４００＿１〜４００＿４〕に入力される。各アナログスイッチに異なる電位を有する選択信号が入力されており、選択信号線は各アナログスイッチごとに設ける。
【００６１】
本実施例では、アナログスイッチがｐチャネル型トランジスタとｎチャネル型トランジスタを有しており、選択信号の極性を反転させた信号もアナログスイッチに入力する。よって、本実施例では選択信号ＳＳ１〜ＳＳｎ〔ＳＳ１〜ＳＳ４〕と、各選択信号の極性を反転させた信号ＳＳｂ１〜ＳＳｂｎ〔ＳＳｂ１〜ＳＳｂ４〕を、各アナログスイッチに入力する。なお、本実施例では、選択信号の極性を反転させた信号も併せて選択信号と総称する。
【００６２】
図４（Ｂ）に、信号線Ｓｉ〜Ｓ（ｉ＋ｎ−１）〔Ｓ（ｉ＋３）〕を選択するときの、選択信号のタイミングチャートを示す。なお選択信号ＳＳｂ１〜ＳＳｂ４は、選択信号ＳＳ１〜ＳＳ４の極性を反転させただけなので、ここでは選択信号ＳＳ１〜ＳＳ４のみ示す。
【００６３】
図４（Ｂ）では、同じＤＡＣに接続されたｎ本〔４本〕の信号線Ｓｉ、Ｓ（ｉ＋１）、Ｓ（ｉ＋２）、Ｓ（ｉ＋ｎ−１）〔Ｓ（ｉ＋３）〕を、表１に示した順序で選択する例を示している。なお本実施例の信号線の選択順は、表１に示した順序に限定されない。
【００６４】
まず水平走査期間が開始されると、選択信号ＳＳ１、ＳＳｂ１のパルスに同期して信号線Ｓｉが選択される。そして、ＤＡＣから出力されたアナログ映像信号がアナログスイッチ４００＿１を介して信号線Ｓｉに入力される。
【００６５】
そして同様に、選択信号ＳＳ２〜ＳＳｎ〔ＳＳ２〜ＳＳ４〕、ＳＳｂ２〜ＳＳｂｎ〔ＳＳ２〜ＳＳ４〕のパルスに同期して、順に信号線Ｓ（ｉ＋１）〜Ｓ（ｉ＋ｎ−１）〔Ｓ（ｉ＋３）〕が選択される。そして、ＤＡＣから出力されたアナログ映像信号がアナログスイッチ４００＿２〜４００＿４〔４００＿ｎ〕を介して信号線Ｓ（ｉ＋１）〜Ｓ（ｉ＋３）に入力される。
【００６６】
そして１水平走査期間が終了し、次の水平走査期間が開始されると、選択信号ＳＳｎ、ＳＳｂｎ〔ＳＳ４、ＳＳｂ４〕のパルスに同期して信号線Ｓ（ｉ＋ｎ−１）〔Ｓ（ｉ＋３）〕が選択される。そして、ＤＡＣから出力されたアナログ映像信号がアナログスイッチ４００＿ｎ〔４００＿４〕を介して信号線Ｓ（ｉ＋ｎ−１）〔Ｓ（ｉ＋３）〕に入力される。
【００６７】
そして同様に、選択信号ＳＳ（ｎ−１）〜ＳＳ１〔ＳＳ３〜ＳＳ１〕、ＳＳｂ（ｎ−１）〜ＳＳｂ１〔ＳＳ（ｎ−１）〜ＳＳ１〕のパルスに同期して、順に信号線Ｓ（ｉ＋ｎ−２）〜Ｓｉ〔Ｓ（ｉ＋２）〜Ｓｉ〕が選択される。そして、ＤＡＣから出力されたアナログ映像信号がアナログスイッチ４００＿（ｎ−１）〔４００＿３〕〜４００＿１を介して信号線Ｓ（ｉ＋２）〜Ｓｉに入力される。
【００６８】
上述したように、信号線の選択順は選択信号によって制御することが可能である。
【００６９】
（実施例２）
本実施例では、駆動に関わる各種信号を生成する、本発明の画像表示装置のコントローラの構成について説明する。
【００７０】
図５に本実施例の画像表示装置の構成をブロック図で示す。５００は画素部、５０１は信号線駆動回路、５０２は走査線駆動回路を示している。５０３は信号線選択回路群であり、信号線駆動回路５０１に含まれる。
【００７１】
５０４はコントローラであり各種回路を有している。具体的には主に、バッファ５０５、表示用メモリ５０６、タイミング発生回路５０７、選択回路用タイミング発生回路５０８、フォーマット回路５０９を有してる。なおこの他に、バイアス電圧発生回路、シリアルインターフェース等を有していても良い。
【００７２】
コントローラ５０４は主に映像信号（Ｖｉｄｅｏ Ｓｉｇｎａｌｓ）と、基準クロック信号（Ｄｏｔ ＣＬＫ）と、水平同期信号（Ｈｓｙｎｃ）と、垂直同期信号（Ｖｓｙｎｃ）とが入力される。
【００７３】
映像信号はバッファ５０５において増幅または緩衝増幅され、表示用メモリ５０６に書き込まれる。なお、必ずしも映像信号をバッファ５０５において増幅または緩衝増幅する必要はなく、バッファ５０５を設けることは必須ではない。
【００７４】
また、基準クロック信号、水平同期信号（Ｈｓｙｎｃ）及び垂直同期信号（Ｖｓｙｎｃ）は、タイミング発生回路５０７に入力される。なお本実施例では、基準クロック信号を画像表示装置の外部から入力しているが、本実施例はこの構成に限定されない。基準クロック信号を外部から入力せずに、画像表示装置に入力された水平同期信号（Ｈｓｙｎｃ）をもとに生成するようにしても良い。
【００７５】
タイミング発生回路５０７では、入力された基準クロック信号、水平同期信号（Ｈｓｙｎｃ）及び垂直同期信号（Ｖｓｙｎｃ）に従って、各種回路の動作のタイミングを決定する信号を生成する。
【００７６】
具体的には、信号線駆動回路５０１用のクロック信号（Ｓ−ＣＬＫ）及びスタートパルス信号（Ｓ−ＳＰ）と、走査線駆動回路５０２用のクロック信号（Ｇ−ＣＬＫ）及びスタートパルス信号（Ｇ−ＳＰ）が、タイミング発生回路５０７において生成される。
【００７７】
さらに、映像信号を表示用メモリ５０６に書き込むタイミングと、表示用メモリ５０６が保持する映像信号をフォーマット回路５０９に入力するタイミングが、タイミング発生回路５０７において決定される。
【００７８】
また、信号線選択回路群５０３において信号線の選択されるタイミングが、タイミング発生回路５０７において決定される。なお、各水平走査期間内にｎ本の信号線が選択されるため、信号線の選択されるタイミングは、各水平走査期間内にｎ回出現する。ただしｎは１つのＤＡＣを共用している信号線の数を意味する。信号線の選択されるタイミングを決める信号は、タイミング発生回路５０７から選択回路用タイミング発生回路５０８に入力される。
【００７９】
選択回路用タイミング発生回路５０８は、選択信号を生成する選択信号生成回路５１０と、信号線の選択順のデータが蓄積されている選択順決定レジスタ５１１とを有している。選択信号生成回路５１０には、タイミング発生回路５０７から、信号線の選択されるタイミングを決める信号が入力される。また選択信号生成回路５１０には、選択順決定レジスタ５１１から、信号線の選択順のデータが入力される。
【００８０】
選択信号生成回路５１０は、信号線の選択順のデータと、ｎ回出現する信号線の選択されるタイミングを決める信号をもとに、選択信号ＳＳ１〜ＳＳｎを生成する。選択信号ＳＳ１〜ＳＳｎのそれぞれは、１水平走査期間内にパルスが１回出現する。該パルスに同期して、信号線が選択される。
【００８１】
一方、フォーマット回路５０９にも、選択順決定レジスタ５１１に蓄積されている信号線の選択順のデータが送られる。そして、フォーマット回路５０９に入力された映像信号は、該信号線の選択順のデータに従って並び替えられ、信号線駆動回路５０１の第１の記憶回路群（図示せず）に入力される。なお、フォーマット部５０９において、映像信号をシリアル−パラレル変換して複数に分割してから、第１の記憶回路群（図示せず）に入力に入力しても良い。
【００８２】
なお図５では、タイミング発生回路５０７と選択回路用タイミング発生回路５０８とを区別して示したが、選択回路用タイミング発生回路５０８を、タイミング発生回路５０７の一部とみなしても良い。また図５では、表示用メモリ５０６をコントローラ５０４の一部とみなして示したが、表示用メモリ５０６をコントローラ５０４と別にしても良い。
【００８３】
また、図５は表示用メモリがコントローラ５０４としか接続されておらず、ＣＰＵ（図示せず）が管理するシステムバスとは独立しているが、本実施例はこの構成に限定されない。ＣＰＵとコントローラ５０４とが同一の表示用メモリを共用していても良い。
【００８４】
また、選択順決定レジスタ５１１に記憶されている、信号線の選択順のデータは、マスク等の設計により決められた固定データであっても良いし、ＣＰＵやディップスイッチ等による書き換えが可能なデータであっても良い。
【００８５】
本実施例の構成は、実施例１と自由に組み合わせて実施することが可能である。
【００８６】
（実施例３）
本実施例では、本発明の信号線駆動回路で用いられる第１及び第２の記憶回路の具体的な構成について説明する。
【００８７】
記憶回路の具体例を図６に示す。図６（Ａ）はクロックドインバータを用いたものであり、図６（Ｂ）はＳＲＡＭ型のものであり、図６（Ｃ）はＤＲＡＭ型のものである。これらは代表例であり、本発明はこれらの形式に限定されない。
【００８８】
なお、制御信号２は、制御信号１の極性を反転させた信号に相当する。また、第２の記憶回路の場合、制御信号にラッチパルスを入力する。
【００８９】
本実施例の構成は、実施例１または２と自由に組み合わせて実施することが可能である。
【００９０】
（実施例４）
本実施例では、Ｄ／Ａ変換回路にランプ型Ｄ／Ａ変換回路を採用した場合の、信号線駆動回路の構成について説明する。
【００９１】
図７にランプ型Ｄ／Ａ変換回路を用いた場合の信号線駆動回路の概略図を示す。なお、本実施例ではＸＧＡ規格の画像表示装置で３ビットのデジタル映像信号に対応した場合を説明するが、本発明は３ビットに限らず、それ以外のビット数に対応した場合やＸＧＡ以外の規格の画像表示装置についても有効である。
【００９２】
本実施例において、シフトレジスタ７０１、第１の記憶回路群７０２、第２の記憶回路群７０３、信号線選択回路群７０６の構成及び動作は、実施の形態と同じである。本実施例は、第２の記憶回路７０３の下段に、ビット比較パルス幅変換回路群７０４及びアナログスイッチ群７０５を有している点が実施の形態の場合と異なる。ビット比較パルス幅変換回路群７０４とアナログスイッチ群７０５との二つの回路が、ランプ型Ｄ／Ａ変換回路として機能する。
【００９３】
ビット比較パルス幅変換回路群には、本実施例では２５６個のビット比較パルス幅変換回路（ＢＰＣ）が設けられている。ＢＰＣには、第２の記憶回路群７０３に記憶されていた３ビットのデジタル映像信号、カウント信号（Ｃ０〜Ｃ２）、セット信号（ＳＴ）が入力される。
【００９４】
アナログスイッチ群７０５には、本実施例では２５６個のアナログスイッチ（ＡＳＷ）が設けられている。アナログスイッチ群７０５には、ビット比較パルス幅変換回路群７０４の出力（ＰＷ−ｉ、ｉは００１〜２５６）と、階調電源（ＶＲ）が入力される。信号線選択回路群７０６にはアナログスイッチ群７０５の出力と選択信号（ＳＳ１〜ＳＳ４）が入力される。
【００９５】
第ｉ段目のＢＰＣの構成を図８に例示する。ＢＰＣは排他的論理和ゲート、３入力ＮＡＮＤゲート、インバータ、セットリセットフリップフロップ（ＲＳ−ＦＦ）を有する。図８では、ｉ段目の第２の記憶回路の出力を、ビットを区別して、Ｌ２−ｉ（０）、Ｌ２−ｉ（１）Ｌ２−ｉ（２）（括弧内はビット番号を表す）とした。
【００９６】
次に、本実施例の信号線駆動回路の動作について説明する。図７の回路動作の概略を理解するために必要な信号系のタイミングチャートを図９に示した。シフトレジスタ７０１から第２の記憶回路群７０３までの動作も、実施の形態で示した信号線駆動回路と同じである。また、信号線選択回路群７０６に入力される選択信号（ＳＳ１〜ＳＳ４）についても、実施の形態の図２で示した信号線駆動回路の場合と同じである。
【００９７】
図９において、信号線選択回路群７０６により４本の信号線が順次選択されていくたびに、カウント信号（Ｃ０〜Ｃ２）、セット信号（ＳＴ）、階調電源（ＶＲ）が周期的に入力される。これにより信号線全てに情報の書き込みを同等に行なうことができる。
【００９８】
ランプ型Ｄ／Ａ変換回路の詳細な動作を説明するために、４本の信号線のうち１本が信号線選択回路により選択されている期間の、タイミングチャートを図１０に示す。
【００９９】
まず、セット信号のパルスに同期して、ＲＳ−ＦＦ３０がセットされ、出力ＰＷ−ｉがＨｉレベルになる。次に、第２の記憶回路群７０３に記憶されていたデジタル映像信号は、排他的論理和ゲートによってカウント信号（Ｃ０〜Ｃ２）とビット毎に比較される。３ビット全てが一致した場合には、全ての排他的論理和ゲートの出力がＨｉレベルになり、その結果、３入力ＮＡＮＤゲートの出力（反転ＲＣ−ｉ）はＬｏレベルになる（したがって、ＲＣ−ｉはＨｉレベルになる）。この３入力ＮＡＮＤの出力もＲＳ−ＦＦ３０に入力され、ＲＣ−ｉがＨｉレベルになるとリセットされ、出力ＰＷ−ｉがＬｏレベルに戻る。図１０には、３ビットのデジタル映像信号｛Ｌ２−ｉ（０）、Ｌ２−ｉ（１）Ｌ２−ｉ（２）｝が｛０、０、１｝の場合についてのＲＣ−ｉ、ＰＷ−ｉ、ＤＡ−ｉの出力例を示した。こうして、デジタル映像信号の情報はＢＰＣの出力ＰＷ−ｉのパルス幅に変換される。
【０１００】
ＢＰＣの出力ＰＷ−ｉは、アナログスイッチ群７０５の開閉を制御する。本実施例では、アナログスイッチ群７０５はＢＰＣの出力ＰＷ−ｉがＨｉレベルの間だけオンになり、ＰＷ−ｉがＬｏレベルになるとオフになる。アナログスイッチ群７０５にはカウント信号（Ｃ０〜Ｃ２）に同期した階段状の電圧レベルをもつ階調電源（ＶＲ）が印加されており、ＰＷ−ｉがＬｏレベルになる瞬間の階調電源（ＶＲ）の電圧が後段の信号線選択回路を経由して、信号線に書き込まれる。
【０１０１】
以上の動作により、デジタル映像信号をアナログ映像信号に変換し、信号線を駆動する。なお、階調電源（ＶＲ）は階段状である必要はなく、連続的に単調に変化するものでもよい。また、ビット比較パルス幅変換回路群７０４の出力とアナログスイッチ群７０５の間に、バッファ回路、レベルシフト回路などを入れてもよい。
【０１０２】
以上のように、本発明では、Ｄ／Ａ変換回路としてランプ型Ｄ／Ａ変換回路を用いることもでき、その回路構成は従来の約４分の１で済み、駆動回路の占有面積および、素子数の大幅な削減が可能となる。
【０１０３】
本実施例の構成は、実施例１〜３と自由に組み合わせて実施することが可能である。
【０１０４】
（実施例５）
本実施例では、本発明の画像表示装置の具体的な作製方法例として、アクティブマトリクス型液晶表示装置の作製方法を例に採りあげる。特にここでは、画素部のスイッチング素子である画素ＴＦＴと、画素部の周辺に設けられる駆動回路（信号線駆動回路、走査線駆動回路等）のＴＦＴを同一基板上に作製する方法について工程に従って詳細に説明する。但し、説明を簡単にするために、駆動回路部としてはその基本構成回路であるＣＭＯＳ回路を、画素ＴＦＴ部としてはｎチャネル型ＴＦＴとを図示することにする。
【０１０５】
図１１（Ａ）において、基板（アクティブマトリクス基板）６００１には低アルカリガラス基板や石英基板を用いることができる。本実施例では低アルカリガラス基板を用いた。この場合、ガラス歪み点よりも１０〜２０℃程度低い温度であらかじめ熱処理しておいても良い。この基板６００１のＴＦＴを形成する表面には、基板６００１からの不純物拡散を防ぐために、酸化シリコン膜、窒化シリコン膜または酸化窒化シリコン膜などの下地膜６００２を形成する。例えば、プラズマＣＶＤ法でＳｉＨ₄、ＮＨ₃、Ｎ₂Ｏから作製される酸化窒化シリコン膜を１００ｎｍ、同様にＳｉＨ₄、Ｎ₂Ｏから作製される酸化窒化シリコン膜を２００ｎｍの厚さに積層形成する。
【０１０６】
次に、２０〜１５０ｎｍ（好ましくは３０〜８０ｎｍ）の厚さで非晶質構造を有する半導体膜６００３ａを、プラズマＣＶＤ法やスパッタ法などの公知の方法で形成する。本実施例では、プラズマＣＶＤ法で非晶質シリコン膜を５４ｎｍの厚さに形成した。非晶質構造を有する半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質シリコンゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。また、下地膜６００２と非晶質シリコン膜６００３ａとは同じ成膜法で形成することが可能であるので、両者を連続形成しても良い。その場合、下地膜を形成した後、一旦大気雰囲気に晒さないことでその表面の汚染を防ぐことが可能となり、作製するＴＦＴの特性バラツキやしきい値電圧の変動を低減させることができる（図１１（Ａ））。
【０１０７】
そして、公知の結晶化技術を使用して非晶質シリコン膜６００３ａから結晶質シリコン膜６００３ｂを形成する。例えば、レーザー結晶化法や熱結晶化法（固相成長法）を適用すれば良いが、ここでは、特開平７−１３０６５２号公報で開示された技術に従って、触媒元素を用いる結晶化法で結晶質シリコン膜６００３ｂを形成した。結晶化の工程に先立って、非晶質シリコン膜の含有水素量にもよるが、４００〜５００℃で１時間程度の熱処理を行ない、含有水素量を５atom％以下にしてから結晶化させることが望ましい。非晶質シリコン膜を結晶化させると原子の再配列が起こり緻密化するので、作製される結晶質シリコン膜の厚さは当初の非晶質シリコン膜の厚さ（本実施例では５４ｎｍ）よりも１〜１５％程度減少する（図１１（Ｂ））。
【０１０８】
そして、結晶質シリコン膜６００３ｂを島状にパターンニングして、島状半導体層６００４〜６００７を形成する。その後、プラズマＣＶＤ法またはスパッタ法により５０〜１５０ｎｍの厚さの酸化シリコン膜によるマスク層６００８を形成する。（図１１（Ｃ））。
【０１０９】
そしてレジストマスク６００９を設け、ｎチャネル型ＴＦＴを形成することとなる島状半導体層６００５〜６００７の全面に１×１０¹⁶〜５×１０¹⁷atoms／cm³程度の濃度でｐ型を付与する不純物元素としてボロン（Ｂ）を添加する。このボロン（Ｂ）の添加は、しきい値電圧を制御する目的でなされる。ボロン（Ｂ）の添加はイオンドープ法で実施しても良いし、非晶質シリコン膜を成膜するときに同時に添加しておくこともできる。ここでのボロン（Ｂ）添加は必ずしも必要ではない（図１１（Ｄ））。その後、レジストマスク６００９を除去する。
【０１１０】
駆動回路のｎチャネル型ＴＦＴのＬＤＤ領域を形成するために、ｎ型を付与する不純物元素を島状半導体層６０１０〜６０１２に選択的に添加する。そのため、あらかじめレジストマスク６０１３〜６０１６を形成する。ｎ型を付与する不純物元素としては、リン（Ｐ）や砒素（Ａｓ）を用いれば良く、ここではリン（Ｐ）を添加すべく、フォスフィン（ＰＨ₃）を用いたイオンドープ法を適用した。形成された不純物領域６０１７、６０１８のリン（Ｐ）濃度は２×１０¹⁶〜５×１０¹⁹atoms／cm³の範囲とすれば良い。本明細書中では、ここで形成された不純物領域６０１７〜６０１９に含まれるｎ型を付与する不純物元素の濃度を（ｎ^-）と表す。また、不純物領域６０１９は、画素部の保持容量を形成するための半導体層であり、この領域にも同じ濃度でリン（Ｐ）を添加する（図１２（Ａ））。その後、レジストマスク６０１３〜６０１６を除去する。
【０１１１】
次に、マスク層６００８をフッ酸などにより除去した後、図１１（Ｄ）と図１２（Ａ）で添加した不純物元素を活性化させる工程を行なう。活性化は、５００〜６００℃の窒素雰囲気中で１〜４時間の熱処理や、レーザー活性化の方法により行なうことができる。また、両者を併用しておこなっても良い。本実施例では、レーザー活性化の方法を用いる。レーザー光にはＫｒＦエキシマレーザー光（波長２４８ｎｍ）を用いる。本実施例では、レーザー光の形状を線状ビームに加工して用い、発振周波数５〜５０Ｈｚ、エネルギー密度１００〜５００ｍＪ／ｃｍ²として線状ビームのオーバーラップ割合を８０〜９８％で走査することによって島状半導体層が形成された基板全面を処理する。尚、レーザー光の照射条件には何ら限定される事項はなく適宣決定することができる。
【０１１２】
そして、ゲート絶縁膜６０２０をプラズマＣＶＤ法またはスパッタ法を用いて１０〜１５０ｎｍの厚さでシリコンを含む絶縁膜で形成する。例えば、１２０ｎｍの厚さで酸化窒化シリコン膜を形成する。ゲート絶縁膜には、他のシリコンを含む絶縁膜を単層または積層構造として用いても良い。（図１２（Ｂ））
【０１１３】
次に、ゲート電極を形成するために第１の導電層を成膜する。この第１の導電層は単層で形成しても良いが、必要に応じて二層あるいは三層といった積層構造としても良い。本実施例では、導電性の窒化物金属膜から成る導電層（Ａ）６０２１と金属膜から成る導電層（Ｂ）６０２２とを積層させた。導電層（Ｂ）６０２２はタンタル（Ｔａ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）から選ばれた元素、または前記元素を主成分とする合金か、前記元素を組み合わせた合金膜（代表的にはＭｏ−Ｗ合金膜、Ｍｏ−Ｔａ合金膜）で形成すれば良く、導電層（Ａ）６０２１は窒化タンタル（ＴａＮ）、窒化タングステン（ＷＮ）、窒化チタン（ＴｉＮ）膜、窒化モリブデン（ＭｏＮ）で形成する。また、導電層（Ａ）６０２１は代替材料として、タングステンシリサイド、チタンシリサイド、モリブデンシリサイドを適用しても良い。導電層（Ｂ）は低抵抗化を図るために含有する不純物濃度を低減させると良く、特に酸素濃度に関しては３０ｐｐｍ以下とすると良い。例えば、タングステン（Ｗ）は酸素濃度を３０ｐｐｍ以下とすることで２０μΩｃｍ以下の比抵抗値を実現することができる。
【０１１４】
導電層（Ａ）６０２１は１０〜５０ｎｍ（好ましくは２０〜３０ｎｍ）とし、導電層（Ｂ）６０２２は２００〜４００ｎｍ（好ましくは２５０〜３５０ｎｍ）とすれば良い。本実施例では、導電層（Ａ）６０２１に３０ｎｍの厚さの窒化タンタル膜を、導電層（Ｂ）６０２２には３５０ｎｍのＴａ膜を用い、いずれもスパッタ法で形成した。このスパッタ法による成膜では、スパッタ用のガスのＡｒに適量のＸｅやＫｒを加えておくと、形成する膜の内部応力を緩和して膜の剥離を防止することができる。尚、図示しないが、導電層（Ａ）６０２１の下に２〜２０ｎｍ程度の厚さでリン（Ｐ）をドープしたシリコン膜を形成しておくことは有効である。これにより、その上に形成される導電膜の密着性向上と酸化防止を図ると同時に、導電層（Ａ）または導電層（Ｂ）が微量に含有するアルカリ金属元素がゲート絶縁膜６０２０に拡散するのを防ぐことができる（図１２（Ｃ））。
【０１１５】
次に、レジストマスク６０２３〜６０２７を形成し、導電層（Ａ）６０２１と導電層（Ｂ）６０２２とを一括でエッチングしてゲート電極６０２８〜６０３１と容量配線６０３２を形成する。ゲート電極６０２８〜６０３１と容量配線６０３２は、導電層（Ａ）から成る６０２８ａ〜６０３２ａと、導電層（Ｂ）から成る６０２８ｂ〜６０３２ｂとが一体として形成されている。この時、駆動回路を構成するＴＦＴのゲート電極６０２８〜６０３０は不純物領域６０１７、６０１８の一部と、ゲート絶縁膜６０２０を介して重なるように形成する（図１２（Ｄ））。
【０１１６】
次いで、駆動回路のｐチャネル型ＴＦＴのソース領域およびドレイン領域を形成するために、ｐ型を付与する不純物元素を添加する工程を行なう。ここでは、ゲート電極６０２８をマスクとして、自己整合的に不純物領域を形成する。このとき、ｎチャネル型ＴＦＴが形成される領域はレジストマスク６０３３で被覆しておく。そして、ジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法で不純物領域６０３４を形成した。この領域のボロン（Ｂ）濃度は３×１０²⁰〜３×１０²¹atoms／cm³となるようにする。その後、レジストマスク６０３３を除去する。本明細書中では、ここで形成された不純物領域６０３４に含まれるｐ型を付与する不純物元素の濃度を（ｐ⁺⁺）と表す（図１３（Ａ））。
【０１１７】
次に、ｎチャネル型ＴＦＴにおいて、ソース領域またはドレイン領域として機能する不純物領域の形成を行った。レジストのマスク６０３５〜６０３７を形成し、ｎ型を付与する不純物元素を添加して不純物領域６０３９〜６０４２を形成した。これは、フォスフィン（ＰＨ₃）を用いたイオンドープ法で行ない、この領域のリン（Ｐ）濃度を１×１０²⁰〜１×１０²¹atoms／cm³とした。本明細書中では、ここで形成された不純物領域６０３９〜６０４２に含まれるｎ型を付与する不純物元素の濃度を（ｎ⁺）と表す（図１３（Ｂ））。
【０１１８】
不純物領域６０３９〜６０４２には、既に前工程で添加されたリン（Ｐ）またはボロン（Ｂ）が含まれているが、それに比して十分に高い濃度でリン（Ｐ）が添加されるので、前工程で添加されたリン（Ｐ）またはボロン（Ｂ）の影響は考えなくても良い。また、不純物領域６０３８に添加されたリン（Ｐ）濃度は図１３（Ａ）で添加されたボロン（Ｂ）濃度の１／２〜１／３なのでｐ型の導電性が確保され、ＴＦＴの特性に何ら影響を与えることはなかった。
【０１１９】
レジストマスク６０３５〜６０３７を除去した後、画素部のｎチャネル型ＴＦＴのＬＤＤ領域を形成するためのｎ型を付与する不純物添加の工程を行った。ここではゲート電極６０３１をマスクとして自己整合的にｎ型を付与する不純物元素をイオンドープ法で添加した。添加するリン（Ｐ）の濃度は１×１０¹⁶〜５×１０¹⁸atoms／cm³であり、図１２（Ａ）および図１３（Ａ）と図１３（Ｂ）で添加する不純物元素の濃度よりも低濃度で添加することで、実質的には不純物領域６０４３、６０４４のみが形成される。本明細書中では、この不純物領域６０４３、６０４４に含まれるｎ型を付与する不純物元素の濃度を（ｎ^--）と表す。（図１３（Ｃ））
【０１２０】
その後、それぞれの濃度で添加されたｎ型またはｐ型を付与する不純物元素を活性化するために熱処理工程を行なう。この工程はファーネスアニール法、レーザーアニール法、またはラピッドサーマルアニール法（ＲＴＡ法）で行なうことができる。ここではファーネスアニール法で活性化工程を行った。熱処理は酸素濃度が１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下の窒素雰囲気中で４００〜８００℃、代表的には５００〜６００℃で行なうものであり、本実施例では５００℃で４時間の熱処理を行った。また、基板６００１に石英基板のような耐熱性を有するものを使用した場合には、８００℃で１時間の熱処理としても良く、不純物元素の活性化と、該不純物元素が添加された不純物領域とチャネル形成領域との接合を良好に形成することができる。なお、上述のゲート電極であるＴａのピーリングを防止するために層間膜を形成した場合には、この効果は得られない場合がある。
【０１２１】
この熱処理において、ゲート電極６０２８〜６０３１と容量配線６０３２を形成する金属膜６０２８ｂ〜６０３２ｂは、表面から５〜８０ｎｍの厚さで導電層（Ｃ）６０２８ｃ〜６０３２ｃが形成される。例えば、導電層（Ｂ）６０２８ｂ〜６０３２ｂがタングステン（Ｗ）の場合には窒化タングステン（ＷＮ）が形成され、タンタル（Ｔａ）の場合には窒化タンタル（ＴａＮ）を形成することができる。また、導電層（Ｃ）６０２８ｃ〜６０３２ｃは、窒素またはアンモニアなどを用いた窒素を含むプラズマ雰囲気にゲート電極６０２８〜６０３１及び容量配線６０３２を晒しても同様に形成することができる。さらに、３〜１００％の水素を含む雰囲気中で、３００〜４５０℃で１〜１２時間の熱処理を行ない、島状半導体層を水素化する工程を行った。この工程は熱的に励起された水素により半導体層のダングリングボンドを終端する工程である。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素、プラズマ化した水素を用いる）をおこなっても良い。
【０１２２】
島状半導体層が、非晶質シリコン膜から触媒元素を用いる結晶化の方法で作製された場合、島状半導体層中には微量の触媒元素が残留した。勿論、そのような状態でもＴＦＴを完成させることが可能であるが、残留する触媒元素を少なくともチャネル形成領域から除去する方がより好ましかった。この触媒元素を除去する手段の一つにリン（Ｐ）によるゲッタリング作用を利用する手段があった。ゲッタリングに必要なリン（Ｐ）の濃度は図１３（Ｂ）で形成した不純物領域（ｎ⁺）と同程度であり、ここで実施される活性化工程の熱処理により、ｎチャネル型ＴＦＴおよびｐチャネル型ＴＦＴのチャネル形成領域から触媒元素をゲッタリングすることができた（図１３（Ｄ））。
【０１２３】
活性化および水素化の工程が終了したら、ゲート配線（走査線）とする第２の導電膜を形成する。この第２の導電膜は低抵抗材料であるアルミニウム（Ａｌ）や銅（Ｃｕ）を主成分とする導電層（Ｄ）と、にチタン（Ｔｉ）やタンタル（Ｔａ）、タングステン（Ｗ）、モリブデン（Ｍｏ）から成る導電層（Ｅ）とで形成すると良い。本実施例では、チタン（Ｔｉ）を０．１〜２重量％含むアルミニウム（Ａｌ）膜を導電層（Ｄ）６０４５とし、チタン（Ｔｉ）膜を導電層（Ｅ）６０４６として形成した。導電層（Ｄ）６０４５は２００〜４００ｎｍ（好ましくは２５０〜３５０ｎｍ）とすれば良く、導電層（Ｅ）６０４６は５０〜２００（好ましくは１００〜１５０ｎｍ）で形成すれば良い。（図１４（Ａ））
【０１２４】
そして、ゲート電極に接続するゲート配線（走査線）を形成するために導電層（Ｅ）６０４６と導電層（Ｄ）６０４５とをエッチング処理して、ゲート配線（走査線）６０４７、６０４８と容量配線６０４９を形成した。エッチング処理は最初にＳｉＣｌ₄とＣｌ₂とＢＣｌ₃との混合ガスを用いたドライエッチング法で導電層（Ｅ）の表面から導電層（Ｄ）の途中まで除去し、その後リン酸系のエッチング溶液によるウエットエッチングで導電層（Ｄ）を除去することにより、下地との選択加工性を保ってゲート配線（走査線）を形成することができた。
【０１２５】
第１の層間絶縁膜６０５０は５００〜１５００ｎｍの厚さで酸化シリコン膜または酸化窒化シリコン膜で形成され、その後、それぞれの島状半導体層に形成されたソース領域またはドレイン領域に達するコンタクトホールを形成し、ソース配線（信号線）６０５１〜６０５４と、ドレイン配線６０５５〜６０５８を形成する。図示していないが、本実施例ではこの電極を、Ｔｉ膜を１００ｎｍ、Ｔｉを含むアルミニウム膜３００ｎｍ、Ｔｉ膜１５０ｎｍをスパッタ法で連続して形成した３層構造の積層膜とした。
【０１２６】
次に、パッシベーション膜６０５９として、窒化シリコン膜、酸化シリコン膜、または窒化酸化シリコン膜を５０〜５００ｎｍ（代表的には１００〜３００ｎｍ）の厚さで形成する。この状態で水素化処理を行なうとＴＦＴの特性向上に対して好ましい結果が得られた。例えば、３〜１００％の水素を含む雰囲気中で、３００〜４５０℃で１〜１２時間の熱処理を行なうと良く、あるいはプラズマ水素化法を用いても同様の効果が得られた。なお、ここで後に画素電極とドレイン配線を接続するためのコンタクトホールを形成する位置において、パッシベーション膜６０５９に開口部を形成しておいても良い。（図１４（Ｃ））
【０１２７】
その後、有機樹脂からなる第２の層間絶縁膜６０６０を１．０〜１．５μｍの厚さに形成する。有機樹脂としては、ポリイミド、アクリル、ポリアミド、ポリイミドアミド、ＢＣＢ（ベンゾシクロブテン）等を使用することができる。ここでは、基板に塗布後、熱重合するタイプのポリイミドを用い、３００℃で焼成して形成した。そして、第２の層間絶縁膜６０６０にドレイン配線６０５８に達するコンタクトホールを形成し、画素電極６０６１、６０６２を形成する。画素電極は、透過型液晶表示装置とする場合には透明導電膜を用いれば良く、反射型の液晶表示装置とする場合には金属膜を用いれば良い。本実施例では透過型の液晶表示装置とするために、酸化インジウム・スズ（ＩＴＯ）膜を１００ｎｍの厚さにスパッタ法で形成した。（図１５）
【０１２８】
こうして同一基板上に、駆動回路のＴＦＴと画素部の画素ＴＦＴとを有した基板を完成させることができた。駆動回路にはｐチャネル型ＴＦＴ６１０１、第１のｎチャネル型ＴＦＴ６１０２、第２のｎチャネル型ＴＦＴ６１０３、画素部には画素ＴＦＴ６１０４、保持容量６１０５が形成した。本明細書では便宜上このような基板をアクティブマトリクス基板と呼ぶ。
【０１２９】
駆動回路のｐチャネル型ＴＦＴ６１０１には、島状半導体層６００４にチャネル形成領域６１０６、ソース領域６１０７ａ、６１０７ｂ、ドレイン領域６１０８ａ、６１０８ｂを有している。第１のｎチャネル型ＴＦＴ６１０２には、島状半導体層６００５にチャネル形成領域６１０９、ゲート電極６０２９と重なるＬＤＤ領域６１１０（以降、このようなＬＤＤ領域をＬovと記す）、ソース領域６１１１、ドレイン領域６１１２を有している。このＬov領域のチャネル長方向の長さは０．５〜３．０μｍ、好ましくは１．０〜１．５μｍとした。第２のｎチャネル型ＴＦＴ６１０３には、島状半導体層６００６にチャネル形成領域６１１３、ＬＤＤ領域６１１４、６１１５、ソース領域６１１６、ドレイン領域６１１７を有している。このＬＤＤ領域はＬov領域とゲート電極６０３０と重ならないＬＤＤ領域（以降、このようなＬＤＤ領域をＬoffと記す）とが形成され、このＬoff領域のチャネル長方向の長さは０．３〜２．０μｍ、好ましくは０．５〜１．５μｍである。画素ＴＦＴ６１０４には、島状半導体層６００７にチャネル形成領域６１１８、６１１９、Ｌoff領域６１２０〜６１２３、ソースまたはドレイン領域６１２４〜６１２６を有している。Ｌoff領域のチャネル長方向の長さは０．５〜３．０μｍ、好ましくは１．５〜２．５μｍである。さらに、容量配線６０３２、６０４９と、ゲート絶縁膜と同じ材料から成る絶縁膜と、画素ＴＦＴ６１０４のドレイン領域６１２６に接続し、ｎ型を付与する不純物元素が添加された半導体層６１２７とから保持容量６１０５が形成されている。図１５では画素ＴＦＴ６１０４をダブルゲート構造としたが、シングルゲート構造でも良いし、複数のゲート電極を設けたマルチゲート構造としても差し支えない。
【０１３０】
以上のように本実施例では、画素ＴＦＴおよび駆動回路が要求する仕様に応じて各回路を構成するＴＦＴの構造を最適化し、画像表示装置の動作性能と信頼性を向上させることを可能とすることができる。
【０１３１】
次に、上記の工程によって作製されたアクティブマトリクス基板をもとに、透過型液晶表示装置を作製する工程を説明する。
【０１３２】
図１６を参照する。図１５の状態のアクティブマトリクス基板に配向膜６２０１を形成する。本実施例では、配向膜６２０１にはポリイミドを用いた。次に、対向基板を用意する。対向基板は、ガラス基板６２０２、遮光膜６２０３、透明導電膜からなる対向電極６２０４、配向膜６２０５とで構成される。
【０１３３】
なお、本実施例では、配向膜には、液晶分子が基板に対して平行に配向するようなポリイミド膜を用いた。なお、配向膜形成後、ラビング処理を施すことにより、液晶分子がある一定のプレチルト角を持って平行配向するようにした。
【０１３４】
次に、上記の工程を経たアクティブマトリクス基板と対向基板とを公知のセル組み工程によって、シール材やスペーサ（共に図示せず）などを介して貼り合わせる。その後、両基板の間に液晶６２０６を注入し、封止剤（図示せず）によって完全に封止する。よって、図１６に示すような透過型液晶表示装置が完成する。
【０１３５】
なお、上記の行程により作製されるＴＦＴはトップゲート構造であるが、ボトムゲート構造のＴＦＴやその他の構造のＴＦＴに対しても本発明は適用され得る。
【０１３６】
また、上記の行程により作製される画像表示装置は透過型の液晶表示装置であるが、本発明は反射型の液晶表示装置に対しても適用され得る。
【０１３７】
本実施例の構成は、実施例１〜４と自由に組み合わせて実施することが可能である。
【０１３８】
（実施例６）
本発明の画像表示装置を用いた電子機器として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。それら電子機器の具体例を図１７に示す。
【０１３９】
図１７（Ａ）は液晶表示装置であり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明の画像表示装置は表示部２００３に用いることができる。なお、液晶表示装置は、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用表示装置が含まれる。
【０１４０】
図１７（Ｂ）はデジタルスチルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明の画像表示装置は表示部２１０２に用いることができる。
【０１４１】
図１７（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明の画像表示装置は表示部２２０３に用いることができる。
【０１４２】
図１７（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明の画像表示装置は表示部２３０２に用いることができる。
【０１４３】
図１７（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明の画像表示装置はこれら表示部Ａ、Ｂ２４０３、２４０４に用いることができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【０１４４】
図１７（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明の画像表示装置は表示部２５０２に用いることができる。
【０１４５】
図１７（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９等を含む。本発明の画像表示装置は表示部２６０２に用いることができる。
【０１４６】
ここで図１７（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明の画像表示装置は表示部２７０３に用いることができる。
【０１４７】
次に、本発明の画像表示装置を用いたプロジェクター（リア型またはフロント型）について説明する。それらの一例を図１８及び図１９に示す。
【０１４８】
図１８（Ａ）はフロント型プロジェクターであり、光源光学系及び表示部７６０１、スクリーン７６０２で構成される。本発明は表示部７６０１に適用することができる。
【０１４９】
図１８（Ｂ）はリア型プロジェクターであり、本体７７０１、光源光学系及び表示部７７０２、ミラー７７０３、ミラー７７０４、スクリーン７７０５で構成される。本発明は表示部７７０２に適用することができる。
【０１５０】
なお、図１８（Ｃ）は、図１８（Ａ）及び図１８（Ｂ）中における光源光学系及び表示部７６０１、７７０２の構造の一例を示した図である。光源光学系及び表示部７６０１、７７０２は、光源光学系７８０１、ミラー７８０２、７８０４〜７８０６、ダイクロイックミラー７８０３、光学系７８０７、表示部７８０８、位相差板７８０９、投射光学系７８１０で構成される。投射光学系７８１０は、投射レンズを備えた複数の光学レンズで構成される。この構成は、表示部７８０８を三つ使用しているため三板式と呼ばれている。また、図１８（Ｃ）中において矢印で示した光路に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するためのフィルム、ＩＲフィルム等を設けてもよい。
【０１５１】
また、図１８（Ｄ）は、図１８（Ｃ）中における光源光学系７８０１の構造の一例を示した図である。本実施例では、光源光学系７８０１は、リフレクター７８１１、光源７８１２、レンズアレイ７８１３、７８１４、偏光変換素子７８１５、集光レンズ７８１６で構成される。なお、図１８（Ｄ）に示した光源光学系は一例であって、この構成に限定されない。例えば、光源光学系に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するフィルム、ＩＲフィルム等を設けてもよい。
【０１５２】
図１８（Ｃ）は三板式の例を示したが、図１９（Ａ）は単板式の一例を示した図である。図１９（Ａ）に示した光源光学系及び表示部は、光源光学系７９０１、表示部７９０２、投射光学系７９０３、位相差板７９０４で構成される。投射光学系７９０３は、投射レンズを備えた複数の光学レンズで構成される。図１９（Ａ）に示した光源光学系及び表示部は図１８（Ａ）及び図１８（Ｂ）中における光源光学系及び表示部７６０１、７７０２に適用できる。また、光源光学系７９０１は図１８（Ｄ）に示した光源光学系を用いればよい。なお、表示部７９０２にはカラーフィルター（図示しない）が設けられており、表示映像をカラー化している。
【０１５３】
また、図１９（Ｂ）に示した光源光学系及び表示部は、図１９（Ａ）の応用例であり、カラーフィルターを設ける代わりに、ＲＧＢの回転カラーフィルター円板７９０５を用いて表示映像をカラー化している。図１９（Ｂ）に示した光源光学系及び表示部は図１８（Ａ）及び図１８（Ｂ）中における光源光学系及び表示部７６０１、７７０２に適用できる。
【０１５４】
また、図１９（Ｃ）に示した光源光学系及び表示部は、カラーフィルターレス単板式と呼ばれている。この方式は、表示部７９１６にマイクロレンズアレイ７９１５を設け、ダイクロイックミラー（緑）７９１２、ダイクロイックミラー（赤）７９１３、ダイクロイックミラー（青）７９１４を用いて表示映像をカラー化している。投射光学系７９１７は、投射レンズを備えた複数の光学レンズで構成される。図１９（Ｃ）に示した光源光学系及び表示部は図１８（Ａ）及び図１８（Ｂ）中における光源光学系及び表示部７６０１、７７０２に適用できる。また、光源光学系７９１１としては、光源の他に結合レンズ、コリメータレンズを用いた光学系を用いればよい。
【０１５５】
以上の様に、本発明の画像表示装置の適用範囲は極めて広く、あらゆる分野の電子機器に適用することが可能である。また、本実施例の電子機器は実施例１〜５のどのような組み合わせからなる構成を用いても実現することができる。
【０１５６】
【発明の効果】
本発明は上記構成により、信号線駆動回路内の回路素子の数を従来例のｎ分の１にすることが可能である。よって、信号線駆動回路の面積を大幅に縮小でき、画像表示装置の小型化に有効であり、さらには、画像表示装置のコスト低減、歩留まり向上に効果がある。また、階調の異なる画素の水平方向における位置が変わるため、フレーム周波数を変えなくとも人間の目に縦縞が視認されにくくなる。
【図面の簡単な説明】
【図１】 本発明の信号線駆動回路の構成を示す図。
【図２】 本発明の信号線駆動回路のタイミングチャートを示す図。
【図３】 アナログ映像信号を画素に入力する順序を示す模式図。
【図４】 信号線選択回路の回路図及びタイミングチャート。
【図５】 本発明の画像表示装置のブロック図。
【図６】 記憶回路の具体例を示す図。
【図７】 本発明の信号線駆動回路の構成を示す図。
【図８】 ビット比較パルス幅変換回路（ＢＰＣ）の構成を示す図。
【図９】 図７の駆動回路のタイミングチャートを示す図。
【図１０】 ランプ型Ｄ／Ａ変換回路の動作を説明する図。
【図１１】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１２】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１３】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１４】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１５】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１６】 実施例３によるアクティブマトリクス型液晶表示装置の作製工程例を示す図。
【図１７】 本発明を用いた電子機器の一例を示す図。
【図１８】 投影型液晶表示装置の構成を示す図。
【図１９】 投影型液晶表示装置の構成を示す図。
【図２０】 アクティブマトリクス型液晶表示装置の構成図。
【図２１】 従来のデジタル方式の信号線駆動回路の構成図。
【図２２】 従来のデジタル方式の信号線駆動回路のタイミングチャート。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method of an image display device for inputting a digital video signal, and relates to an image display device using the driving method. Furthermore, the present invention relates to an electronic device using the image display device.
[0002]
[Prior art]
In recent years, research and development of thin film transistors (TFTs) using a polycrystalline silicon film as an active layer have been actively conducted. A TFT using a polycrystalline silicon film has a mobility that is two orders of magnitude higher than that of a TFT using an amorphous silicon film. Enough can be secured. Therefore, it is possible to realize a system-on-panel in which a pixel portion of an active matrix flat panel display and a driving circuit thereof are integrally formed on the same substrate.
[0003]
Realization of the system-on-panel enables cost reduction by reducing the assembly process and inspection process of the display, and also enables miniaturization and high definition of the flat panel display.
[0004]
By the way, there are a drive circuit of an image display device that is driven using an analog video signal and a drive circuit that is driven using a digital video signal. A driving circuit driven using a digital video signal can input digital broadcasting radio waves into the driving circuit as they are without converting them into analog, and is promising because it can handle recent digital broadcasting. Has been.
[0005]
FIG. 20 shows a general configuration of an active matrix liquid crystal display device which is a kind of active matrix image display device driven using a digital video signal. As shown in FIG. 20, the liquid crystal display device includes a signal line driver circuit 9001, a scanning line driver circuit 9002, a pixel portion 9003, a signal line 9004, a scanning line 9005, a pixel TFT 9006, a liquid crystal cell 9007, and the like. A liquid crystal cell 9007 includes a pixel electrode, a counter electrode, and liquid crystal provided between the pixel electrode and the counter electrode.
[0006]
A detailed configuration of the signal line driver circuit 9001 is shown in FIG. FIG. 22 is a timing chart in the signal line driver circuit shown in FIG. Here, an image display apparatus having k (horizontal) × l (vertical) pixels will be described as an example. In order to make the explanation easy to understand, the case where the digital video signal is 3 bits is exemplified, but the number of bits is not limited to 3 in an actual image display apparatus. In FIG. 21 and FIG. 22, k = 640 is shown using specific numerical values.
[0007]
A general signal line driver circuit mainly includes a shift register 9100, first and second memory circuit groups 9101 and 9102, and a D / A conversion circuit group 9103. The shift register 9100 includes a plurality of delay flip-flops (DFF). The first memory circuit group 9101 and the second memory circuit group 9102 each include a plurality of first memory circuits and a plurality of second memory circuits. In FIG. 21, a first latch (LAT1) is used as the first memory circuit, and a second latch (LAT2) is used as the second memory circuit. The D / A conversion circuit group 9103 has a plurality of D / A conversion circuits (DACs).
[0008]
The shift register 9100 sequentially shifts the pulses of the output signal in accordance with the input signal line driver circuit clock signal (S-CLK) and the signal line driver circuit start pulse (S-SP). The first memory circuit group 9101 sequentially stores digital video signals in synchronization with the output signal of the shift register 9100. The second memory circuit group 9102 stores the output of the first memory circuit group 9101 in synchronization with the latch pulse. The D / A conversion circuit group 9103 converts the output signal of the second memory circuit group 9102 into an analog signal.
[0009]
Hereinafter, a more detailed configuration and operation of the signal line driving circuit will be described. The number of DFF stages in the shift register 9101 described above (corresponding to the number of DFFs shown in FIG. 21) is k + 1 because the number of pixels in the horizontal direction is k. A control signal (SR-001 to SR-640 in FIG. 21) which is an output signal of the shift register has a pulse shifted by one cycle of S-CLK as shown in FIG. The control signals (SR-001 to SR-640) are input to the first latch (LAT1) of the first memory circuit group 9101 directly or through a buffer.
[0010]
The first latch (LAT1) stores the input 3-bit digital video signal (D0 to D2) in synchronization with the control signal. By shifting the pulse of the control signal output from the shift register 9100 by the same number as the number k of pixels for one line, the digital video signal corresponding to the pixels for one line is stored in the first latch (LAT1). Is done. Therefore, the first latch (LAT1) requires 3 (the number of bits of the digital video signal) × k (the number of pixels in the horizontal direction).
[0011]
Next, during the blanking period, the second latch (LAT2) of the second memory circuit group 9102 is operated by the input latch pulse (LP) and stored in the first latch (LAT1). Digital video signals (L1-001 to L1-640 in FIGS. 21 and 22) are stored in the second latch (LAT2). Therefore, the second latch (LAT2) also needs 3 × k. In FIG. 21, L1-001 to L1-640 are shown with numbers for each corresponding pixel without distinguishing the number of bits.
[0012]
When the blanking period ends and the next horizontal scanning period starts, the shift register 9100 starts operating again to output a control signal, and the digital video signal (D0 to D2) is input to the first latch (LAT1). Be started. On the other hand, the digital video signals (L2-001 to L2-640) stored in the second latch (LAT2) are converted into analog signals in the D / A conversion circuit (DAC) of the D / A conversion circuit group 9103. The analog video signals are input to the source signal lines (S1 to S640). This analog video signal is written to the pixel electrode of the liquid crystal cell when the pixel TFT of each pixel is turned on.
[0013]
With the above operation, the image display apparatus performs display.
[0014]
[Problems to be solved by the invention]
The digital driving circuit that performs the above operation has a drawback that its occupied area is very large compared to the analog driving circuit. The digital method has an advantage that the signal can be expressed by binary values of “Hi” or “Lo”, but instead, the amount of data becomes enormous, and the number of circuit elements increases because the data is processed. Therefore, an increase in the area occupied by the drive circuit on the substrate cannot be suppressed, which is a major obstacle to miniaturization of the image display device.
[0015]
In recent years, with the rapid increase in the amount of information to be handled, the number of pixels has been increased and the definition of pixels has been increased. However, as the number of pixels increases, the number of circuit elements included in the drive circuit also increases, and the area of the drive circuit is expected to increase.
[0016]
Here, an example of a display resolution of a commonly used computer is shown below by the number of pixels and the standard name.
Number of pixels Standard name
640 × 480 VGA
800 × 600 SVGA
1024 x 768 XGA
1280 × 1024 SXGA
1600 × 1200 UXGA
[0017]
For example, in the case of the SXGA standard, when the number of bits is 8, in the conventional driving circuit described above, there are 10240 (8 × 1280) first memory circuits and second memory circuits for 1280 signal lines. I need it. In addition, high-definition television receivers such as high-definition TV (HDTV) have become widespread, and high-definition images have become necessary not only in the computer world but also in the AV field. In the United States, terrestrial digital broadcasting begins, and in Japan, the era of digital broadcasting will begin. In digital broadcasting, the standard of 1920 × 1080 pixels is prominent, and reduction of the driving circuit is urgently required.
[0018]
However, as described above, the area occupied by the signal line driver circuit is large, which hinders downsizing of the image display device. In order to solve such a problem, the present invention provides a technique advantageous in reducing the area occupied by a signal line driving circuit and reducing the size.
[0019]
[Means for Solving the Problems]
In view of the above problems, the present invention shares n memory circuits and D / A conversion circuits in a signal line driver circuit with n (n is a natural number of 2 or more) signal lines. Then, one horizontal scanning period is divided into n pieces, and in each divided period, the memory circuit and the D / A conversion circuit perform processing on different signal lines, so that within one horizontal scanning period, Video signals can be input to all signal lines. Thus, the number of memory circuits and D / A conversion circuits in the signal line driver circuit can be reduced to 1 / n of the conventional example.
[0020]
Further, in the present invention, the order of inputting the video signals to the n signal lines is changed every horizontal scanning period or every plural horizontal scanning periods.
[0021]
Adjacent signal lines are capacitively coupled directly or indirectly. Therefore, when a video signal is written to one signal line, the potential held in the signal line adjacent to the signal line is affected and changes. That is, the signal line to which the video signal is first written tends to change due to the influence of the writing of the signal line to which the video signal is written later.
[0022]
Therefore, if the order of inputting video signals is fixed, only the potential of a specific signal line always deviates from its ideal value. And in the pixel connected to the signal line whose potential has changed, the relative gradation expression is always different from the pixel connected to the other signal line, and vertical stripes parallel to the signal line are visually recognized by human eyes. Will be.
[0023]
However, in the present invention, since the position in the horizontal direction of the pixel modulated by the write potential changes every fixed period (specifically, every horizontal scanning period or every horizontal scanning period), Vertical stripes are difficult to see.
[0024]
Note that the order of signal lines for inputting video signals may be random or have a certain regularity. The order may not be changed every horizontal scanning period, and the order may be changed every two horizontal scanning periods or every more horizontal scanning periods. However, it is important to set the number of horizontal scanning periods to such an extent that vertical stripes are not easily recognized by human eyes. When the frame frequency is increased, vertical stripes are difficult to see. Therefore, it is preferable to set the number of horizontal scanning periods for changing the order in consideration of the frame frequency.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. Here, an image display apparatus in which the number of pixels in the horizontal and vertical directions is generally set to k and l will be described as an example. In this embodiment, a case where the digital video signal is 3 bits will be described. However, the present invention is not limited to 3 bits, and can be applied to 6 bits, 8 bits, or other numbers of bits. In the following description, n is used as a parameter indicating the number of signal lines sharing one D / A conversion circuit. However, when the horizontal pixel count k is not a multiple of n, a new pixel is added. Appropriately added, the number of pixels in the horizontal direction is set to a multiple k ′ of n larger than k. In this case, the pixel number k ′ may be newly defined as k. If the added pixels are handled as virtual ones, there will be no trouble in actual operation.
[0026]
FIG. 1 shows a configuration of the signal line driver circuit of this embodiment mode, and FIG. 2 shows a timing chart thereof. However, FIGS. 1 and 2 show specific examples in which the number of pixels in the horizontal direction k = 640. In the following, symbols such as k are used for general explanation, but specific numbers in the case of k = 640 are shown in []. Although FIG. 1 shows the case of n = 4, n is not limited to this value as long as n is a natural number of 2 or more.
[0027]
The signal line driver circuit of this embodiment includes a shift register 101 including a plurality of delay flip-flops (DFFs), a first memory circuit group 102 including a plurality of first memory circuits, and a plurality of second memory circuits. A signal line selection circuit having a second memory circuit group 103 having a memory circuit, a D / A conversion circuit group 104 having a plurality of D / A conversion circuits (DAC), and a plurality of signal line selection circuits (SEL). Group 105. In FIG. 1, the first latch (LAT1) is used as the first memory circuit, and the second latch (LAT2) is used as the second memory circuit. In FIG. 1, unlike the image display device shown in FIG. 21, two types of latch signal lines (LPa, LPb) are supplied, and the first half (1 to 80 [1-k / 2n] stages of the second memory circuit is provided. The first latch signal line (LPa) is connected to the second DFF (LAT2 corresponding to the DFF in the 81st to 160 [1+ (k / 2n) to k / n) stages). Latch signal lines (LPb) are connected to each other. In the present invention, the number of latch signal lines may be one.
[0028]
Specifically, in FIG. 1, the shift register 101 includes (k / n) +1 stage [161 stage] of DFF, 3k / n each of the first memory circuit (LAT1) and the second memory circuit (LAT2). [480] and D / A conversion circuits (DACs) are composed of k / n [160]. As can be seen from FIG. 1, the number of circuits constituting the signal line driver circuit is about 1 / n [1/4] of the signal line driver circuit shown in FIG.
[0029]
Next, the operation will be described with reference to FIG. The shift register 101 receives a signal line driver circuit start pulse (S-SP) and a signal line driver circuit clock signal (S-CLK). In FIG. 22, the S-SP pulse appears once in one horizontal scanning period, whereas it appears n times [4 times] in this embodiment. Similarly to FIG. 22, the shift register 101 sequentially shifts the pulses of the output signal according to the input S-SP and S-CLK. The output signal is input to the first memory circuit (LAT1) as a control signal [SR-001 to SR-160].
[0030]
In synchronization with the control signal pulse output from the shift register 101, the digital video signals (D0 to D2) are sequentially stored in the first memory circuit (LAT1). The number of DFF stages is about 1 / n [1/4] of FIG. 21, and in the present invention, the first memory circuit performs n [4 times] memory operations during one horizontal scanning period. . In FIG. 1, the digital video signals L1-001 to L1-160 input from the first memory circuit group 102 to the second memory circuit group 103 are associated with the corresponding signal lines without distinguishing the number of bits. The numbers are indicated with numbers.
[0031]
Unlike FIG. 21, each of the digital video signals L1-001 to L1-160 corresponds to n signal lines. For example, in FIG. 2, the digital video signal L1-001 sequentially corresponds to the signal lines S1 to Sn [S1 to S4]. Similarly, when the digital video signals L1-001 to L1-160 are represented by corresponding signal line numbers, S1 to Sn, Sn + 1 to S2n, S2n + 1 to S3n,..., Sk-n + 1 to Sk [S1 to S4. , S5 to S8, S9 to S12,..., S637 to S640].
[0032]
In one horizontal scanning period, the digital video signal L1-i (i = 1 to 160) outputs information on the corresponding n signal lines, but the order of the corresponding signal lines is not necessarily fixed. In the present invention, the order in which the digital video signals L1-i (i = 1 to 160) are output with respect to the signal lines is changed every horizontal scanning period. In other words, the order of the signal lines corresponding to each of the digital video signals L1-001 to L1-160 is changed for each horizontal scanning period. This order is realized by converting the data arrangement of the digital video signals (D0 to D2) so as to be the same as the selection order of the signal lines of the signal line selection circuit described later.
[0033]
The latch pulses input to the second memory circuit group 103 via two types of latch signal lines (LPa, LPb) in one horizontal scanning period are n in total, and 2n [8] pulses in total. Appear. The latch pulse is input not only during the blanking period but also during the period during which the digital video signal is input.
[0034]
In this embodiment, after the writing of the digital video signal corresponding to the previous signal line to the first memory circuit (LAT1) at the (k / 2n) -th stage [80th stage] is completed, A latch pulse is input to the first latch signal line (LPa) before the data written in the first memory circuit (LAT1) of the eye is rewritten to a digital video signal corresponding to the next signal line. Further, after the writing of the digital video signal corresponding to the previous signal line to the first memory circuit (LAT1) at the (k / n) -th stage [160th stage] is completed, (k / 2n) +1 Before the data written in the first memory circuit (LAT1) of the stage [81th stage] is rewritten to the digital video signal corresponding to the next signal line, the latch pulse is supplied to the second latch signal line (LPb). ).
[0035]
That is, when the writing of the digital video signal to the first memory circuit in the first half is completed, the writing of the digital video signal to the first memory circuit in the second half is started. While the digital video signal is written to the first memory circuit in the second half, the digital video signal written in the first memory circuit in the first half is transferred to the second memory circuit in the first half. . When the writing of the digital video signal to the first storage circuit in the second half is completed, the writing of the next digital video signal to the first storage circuit in the first half is started. While the digital video signal is written to the first memory circuit in the first half, the digital video signal written in the first memory circuit in the second half is transferred to the second memory circuit in the second half. .
[0036]
Through these operations, digital video signals corresponding to the respective signal lines are sequentially transferred to the second memory circuit group 103.
[0037]
Although FIG. 1 shows an example in which two latch pulse lines are provided and the latch pulse is input 2n times [8 times] in one horizontal scanning period, the present invention is not limited to this configuration. All the second memory circuits (LAT2) may be connected to one latch pulse line. In this case, it is necessary to provide a blanking period every time the shift register 101 completes one scan, and to interrupt writing of the digital video signal to the first storage circuit in the blanking period. In the blanking period, transfer is performed from all the first memory circuits (LAT1) to all the second memory circuits (LAT2). The latch pulse is input n times [4 times] during one horizontal scanning period.
[0038]
The 3-bit digital video signal output from the second memory circuit (LAT2) is input to the D / A conversion circuit (DAC) and converted into an analog video signal. Note that a buffer circuit, a level shift circuit, an enable circuit for limiting an output period, or the like may be provided between the second memory circuit and the D / A converter circuit. The converted analog video signal is written to an appropriate signal line via a signal line selection circuit (SEL) included in the signal line selection circuit group 105.
[0039]
The timing at which the analog video signal is written to an appropriate signal line by the signal line selection circuit (SEL) is determined by the timing at which the latch pulse is input. Corresponding to the shift register scanning n times within one horizontal scanning period, the second memory circuit repeats the memory operation n times as described above. Therefore, while the digital video signal corresponding to a certain signal line is stored in the second memory circuit, the analog video signal output from the D / A conversion circuit (DAC) is selected and written. Must be completed.
[0040]
The input of the analog video signal from the signal line selection circuit (SEL) to the signal line is performed in synchronization with the pulse of the selection signal input to the signal line selection circuit (SEL). The pulse of the selection signal appears n times in one horizontal scanning period.
[0041]
In the present invention, the order in which analog video signals of n signal lines are input is changed for each horizontal scanning period or for each of a plurality of horizontal scanning periods. The selection order of the signal lines is controlled by selection signals SS1 to SS4 [SS1 to SSn] input to the signal line selection circuit (SEL).
[0042]
The order of the signal lines for inputting the analog video signal may be random or may have a certain regularity. The order may not be changed every horizontal scanning period, and the order may be changed every two horizontal scanning periods or every more horizontal scanning periods. For example, the order may be changed for each frame period. However, it is important to set the number of horizontal scanning periods to such an extent that vertical stripes are not easily recognized by human eyes. When the frame frequency is increased, vertical stripes are difficult to see. Therefore, it is preferable to set the number of horizontal scanning periods for changing the order in consideration of the frame frequency.
[0043]
Table 1 shows the selection order of the signal lines of the present embodiment.
[0044]
[Table 1]

[0045]
When signal lines are selected in the order shown in Table 1, the order in which analog video signals are written to pixels is schematically shown in FIG. For comparison, FIG. 3B schematically shows a general order in which analog video signals are written to pixels.
[0046]
As shown in FIG. 3A, when the signal lines are selected in the order shown in Table 1, the signal line to which the analog video signal is first written differs for each horizontal scanning period. On the other hand, as shown in FIG. 3B, when the selection order of the signal lines is fixed, the analog video signal is always written to the same signal line first in each horizontal scanning period.
[0047]
Therefore, in the driving method shown in Table 1, even if the potential of the signal line to which the video signal is first written changes, the horizontal position of the pixel to which the modulated potential is written is changed every horizontal scanning period. Therefore, it is difficult for human eyes to visually recognize vertical stripes. Note that in the driving example of FIG. 3A, the signal line to which the analog video signal is first written may be different for each of a plurality of horizontal scanning periods.
[0048]
Note that the selection order of the signal lines of the present invention is not limited to the order shown in Table 1. As shown in Table 1, it may have a certain regularity or may be random. Table 2 shows an example of the signal line selection order of the present invention, which is different from Table 1.
[0049]
[Table 2]

[0050]
In Table 2, unlike Table 1, the number of the signal line selected first is different for each horizontal scanning period, and all the signal lines are always selected first in any horizontal scanning period. Yes. In the above configuration, since the first selected period is provided for all the signal lines, the vertical stripes are less visible even when the frame frequency is the same as in the driving method of Table 1.
[0051]
Alternatively, the signal line selection order may be changed for each horizontal scanning period or for each of a plurality of horizontal scanning periods, and the signal line selection order may be changed for each frame period. For example, the signal lines may be selected in the order shown in Table 1 in the previous frame period, and the signal lines may be selected in the order shown in Table 2 in the next frame period. With this configuration, vertical stripes are less likely to be visually recognized even if the frame frequency is the same as compared with a driving method in which the order is simply changed every horizontal scanning period.
[0052]
In the embodiment of the present invention, a signal line driving circuit (so-called digital signal line driving circuit) that inputs a digital video signal and outputs an analog video signal corresponding to each signal line is shown as an example. However, the present invention is not limited to this. For example, a signal line driving circuit (so-called analog signal line driving circuit) that inputs an analog video signal and outputs an analog video signal corresponding to each signal line may be used.
[0053]
According to the present invention, the number of circuit elements in the signal line driver circuit can be reduced to 1 / n of the conventional example. In addition, since the horizontal positions of pixels having different gradations change, it is difficult for human eyes to visually recognize vertical stripes without changing the frame frequency.
[0054]
In the description of the above embodiment, a shift register is used as a circuit for controlling the first memory circuit. However, a decoder circuit may be used instead of the shift register. The D / A conversion circuit may be a lamp type D / A conversion circuit. In that case, the number of D / A conversion circuits is not limited to k / n.
[0055]
【Example】
Examples of the present invention will be described below.
[0056]
(Example 1)
In this embodiment, a detailed configuration of a signal line selection circuit used in the image display apparatus of the present invention will be described.
[0057]
FIG. 4A shows a circuit diagram of the signal line selection circuit (SEL) of this embodiment. In this embodiment, n is used as a parameter indicating the number of signal lines sharing one D / A conversion circuit. However, FIG. 4 shows a case where one DAC corresponds to four signal lines for the sake of simplicity. In the following, n is used for general description, but specific numbers in the case of n = 4 are shown in [].
[0058]
In this embodiment, the analog switch has a p-channel transistor and an n-channel transistor. However, the present invention is not limited to this, and may be an analog switch using only a p-channel transistor or an analog switch using only an n-channel transistor.
[0059]
The signal line driver circuit (SEL) of this embodiment includes n [4] analog switches 400_1 to 400_n [400_1 to 400_4]. A selection signal for controlling switching is input to each analog switch.
[0060]
A selection signal for controlling switching is input to the analog switches 400_1 to 400_n [400_1 to 400_4] through the selection signal line. Selection signals having different potentials are input to each analog switch, and a selection signal line is provided for each analog switch.
[0061]
In this embodiment, the analog switch includes a p-channel transistor and an n-channel transistor, and a signal obtained by inverting the polarity of the selection signal is also input to the analog switch. Therefore, in this embodiment, the selection signals SS1 to SSn [SS1 to SS4] and the signals SSb1 to SSbn [SSb1 to SSb4] obtained by inverting the polarity of each selection signal are input to each analog switch. In this embodiment, signals obtained by inverting the polarity of the selection signal are collectively referred to as selection signals.
[0062]
FIG. 4B shows a timing chart of the selection signal when the signal lines Si to S (i + n−1) [S (i + 3)] are selected. Since the selection signals SSb1 to SSb4 are obtained by inverting the polarity of the selection signals SS1 to SS4, only the selection signals SS1 to SS4 are shown here.
[0063]
In FIG. 4B, n [4] signal lines Si, S (i + 1), S (i + 2), S (i + n−1) [S (i + 3)] connected to the same DAC are shown in Table 1 below. An example of selection in the order shown in FIG. Note that the selection order of the signal lines in this embodiment is not limited to the order shown in Table 1.
[0064]
First, when the horizontal scanning period is started, the signal line Si is selected in synchronization with the pulses of the selection signals SS1 and SSb1. Then, the analog video signal output from the DAC is input to the signal line Si via the analog switch 400_1.
[0065]
Similarly, the signal lines S (i + 1) to S (i + n-1) [S (i + 3)] are sequentially synchronized with the pulses of the selection signals SS2 to SSn [SS2 to SS4] and SSb2 to SSbn [SS2 to SS4]. Is selected. Then, the analog video signal output from the DAC is input to the signal lines S (i + 1) to S (i + 3) via the analog switches 400_2 to 400_4 [400_n].
[0066]
When one horizontal scanning period ends and the next horizontal scanning period starts, the signal line S (i + n-1) [S (i + 3)] is synchronized with the pulses of the selection signals SSn, SSbn [SS4, SSb4]. Is selected. Then, the analog video signal output from the DAC is input to the signal line S (i + n−1) [S (i + 3)] via the analog switch 400_n [400_4].
[0067]
Similarly, in synchronization with the pulses of the selection signals SS (n−1) to SS1 [SS3 to SS1] and SSb (n−1) to SSb1 [SS (n−1) to SS1], the signal lines S ( i + n-2) to Si [S (i + 2) to Si] are selected. Then, the analog video signal output from the DAC is input to the signal lines S (i + 2) to Si via the analog switches 400_ (n−1) [400_3] to 400_1.
[0068]
As described above, the selection order of the signal lines can be controlled by the selection signal.
[0069]
(Example 2)
In this embodiment, the configuration of the controller of the image display apparatus of the present invention that generates various signals related to driving will be described.
[0070]
FIG. 5 is a block diagram showing the configuration of the image display apparatus of this embodiment. Reference numeral 500 denotes a pixel portion, 501 denotes a signal line driver circuit, and 502 denotes a scanning line driver circuit. A signal line selection circuit group 503 is included in the signal line drive circuit 501.
[0071]
Reference numeral 504 denotes a controller having various circuits. Specifically, it mainly includes a buffer 505, a display memory 506, a timing generation circuit 507, a selection circuit timing generation circuit 508, and a format circuit 509. In addition, a bias voltage generation circuit, a serial interface, or the like may be provided.
[0072]
The controller 504 mainly receives a video signal (Video Signals), a reference clock signal (Dot CLK), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync).
[0073]
The video signal is amplified or buffer amplified in the buffer 505 and written in the display memory 506. Note that it is not always necessary to amplify or buffer the video signal in the buffer 505, and it is not essential to provide the buffer 505.
[0074]
Further, the reference clock signal, the horizontal synchronization signal (Hsync), and the vertical synchronization signal (Vsync) are input to the timing generation circuit 507. In this embodiment, the reference clock signal is input from the outside of the image display device, but this embodiment is not limited to this configuration. The reference clock signal may be generated based on the horizontal synchronization signal (Hsync) input to the image display device without inputting the reference clock signal from the outside.
[0075]
The timing generation circuit 507 generates signals for determining the operation timing of various circuits in accordance with the input reference clock signal, horizontal synchronization signal (Hsync), and vertical synchronization signal (Vsync).
[0076]
Specifically, a clock signal (S-CLK) and a start pulse signal (S-SP) for the signal line driver circuit 501 and a clock signal (G-CLK) and a start pulse signal (G for the scan line driver circuit 502 are displayed. -SP) is generated in the timing generation circuit 507.
[0077]
Further, the timing generation circuit 507 determines the timing for writing the video signal to the display memory 506 and the timing for inputting the video signal held in the display memory 506 to the format circuit 509.
[0078]
In addition, a timing for selecting a signal line in the signal line selection circuit group 503 is determined in the timing generation circuit 507. Since n signal lines are selected in each horizontal scanning period, the signal line selection timing appears n times in each horizontal scanning period. However, n means the number of signal lines sharing one DAC. A signal for determining the timing for selecting the signal line is input from the timing generation circuit 507 to the selection circuit timing generation circuit 508.
[0079]
The selection circuit timing generation circuit 508 includes a selection signal generation circuit 510 that generates a selection signal, and a selection order determination register 511 in which data in the selection order of signal lines is stored. The selection signal generation circuit 510 receives a signal for determining the timing for selecting a signal line from the timing generation circuit 507. The selection signal generation circuit 510 receives data in the selection order of the signal lines from the selection order determination register 511.
[0080]
The selection signal generation circuit 510 generates the selection signals SS1 to SSn based on the data in the selection order of the signal lines and a signal that determines the selection timing of the signal lines that appear n times. Each of the selection signals SS1 to SSn appears once in one horizontal scanning period. A signal line is selected in synchronization with the pulse.
[0081]
On the other hand, data in the selection order of the signal lines stored in the selection order determination register 511 is also sent to the format circuit 509. The video signals input to the format circuit 509 are rearranged according to the data in the selection order of the signal lines, and input to the first memory circuit group (not shown) of the signal line driver circuit 501. Note that in the format unit 509, the video signal may be serial-parallel converted and divided into a plurality of parts before being input to a first memory circuit group (not shown).
[0082]
In FIG. 5, the timing generation circuit 507 and the selection circuit timing generation circuit 508 are distinguished from each other, but the selection circuit timing generation circuit 508 may be regarded as a part of the timing generation circuit 507. 5 shows the display memory 506 as a part of the controller 504, the display memory 506 may be separated from the controller 504.
[0083]
In FIG. 5, the display memory is connected only to the controller 504 and is independent of a system bus managed by a CPU (not shown), but this embodiment is not limited to this configuration. The CPU and the controller 504 may share the same display memory.
[0084]
In addition, the signal line selection order data stored in the selection order determination register 511 may be fixed data determined by the design of a mask or the like, or data that can be rewritten by a CPU, a dip switch, or the like. It may be.
[0085]
The configuration of this embodiment can be implemented by freely combining with the first embodiment.
[0086]
(Example 3)
In this embodiment, specific structures of the first and second memory circuits used in the signal line driver circuit of the present invention will be described.
[0087]
A specific example of the memory circuit is shown in FIG. 6A uses a clocked inverter, FIG. 6B shows an SRAM type, and FIG. 6C shows a DRAM type. These are representative examples, and the present invention is not limited to these forms.
[0088]
The control signal 2 corresponds to a signal obtained by inverting the polarity of the control signal 1. In the case of the second memory circuit, a latch pulse is input to the control signal.
[0089]
The configuration of this embodiment can be implemented by freely combining with the first or second embodiment.
[0090]
Example 4
In this embodiment, a configuration of a signal line driver circuit when a lamp type D / A converter circuit is adopted as the D / A converter circuit will be described.
[0091]
FIG. 7 shows a schematic diagram of a signal line driving circuit in the case where a lamp type D / A conversion circuit is used. In the present embodiment, a case where an XGA standard image display apparatus supports a 3-bit digital video signal will be described. However, the present invention is not limited to 3 bits, and the case where the number of other bits is supported or other than XGA. It is also effective for standard image display devices.
[0092]
In this embodiment, the structures and operations of the shift register 701, the first memory circuit group 702, the second memory circuit group 703, and the signal line selection circuit group 706 are the same as those in the embodiment mode. This embodiment is different from the embodiment in that a bit comparison pulse width conversion circuit group 704 and an analog switch group 705 are provided in the lower stage of the second memory circuit 703. Two circuits of the bit comparison pulse width conversion circuit group 704 and the analog switch group 705 function as a ramp type D / A conversion circuit.
[0093]
In this embodiment, the bit comparison pulse width conversion circuit group is provided with 256 bit comparison pulse width conversion circuits (BPC). The 3-bit digital video signal, count signal (C0 to C2), and set signal (ST) stored in the second memory circuit group 703 are input to the BPC.
[0094]
The analog switch group 705 is provided with 256 analog switches (ASW) in this embodiment. The analog switch group 705 receives the output of the bit comparison pulse width conversion circuit group 704 (PW-i, i is 001 to 256) and the gradation power supply (VR). The signal line selection circuit group 706 receives the output of the analog switch group 705 and the selection signals (SS1 to SS4).
[0095]
The configuration of the i-th stage BPC is illustrated in FIG. The BPC has an exclusive OR gate, a 3-input NAND gate, an inverter, and a set-reset flip-flop (RS-FF). In FIG. 8, the output of the second memory circuit at the i-th stage is distinguished from the bit, and L2-i (0), L2-i (1) L2-i (2) (the parentheses indicate the bit numbers). It was.
[0096]
Next, the operation of the signal line driving circuit of this embodiment will be described. FIG. 9 shows a timing chart of a signal system necessary for understanding the outline of the circuit operation of FIG. The operation from the shift register 701 to the second memory circuit group 703 is also the same as that of the signal line driver circuit described in the embodiment mode. The selection signals (SS1 to SS4) input to the signal line selection circuit group 706 are the same as those in the signal line driver circuit shown in FIG. 2 of the embodiment.
[0097]
In FIG. 9, every time four signal lines are sequentially selected by the signal line selection circuit group 706, a count signal (C0 to C2), a set signal (ST), and a gradation power supply (VR) are periodically input. Is done. As a result, information can be equally written to all the signal lines.
[0098]
In order to explain the detailed operation of the ramp type D / A conversion circuit, FIG. 10 shows a timing chart during a period in which one of the four signal lines is selected by the signal line selection circuit.
[0099]
First, in synchronization with the pulse of the set signal, the RS-FF 30 is set and the output PW-i becomes Hi level. Next, the digital video signal stored in the second memory circuit group 703 is compared bit by bit with the count signal (C0 to C2) by the exclusive OR gate. When all three bits match, the outputs of all the exclusive OR gates become Hi level, and as a result, the output (inverted RC-i) of the three-input NAND gate becomes Lo level (thus, RC- i becomes Hi level). The output of the three-input NAND is also input to the RS-FF 30 and reset when RC-i becomes Hi level, and the output PW-i returns to Lo level. FIG. 10 shows RC-i, PW- when the 3-bit digital video signal {L2-i (0), L2-i (1) L2-i (2)} is {0, 0, 1}. The output example of i and DA-i is shown. Thus, the information of the digital video signal is converted into the pulse width of the BPC output PW-i.
[0100]
The BPC output PW-i controls the opening and closing of the analog switch group 705. In this embodiment, the analog switch group 705 is turned on only while the BPC output PW-i is at the Hi level, and is turned off when the PW-i is at the Lo level. A gradation power supply (VR) having a stepped voltage level synchronized with the count signals (C0 to C2) is applied to the analog switch group 705, and the gradation power supply (VR) at the moment when PW-i becomes Lo level. ) Is written to the signal line via the signal line selection circuit in the subsequent stage.
[0101]
Through the above operation, the digital video signal is converted into an analog video signal, and the signal line is driven. Note that the gradation power supply (VR) does not have to be stepped, and may continuously change monotonously. Further, a buffer circuit, a level shift circuit, or the like may be inserted between the output of the bit comparison pulse width conversion circuit group 704 and the analog switch group 705.
[0102]
As described above, in the present invention, a ramp type D / A conversion circuit can also be used as the D / A conversion circuit, and the circuit configuration is about one-fourth that of the conventional circuit. The number can be greatly reduced.
[0103]
The structure of a present Example can be implemented in combination freely with Examples 1-3.
[0104]
(Example 5)
In this embodiment, a method for manufacturing an active matrix liquid crystal display device is taken as an example as a specific method for manufacturing the image display device of the present invention. In particular, here, a method for manufacturing a pixel TFT which is a switching element of the pixel portion and a TFT of a driver circuit (a signal line driver circuit, a scanning line driver circuit, etc.) provided around the pixel portion on the same substrate is described in detail according to the process. Explained. However, in order to simplify the description, a CMOS circuit, which is a basic configuration circuit, is illustrated as the drive circuit unit, and an n-channel TFT is illustrated as the pixel TFT unit.
[0105]
In FIG. 11A, a low alkali glass substrate or a quartz substrate can be used as the substrate (active matrix substrate) 6001. In this example, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 6001 where a TFT is formed in order to prevent impurity diffusion from the substrate 6001. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film made from O is 100 nm, similarly SiH _Four , N ₂ A silicon oxynitride film formed from O is stacked to a thickness of 200 nm.
[0106]
Next, a semiconductor film 6003a having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 54 nm by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Further, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, they may be formed continuously. In that case, after the base film is formed, it is possible to prevent contamination of the surface by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics and threshold voltage of the TFT to be manufactured (see FIG. 11 (A)).
[0107]
Then, a crystalline silicon film 6003b is formed from the amorphous silicon film 6003a using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. Here, in accordance with the technique disclosed in Japanese Patent Laid-Open No. 7-130552, the crystallization method using a catalytic element is used for crystallization. A quality silicon film 6003b was formed. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen to 5 atom% or less before crystallization. desirable. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the amorphous silicon film is densified. Therefore, the thickness of the crystalline silicon film to be produced is larger than the initial thickness of the amorphous silicon film (54 nm in this embodiment). Is also reduced by about 1 to 15% (FIG. 11B).
[0108]
Then, the crystalline silicon film 6003b is patterned into an island shape to form island-like semiconductor layers 6004 to 6007. Thereafter, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 150 nm is formed by plasma CVD or sputtering. (FIG. 11C).
[0109]
Then, a resist mask 6009 is provided, and 1 × 10 6 is formed on the entire surface of the island-like semiconductor layers 6005 to 6007 where n-channel TFTs are to be formed. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three Boron (B) is added as an impurity element imparting p-type at a moderate concentration. The boron (B) is added for the purpose of controlling the threshold voltage. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. The addition of boron (B) here is not always necessary (FIG. 11D). Thereafter, the resist mask 6009 is removed.
[0110]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layers 6010 to 6012. Therefore, resist masks 6013 to 6016 are formed in advance. As the impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, phosphorous (PH) is added to add phosphorus (P). _Three ) Was applied. The formed impurity regions 6017 and 6018 have a phosphorus (P) concentration of 2 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It may be in the range. In this specification, the concentration of an impurity element imparting n-type contained in the impurity regions 6017 to 6019 formed here is defined as (n ^- ). The impurity region 6019 is a semiconductor layer for forming a storage capacitor of the pixel portion, and phosphorus (P) is added to this region at the same concentration (FIG. 12A). Thereafter, the resist masks 6013 to 6016 are removed.
[0111]
Next, after removing the mask layer 6008 with hydrofluoric acid or the like, a step of activating the impurity element added in FIGS. 11D and 12A is performed. The activation can be performed by a heat treatment for 1 to 4 hours in a nitrogen atmosphere at 500 to 600 ° C. or a laser activation method. Moreover, you may carry out using both together. In this embodiment, a laser activation method is used. As the laser light, KrF excimer laser light (wavelength 248 nm) is used. In this embodiment, the shape of the laser beam is processed into a linear beam, and the oscillation frequency is 5 to 50 Hz, and the energy density is 100 to 500 mJ / cm. ² As described above, the entire surface of the substrate on which the island-shaped semiconductor layer is formed is processed by scanning the linear beam with an overlap ratio of 80 to 98%. Note that the laser light irradiation conditions are not limited and can be appropriately determined.
[0112]
Then, the gate insulating film 6020 is formed with an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 12 (B))
[0113]
Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this example, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film were laminated. The conductive layer (B) 6022 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, a Mo—W alloy film or a Mo—Ta alloy film). The conductive layer (A) 6021 is a tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 6021 as an alternative material. In the conductive layer (B), it is preferable to reduce the concentration of impurities contained in order to reduce resistance, and in particular, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0114]
The conductive layer (A) 6021 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 6022 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is used for the conductive layer (A) 6021 and a 350 nm Ta film is used for the conductive layer (B) 6022, both of which are formed by sputtering. In film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 6020. Can be prevented (FIG. 12C).
[0115]
Next, resist masks 6023 to 6027 are formed, and the conductive layers (A) 6021 and (B) 6022 are etched together to form gate electrodes 6028 to 6031 and capacitor wirings 6032. The gate electrodes 6028 to 6031 and the capacitor wiring 6032 are integrally formed of 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, the gate electrodes 6028 to 6030 of the TFTs constituting the driver circuit are formed so as to overlap part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween (FIG. 12D).
[0116]
Next, a step of adding an impurity element imparting p-type is performed in order to form a source region and a drain region of the p-channel TFT of the driver circuit. Here, impurity regions are formed in a self-aligning manner using the gate electrode 6028 as a mask. At this time, a region where the n-channel TFT is formed is covered with a resist mask 6033. And diborane (B ₂ H ₆ An impurity region 6034 was formed by an ion doping method using). The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three To be. Thereafter, the resist mask 6033 is removed. In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 6034 formed here (p ⁺⁺ ) (FIG. 13A).
[0117]
Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and an impurity element imparting n-type conductivity was added to form impurity regions 6039 to 6042. This is the phosphine (PH _Three ), And the phosphorus (P) concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three It was. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6039 to 6042 formed here is defined as (n ⁺ ) (FIG. 13B).
[0118]
The impurity regions 6039 to 6042 already contain phosphorus (P) or boron (B) added in the previous step, but phosphorus (P) is added at a sufficiently higher concentration than that. The influence of phosphorus (P) or boron (B) added in the previous step may not be considered. Further, since the phosphorus (P) concentration added to the impurity region 6038 is 1/2 to 1/3 of the boron (B) concentration added in FIG. 13A, p-type conductivity is ensured, and TFT characteristics are obtained. It had no effect on.
[0119]
After removing the resist masks 6035 to 6037, an impurity addition step for imparting n-type for forming an LDD region of the n-channel TFT in the pixel portion was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) to be added is 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three By adding the impurity element at a concentration lower than that of the impurity element added in FIGS. 12A, 13A, and 13B, substantially only the impurity regions 6043 and 6044 are formed. The In this specification, the concentration of an impurity element imparting n-type contained in the impurity regions 6043 and 6044 is defined as (n ^- ). (Fig. 13 (C))
[0120]
Thereafter, a heat treatment step is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment is performed at 400 to 800 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. went. Further, in the case where a substrate 6001 having heat resistance such as a quartz substrate is used, heat treatment may be performed at 800 ° C. for 1 hour, and activation of the impurity element, impurity region to which the impurity element is added, and A junction with the channel formation region can be formed satisfactorily. Note that this effect may not be obtained when an interlayer film is formed in order to prevent the peeling of Ta, which is the gate electrode.
[0121]
In this heat treatment, conductive films (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface of the metal films 6028b to 6032b forming the gate electrodes 6028 to 6031 and the capacitor wiring 6032. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) can be formed, and when tantalum (Ta) is used, tantalum nitride (TaN) can be formed. The conductive layers (C) 6028c to 6032c can be formed in the same manner even when the gate electrodes 6028 to 6031 and the capacitor wiring 6032 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogenated plasma) may be performed.
[0122]
In the case where the island-shaped semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalytic element, a trace amount of the catalytic element remained in the island-shaped semiconductor layer. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. As one of means for removing the catalyst element, there is a means for utilizing the gettering action by phosphorus (P). The concentration of phosphorus (P) necessary for gettering is the impurity region (n) formed in FIG. ⁺ The catalytic element could be gettered from the channel formation region of the n-channel TFT and the p-channel TFT by the heat treatment in the activation process performed here (FIG. 13D). .
[0123]
When the activation and hydrogenation steps are completed, a second conductive film is formed as a gate wiring (scanning line). This second conductive film includes a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low resistance material, and titanium (Ti), tantalum (Ta), tungsten (W), molybdenum. It is good to form with the conductive layer (E) which consists of (Mo). In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is formed as the conductive layer (D) 6045, and a titanium (Ti) film is formed as the conductive layer (E) 6046. The conductive layer (D) 6045 may be 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 6046 may be 50 to 200 (preferably 100 to 150 nm). (Fig. 14 (A))
[0124]
Then, in order to form a gate wiring (scanning line) connected to the gate electrode, the conductive layer (E) 6046 and the conductive layer (D) 6045 are etched, and the gate wiring (scanning lines) 6047 and 6048 and the capacitor wiring are formed. 6049 was formed. The etching process starts with SiCl _Four And Cl ₂ And BCl _Three The conductive layer (E) is removed from the surface of the conductive layer (E) to the middle of the conductive layer (D) by a dry etching method using a mixed gas and then the conductive layer (D) is removed by wet etching with a phosphoric acid-based etching solution. As a result, the gate wiring (scanning line) can be formed while maintaining the selective processability with the base.
[0125]
The first interlayer insulating film 6050 is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 500 to 1500 nm, and then a contact hole reaching the source region or the drain region formed in each island-shaped semiconductor layer is formed. Then, source wirings (signal lines) 6051 to 6054 and drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.
[0126]
Next, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed as the passivation film 6059 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment was performed in this state, a favorable result was obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 6059 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (Figure 14 (C))
[0127]
Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film having a thickness of 100 nm is formed by sputtering to form a transmissive liquid crystal display device. (Fig. 15)
[0128]
In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion on the same substrate was completed. A p-channel TFT 6101, a first n-channel TFT 6102, and a second n-channel TFT 6103 are formed in the driver circuit, and a pixel TFT 6104 and a storage capacitor 6105 are formed in the pixel portion. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0129]
The p-channel TFT 6101 of the driver circuit includes a channel formation region 6106, source regions 6107a and 6107b, and drain regions 6108a and 6108b in an island-shaped semiconductor layer 6004. In the first n-channel TFT 6102, an LDD region 6110 that overlaps the island-shaped semiconductor layer 6005 with the channel formation region 6109 and the gate electrode 6029 (hereinafter, such an LDD region is referred to as Lov), a source region 6111, and a drain region 6112. have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 has a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. The LDD region is formed with an LDD region that does not overlap the Lov region and the gate electrode 6030 (hereinafter, such LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3-2. It is 0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 6104 has channel formation regions 6118 and 6119, Loff regions 6120 to 6123, and source or drain regions 6124 to 6126 in an island-shaped semiconductor layer 6007. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 6105 includes capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 6127 which is connected to the drain region 6126 of the pixel TFT 6104 and to which an impurity element imparting n-type conductivity is added. Is formed. Although the pixel TFT 6104 has a double gate structure in FIG. 15, it may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.
[0130]
As described above, in this embodiment, the structure of the TFT constituting each circuit is optimized according to the specifications required by the pixel TFT and the drive circuit, and the operation performance and reliability of the image display apparatus can be improved. be able to.
[0131]
Next, a process of manufacturing a transmissive liquid crystal display device based on the active matrix substrate manufactured by the above process will be described.
[0132]
Refer to FIG. An alignment film 6201 is formed on the active matrix substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 6201. Next, a counter substrate is prepared. The counter substrate includes a glass substrate 6202, a light shielding film 6203, a counter electrode 6204 made of a transparent conductive film, and an alignment film 6205.
[0133]
In this embodiment, a polyimide film in which liquid crystal molecules are aligned in parallel to the substrate is used for the alignment film. Note that after the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.
[0134]
Next, the active matrix substrate and the counter substrate that have undergone the above-described steps are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling step. Thereafter, liquid crystal 6206 is injected between both the substrates and completely sealed with a sealant (not shown). Therefore, a transmissive liquid crystal display device as shown in FIG. 16 is completed.
[0135]
Although the TFT manufactured by the above process has a top gate structure, the present invention can be applied to a TFT having a bottom gate structure and other structures.
[0136]
The image display device manufactured by the above process is a transmissive liquid crystal display device, but the present invention can also be applied to a reflective liquid crystal display device.
[0137]
The structure of a present Example can be implemented in combination freely with Examples 1-4.
[0138]
(Example 6)
As an electronic device using the image display device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device , A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a recording medium such as a digital video disc (DVD), etc.) And the like). Specific examples of these electronic devices are shown in FIGS.
[0139]
FIG. 17A illustrates a liquid crystal display device which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The image display device of the present invention can be used for the display portion 2003. The liquid crystal display device includes all display devices for information display such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.
[0140]
FIG. 17B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The image display device of the present invention can be used for the display portion 2102.
[0141]
FIG. 17C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The image display device of the present invention can be used for the display portion 2203.
[0142]
FIG. 17D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The image display device of the present invention can be used for the display portion 2302.
[0143]
FIG. 17E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the image display device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0144]
FIG. 17F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The image display device of the present invention can be used for the display portion 2502.
[0145]
FIG. 17G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The image display device of the present invention can be used for the display portion 2602.
[0146]
Here, FIG. 17H shows a cellular phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The image display device of the present invention can be used for the display portion 2703.
[0147]
Next, a projector (rear type or front type) using the image display device of the present invention will be described. Examples of these are shown in FIGS.
[0148]
FIG. 18A illustrates a front projector, which includes a light source optical system and display portion 7601 and a screen 7602. The present invention can be applied to the display portion 7601.
[0149]
FIG. 18B shows a rear projector, which includes a main body 7701, a light source optical system and display portion 7702, a mirror 7703, a mirror 7704, and a screen 7705. The present invention can be applied to the display portion 7702.
[0150]
Note that FIG. 18C illustrates an example of the structure of the light source optical system and the display portions 7601 and 7702 in FIGS. 18A and 18B. The light source optical system and display units 7601 and 7702 are composed of a light source optical system 7801, mirrors 7802 and 7804 to 7806, a dichroic mirror 7803, an optical system 7807, a display unit 7808, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration is called a three-plate type because three display portions 7808 are used. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG.
[0151]
FIG. 18D illustrates an example of the structure of the light source optical system 7801 in FIG. In this embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, lens arrays 7813 and 7814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system illustrated in FIG. 18D is an example, and the present invention is not limited to this structure. For example, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system.
[0152]
FIG. 18C shows an example of a three-plate type, while FIG. 19A shows an example of a single-plate type. The light source optical system and display unit shown in FIG. 19A includes a light source optical system 7901, a display unit 7902, a projection optical system 7903, and a phase difference plate 7904. The projection optical system 7903 is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and display portion shown in FIG. 19A can be applied to the light source optical system and display portions 7601 and 7702 in FIGS. 18A and 18B. Further, the light source optical system 7901 may be the light source optical system shown in FIG. Note that the display portion 7902 is provided with a color filter (not shown) to colorize the display image.
[0153]
The light source optical system and display unit shown in FIG. 19B is an application example of FIG. 19A. Instead of providing a color filter, a display image is displayed using an RGB rotating color filter disc 7905. Colored. The light source optical system and display portion shown in FIG. 19B can be applied to the light source optical system and display portions 7601 and 7702 in FIGS. 18A and 18B.
[0154]
The light source optical system and the display portion shown in FIG. 19C are called a color filterless single plate type. In this method, a micro lens array 7915 is provided in a display portion 7916, and a display image is colored using a dichroic mirror (green) 7912, a dichroic mirror (red) 7913, and a dichroic mirror (blue) 7914. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and display portion shown in FIG. 19C can be applied to the light source optical system and display portions 7601 and 7702 in FIGS. 18A and 18B. As the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.
[0155]
As described above, the application range of the image display device of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-5.
[0156]
【The invention's effect】
According to the present invention, the number of circuit elements in the signal line driver circuit can be reduced to 1 / n of the conventional example. Therefore, the area of the signal line driver circuit can be greatly reduced, which is effective for downsizing the image display device, and further, it is effective in reducing the cost of the image display device and improving the yield. In addition, since the horizontal positions of pixels having different gradations change, it is difficult for human eyes to visually recognize vertical stripes without changing the frame frequency.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a signal line driver circuit of the present invention.
FIG. 2 is a timing chart of a signal line driver circuit of the present invention.
FIG. 3 is a schematic diagram showing an order of inputting analog video signals to pixels.
FIG. 4 is a circuit diagram and a timing chart of a signal line selection circuit.
FIG. 5 is a block diagram of an image display device of the present invention.
FIG. 6 illustrates a specific example of a memory circuit.
FIG. 7 is a diagram showing a configuration of a signal line driver circuit of the present invention.
FIG. 8 is a diagram showing a configuration of a bit comparison pulse width conversion circuit (BPC).
9 is a timing chart of the drive circuit in FIG.
FIG. 10 is a diagram for explaining the operation of a lamp type D / A conversion circuit.
11 is a diagram showing a manufacturing process example of an active matrix liquid crystal display device according to Embodiment 3; FIG.
12 is a diagram showing a manufacturing process example of an active matrix liquid crystal display device according to Embodiment 3. FIG.
13 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device according to Embodiment 3. FIG.
14 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to Embodiment 3. FIG.
15 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to Example 3. FIG.
16 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to Example 3. FIG.
FIG. 17 illustrates an example of an electronic device using the invention.
FIG. 18 is a diagram showing a configuration of a projection type liquid crystal display device.
FIG. 19 is a diagram showing a configuration of a projection type liquid crystal display device.
FIG. 20 is a configuration diagram of an active matrix liquid crystal display device.
FIG. 21 is a configuration diagram of a conventional digital signal line driver circuit.
FIG. 22 is a timing chart of a conventional digital signal line driver circuit.

Claims (6)

A signal line driver circuit; k signal lines (k is a natural number); a plurality of scanning lines; and a plurality of pixels.
Each of the plurality of pixels receives an analog video signal from any one of the k signal lines when any one of the plurality of scanning lines is selected.
The k signal lines are divided into n (n is a natural number) k / n blocks,
The signal line driving circuit includes:
Corresponding to each of the k / n blocks,
a first latch for storing a digital video signal of m bits (m is a natural number);
A second latch for storing an m-bit output signal of the first latch;
A D / A conversion circuit for converting an m-bit output signal of the second latch into an analog video signal;
A signal line selection circuit,
The signal line selection circuit has an analog switch. By switching the analog switch n times, n signal lines included in each block of the k / n blocks are selected one by one, and n signal lines are selected. The analog video signal is output to the signal line of
In one horizontal scanning period, any one of the plurality of scanning lines is selected, and the analog switch of the signal line selection circuit corresponding to the k / n blocks is simultaneously switched n times, thereby causing one time. Each time it is switched, an analog video signal is output to the k / n signal lines, and an analog video signal is output to the k signal lines.
The order in which the n signal lines are selected in each of the k / n blocks is different from each other in the horizontal scanning period that appears consecutively.
A first latch pulse is input to the second latch corresponding to the first to k / 2n-th blocks of the k / n blocks, and the first latch pulse causes the first latch pulse to be input. An m-bit output signal of one latch is transferred to the second latch;
A second latch pulse is input to the second latch corresponding to the (k / 2n + 1) th block to the k / nth block among the k / n blocks, and the second latch is input. An image display apparatus, wherein an m-bit output signal of the first latch is transferred to the second latch by a pulse. A signal line driver circuit, a controller, k (k is a natural number) signal lines, a plurality of scanning lines, and a plurality of pixels .
Each of the plurality of pixels receives an analog video signal from any one of the k signal lines when any one of the plurality of scanning lines is selected.
The k signal lines are divided into n (n is a natural number) k / n blocks,
The signal line driving circuit includes:
Corresponding to each of the k / n blocks,
a first latch for storing a digital video signal of m bits (m is a natural number);
A second latch for storing an m-bit output signal of the first latch ;
A D / A converter circuit for converting an output signal of the m bits of said second latch to an analog video signal,
And a signal Route selection circuit,
The signal line selection circuit includes an analog switch. By switching the analog switch n times, n signal lines included in each block of the k / n blocks are selected one by one, and n signal lines are selected. The analog video signal is output to the signal line of
In one horizontal scanning period, one of the plurality of scanning lines is selected, and the analog switch of the signal line selection circuit corresponding to the k / n blocks is switched n times at a time. Each time switching is performed, an analog video signal is output to the k / n signal lines, and an analog video signal is output to the k signal lines.
The order in which the n signal lines are selected in each of the k / n blocks is determined by a selection signal generated in the controller, and is different from each other in horizontal scanning periods that appear successively,
Of the k / n blocks, a first latch pulse is input to the second latch corresponding to the first block to the k / 2n-th block, and the first latch pulse causes the first latch pulse to be input. An m-bit output signal of one latch is transferred to the second latch;
A second latch pulse is input to the second latch corresponding to the (k / 2n + 1) th block to the k / nth block among the k / n blocks, and the second latch is input. An image display device, wherein an m-bit output signal of the first latch is transferred to the second latch by a pulse. In claim 1 or claim 2 ,
The image display device, wherein the first latch and the second latch are configured using a clocked inverter. In claim 1 or claim 2 ,
The image display device, wherein the first latch and the second latch are configured using an analog switch and a plurality of inverters. In any one of claims 1 to 4,
2. The image display device according to claim 1, wherein the signal line driving circuit is formed using a polysilicon thin film transistor. An electronic apparatus using the image display device according to any one of claims 1 to 5 .

Images