JP4157449B2 - 高周波用モジュール - Google Patents
高周波用モジュール Download PDFInfo
- Publication number
- JP4157449B2 JP4157449B2 JP2003334386A JP2003334386A JP4157449B2 JP 4157449 B2 JP4157449 B2 JP 4157449B2 JP 2003334386 A JP2003334386 A JP 2003334386A JP 2003334386 A JP2003334386 A JP 2003334386A JP 4157449 B2 JP4157449 B2 JP 4157449B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency module
- substrate
- power transistor
- power
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
2 誘電体基板
3 ストリップ線路
4 接続導体
5 導体層
6 電力用トランジスタ
7 受動素子部品
8 チップ部品
9 出力検知制御部品
10 放熱用ビアホール
11 凹部
Claims (6)
- 誘電体基板表面に、複数段のパワーアンプによって構成された電力用トランジスタを実装してなるとともに、該電力用トランジスタ実装部の直下の基板内に、基板表面側から基板裏面に貫通して複数の放熱体を設けてなる高周波モジュールにおいて、前記電力用トランジスタが、該パワーアンプのうち、最終段パワーアンプの直下に設けた放熱体の最小径を、他の放熱体の最小径よりも大きくしたことを特徴とする高周波モジュール。
- 前記最終段パワーアンプの直下に設けた放熱体の最小径が、他の放熱体の径の1.2倍以上であることを特徴とする請求項1記載の高周波モジュール。
- 前記放熱体が、ビアホール形状を有することを特徴とする請求項1記載の高周波モジュール。
- 前記誘電体層の熱伝導率が20W/m・K以下であることを特徴とする請求項1記載の高周波モジュール。
- 前記電力用トランジスタは、前記誘電体基板表面または裏面に形成された凹部に収納されていることを特徴とする請求項1記載の高周波モジュール。
- 前記誘電体基板上に、弾性表面波素子部品、FBAR、アンテナスイッチ部品の群から選ばれる少なくとも1種の受動部品が実装されてなることを特徴とする請求項1記載の高周波モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003334386A JP4157449B2 (ja) | 2003-09-25 | 2003-09-25 | 高周波用モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003334386A JP4157449B2 (ja) | 2003-09-25 | 2003-09-25 | 高周波用モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005101364A JP2005101364A (ja) | 2005-04-14 |
JP4157449B2 true JP4157449B2 (ja) | 2008-10-01 |
Family
ID=34462089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003334386A Expired - Fee Related JP4157449B2 (ja) | 2003-09-25 | 2003-09-25 | 高周波用モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4157449B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101598200B1 (ko) * | 2014-07-10 | 2016-02-26 | 광운대학교 산학협력단 | Iii-v족 화합물 반도체 소자 패키지 및 그 제조 방법 |
US10229864B1 (en) * | 2017-09-14 | 2019-03-12 | Northrop Grumman Systems Corporation | Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias |
-
2003
- 2003-09-25 JP JP2003334386A patent/JP4157449B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2005101364A (ja) | 2005-04-14 |
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