JP4127452B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology that is effective for use in a semiconductor integrated circuit device including a dynamic RAM (Random Access Memory) incorporating a boosted voltage generation circuit.
[0002]
[Prior art]
For example, JP-A-3-214669 discloses a dynamic RAM including a pumping circuit for generating a substrate back bias voltage and a boosted voltage. The pumping circuit (charge pump circuit) for generating the substrate back bias voltage and the boosted voltage in this publication is composed of a main circuit and a sub circuit, and the sub circuit has only a small current supply capability to compensate for leakage current and the like. The
[Problems to be solved by the invention]
[0003]
In recent years, in semiconductor integrated circuits such as memories and microprocessors, a positive and negative charge pump circuit is often provided in a chip in order to make a user-friendly external single power supply and improve device performance. However, in the address selection MOSFET constituting the memory cell in the dynamic RAM, it is difficult to lower the threshold voltage in accordance with the scaling law because the subthreshold current is increased and the information holding time is shortened. Therefore, the voltage to be generated in the charge pump circuit even if the element is miniaturized, in other words, the selection level of the address selection MOSFET cannot be lowered in proportion to the element size, and is close to the element breakdown voltage. Ensuring the reliability of these elements is an important issue.
[0004]
FIG. 10 shows a booster circuit studied prior to the present invention. In this circuit, after precharging the capacitors CB1, CB2, and CB4 to VDD, the nodes N1 and N2 are set to VDD. At this time, the charge of the capacitor CB2 passes through the MOSFET M8, and the drain and source sides of the capacitor CB4 are set to 2VDD. For this reason, the gate side potential of the capacitor CB4 is 3VDD. In this circuit, the gate voltage of the rectifying MOSFET M1 is boosted to 3VDD, so that the current supply capability can be increased.
[0005]
For example, when an element made by a 0.3 μm process is used, VCH = 4.0 V when VDD = 2.9 V, VTN (M1) = 1 V, W / L (M1) = 75 μm / 1 μm, and load current = 2 mA. The voltage 3.8V necessary for full writing to the memory cell is sufficiently satisfied. However, since a maximum voltage of 2VDD is applied to the MOSFET M7, the gate breakdown voltage of the element is exceeded. Usually, the allowable electric field of the gate oxide film is 5 MV / cm or less. However, in this circuit, when tox = 8 nm, when VDD = 3.7V, the gate-source voltage of the MOSFET M7 reaches 7.2V, and the electric field reaches 9MV / cm, which is far beyond the allowable value.
[0006]
An object of the present invention is to provide a semiconductor integrated circuit device having an internal voltage generation circuit that relaxes a voltage applied to an element while maintaining a high voltage that is a multiple of the operating voltage and maintains its reliability. It is in. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a charge pump circuit driven by a power supply voltage VDD, a MOSFET of the same conductivity type is connected in series to a MOSFET to which a maximum voltage of 2 VDD or a voltage close to it is applied between the drain and source, and the gate thereof A potential VD-VDD lower than VDD by a drain potential VD before turning on. The gate potential is generated directly or from a part of the node of the charge pump circuit that generates a voltage pulse synchronized with the voltage between the drain and source of the MOSFET, or is branched by a capacitor from another node through another rectifying element. obtain.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 11 shows a characteristic portion of the boosted voltage generating circuit according to the present invention. In the present invention, in order to efficiently output the boosted voltage Vpp, 3VDD output from the second booster circuit is supplied to the gate of the MOSFET M1 included in the rectifier circuit RC. Here, the second booster circuit BC2 includes a capacitor CB4, a MOSFET M7 that precharges the capacitor CB4, a withstand voltage reducing MOSFET M14 provided between the MOSFET M7 and the capacitor CB4, and a rectifying MOSFET M13.
[0009]
Capacitor CB4 is precharged to VDD by MOSFET M7, and boosts node N5 to 3VDD in response to the change in output φ4 of first booster circuit BC1 from VDD to 2VDD. When the node N5 is set to 3VDD, the output φ3 of the first booster circuit is input to the gate of the MOSFET M14, and the voltage between the source and drain of the MOSFET M7 is relaxed to VDD-VTN instead of 2VDD. Hereinafter, although the present application focuses on the relaxation of the voltage between the source and the drain, the voltage between the source and the gate is also relaxed in the same manner. When attention is paid to one MOSFET, the electric field in the MOSFET is also reduced by relaxing the voltage between the two nodes.
[0010]
With such a configuration, the voltage between the source and drain of the MOSFET M7 does not exceed VDD, and the breakdown voltage against gate breakdown can be improved even when an element having a low gate breakdown voltage is used. Here, the outputs φ1 to φ4 of the first booster circuit BC1 mean the outputs of the double booster circuit that swings between VDD and 2VDD, but they are not necessarily output from different nodes, and φ3 and φ4 are the same. It may be output from the node, and φ1 and φ4 may be output from the same node. Further, in the above description, 2VDD represents a potential twice as high as VDD in consideration of an ideal state, and 3VDD represents a potential as 3 times as high as VDD. However, in reality, the potential drops slightly according to the charge share of the realization circuit and takes a slightly small value.
[0011]
FIG. 1 is a circuit diagram showing one embodiment of a boosted voltage generating circuit according to the present invention. In the figure, the P-channel type MOSFET is distinguished from the N-channel type MOSFET by adding a circle indicating that the low level is the active level to the gate portion. Further, the MOSFETs M1, M7, M8, M13, etc., in which the substrate gate and the source are connected in common, are formed in an electrically isolated well region. Therefore, the N-type well region DWLL is formed at a deep depth on the P-type substrate, and the N-channel MOSFET is formed by forming the P-type well region PWELL in the DELL.
[0012]
The boosted voltage generating circuit of this embodiment has an internal voltage in consideration of the low withstand voltage of the miniaturized MOSFET in addition to a device for efficiently forming the boosted voltage Vpp under the low power supply voltage VDD. It is devised not to exceed VDD. In this embodiment, the booster circuit is configured by combining four circuits. FIG. 2 shows an internal voltage waveform diagram for explaining the operation.
[0013]
The NOR gate circuit OR1 constitutes a drive circuit and constitutes a charge pump circuit together with the capacitor CB3. Similarly, the same applies to the NOR channel circuit OR2, the capacitor CB2, the inverter circuit i10, the capacitor CB1, and the P channel MOSFET M8, the N channel MOSFET M9, the N channel MOSFET M10, and the capacitor CB4 that use the boosted voltage formed by the capacitor CB2. A charge pump circuit is configured. The MOSFET M6 constitutes a precharge circuit for the capacitor CB6, the MOSFET M3 constitutes a precharge circuit for the capacitor CB2, and the MOSFET M2 constitutes a precharge circuit for the capacitor CB1. The MOSFET M7 constitutes a precharge circuit for the capacitor CB4, and the MOSFET M14 is provided for relaxing the voltage.
[0014]
As shown in the timing chart of FIG. 2, the potential of the node N1 changes to 0V-VDD in response to the oscillation pulse OSC, and the potential of the output side node N4 of the capacitor CB4 driven thereby is 2VDD at the maximum. Then, the operation is lowered by the charge transfer (current injection) to the output capacitor CD through the rectifying MOSFET M1, and the operation of changing to 2VDD again is repeated. In this embodiment, the drive voltage supplied to the gate of the rectifying MOSFET M1 is increased to 3VDD to increase the charge pump efficiency.
[0015]
In order to form the high voltage 3VDD, the boosted voltage 2VDD of the node N7 formed by the capacitor CB2 is used as the drive voltage of the capacitor CB4. The capacitor CB3 forms a drive voltage for the MOSFET M3 that precharges the capacitor CB2 to VDD. That is, the potential of the node N6 is changed to VDD-2VDD to drive the MOSFETs M3, M2, and M7, and the capacitors CB1, CB2, and CB4 are precharged to VDD without loss of the threshold voltage of the MOSFETs, respectively. Let
[0016]
The MOSFETs M4 and M11 precharge the nodes N6 and N7 to VDD-VTH (VTH is the threshold voltage of the MOSFET) in the initial state when the supply of the pulse OSC is started. When the potentials of the nodes N7 and N6 rise by the boosting operation, the capacitors CB2 and CB3 are precharged by the MOSFETs M6 and M3, and are precharged to VDD without loss of the threshold voltage as described above.
[0017]
In this embodiment, the MOSFET M14 is relaxed between the drain and the source of the precharge MOSFET M7 of the capacitor CB4 at the timing when the rectifying MOSFET M1 is turned on in order to ease the application of the voltage of 2VDD as described above. Is provided. That is, the MOSFET M14 is inserted in the precharge path of the capacitor CB4, but the operation itself plays a role of voltage relaxation between the source and drain of the MOSFET M7.
[0018]
In this embodiment, although not particularly limited, a capacitor CG for holding a boosted voltage 2VDD formed by the capacitor CB2 is provided, and the boosted voltage of 2VDD held here is supplied to the gate of the voltage relaxation MOSFET M14. . In order to perform the rectifying operation to the capacitor CG, a MOSFET M13 is provided, and the potential of the output node N5 on the boosting side of the capacitor CB4 is applied to the gate thereof. During the boosting operation, the MOSFET M13 is turned on and 2VDD of the node N7 is supplied. Is transmitted to the capacitor CG.
[0019]
When the potential of the node N2 becomes low level by the oscillation pulse OSC and the precharge voltage VDD is applied to the node N7, a precharge voltage such as VDD is also applied from the MOSFETs M7 and M14 to the node N5 correspondingly. . As a result, the MOSFET M13 is turned off, the potential of 2VDD is held in the capacitor CG, and the double boosted voltage 2VDD is applied to the MOSFET M14 similarly to the MOSFET M7, so that the capacitor CB4 is brought to the power supply voltage VDD. Can be precharged.
[0020]
As described above, when the MOSFET M14 is provided as a voltage relaxation element and the gate potential thereof is boosted to 3VDD and at the same time 2VDD, the maximum voltage in this circuit is applied between the drain and source of the MOSFET M7 when the MOSFET M14 is not provided. 2VDD to VDD + VNT applied between the drain and source of MOSFET M14. Here, VTN is the threshold voltage of MOSFET M14, and its back gate potential is VDD, so it is 0.5 V or less. As described above, by setting the back gate potential of the MOSFET M14 to VDD, the threshold voltage of the MOSFET M14 is lowered and the drain-source voltage is lowered. In addition, a capacitor is formed by a PN junction diode formed between the back gate and the node N5. There is also an advantage that CB4 is precharged quickly.
[0021]
This reduces the time from power-on to the desired output level. If the back gate of the MOSFET M14 is connected to VSS, since the nodes N5 and N8 are almost 0V immediately after power-on, the rise is very slow. Here, the capacitor CG is a capacitor for stabilizing the potential of the node N8. This keeps the potential of the node N8 at approximately 2VDD even if the boosting timings of the node N8 and the node N5 are slightly shifted, and prevents an excessive voltage from being applied between the drain and source of the MOSFET M14. However, since the time is usually short, it may not be necessary if the device has a sufficient withstand voltage.
[0022]
FIG. 12 is a circuit diagram showing another embodiment of the voltage doubler generating circuit according to the present invention. This embodiment is a modification of FIG. 1 except that the drain of the withstand voltage reducing MOSFET M13 connected to the node N7 in FIG. 1 is connected to the node N4 of the capacitor CB1 instead of the node N7. Other configurations are the same as those in FIG.
[0023]
As can be seen from FIG. 1 and FIG. 2, in the voltage doubler generation circuit shown in this embodiment, the potential at the node N5 is pulled down before the node N4 in order to prevent the charge from flowing backward from the node N10 to the node N4 through the MOSFET Ml. I am doing so. Therefore, according to the present embodiment, since the potential of the node N5 is lowered to the VDD level and the MOSFET M13 is sufficiently cut off, the node N4 is pulled down, so that the backflow of the charge at the node N8 is completely prevented. be able to. Therefore, there is an advantage that the potential holding capacitor CG of FIG. 1 can be omitted.
[0024]
FIG. 3 is a circuit diagram showing one embodiment of the negative voltage generating circuit according to the present invention. The circuit symbols attached to the respective elements in the figure partially overlap those in FIG. 1 for easy understanding of the drawing, but it should be understood that each has a separate circuit function. The same applies to other drawings described below.
[0025]
In this embodiment, although not particularly limited, the main MOSFET is configured as a P-channel type. These P-channel MOSFETs are formed in the N-type well region. Therefore, it can be electrically separated from the P-type well region where the memory cell is formed, and minority carriers are generated in the N-type well region in the charge pump operation. Therefore, it is used for the negative voltage generating circuit of the dynamic RAM. In this case, there is no influence on the memory cell formed in the P-type well region.
[0026]
A basic circuit of a pumping circuit that generates a negative voltage VBB is configured by a driving circuit including a CMOS inverter circuit I1 using a capacitor CB1, a P-channel MOSFET, and an N-channel MOSFET formed by using a MOS capacitor. The capacitor CB2 and the CMOS inverter circuit I2 are similar basic circuits, but the input pulses OSC and OSCB have a reverse phase relationship in which their active levels do not overlap with each other, and operate alternately according to the input pulse. Efficient charge pump operation.
[0027]
The rectifying MOSFETs M1 and M2 may basically be in the form of a diode, but if this is done, a level loss corresponding to the threshold voltage will occur. When the high level of the pulse signal OSC is a low voltage of about 3.3V, it substantially does not operate. Therefore, focusing on the fact that the MOSFET M2 only needs to be turned on when the input pulse OSC is at a high level, the inverter circuit I3 that drives the capacitor CB3 by forming a pulse similar to the input pulse, and the inverter circuit I3 When the input pulse OSC is at a low level, the capacitors CB3 and CB5 are precharged to VDD, respectively, and when the input pulse OSC is at a high level, the capacitors are connected in series, and the output signal of the inverter circuit I3 has a low level (0V). ) Is generated at the node N3, and the rectifying MOSFET M1 is turned on.
[0028]
In this configuration, when the MOSFET M1 is turned on, the gate voltage can be lowered by VDD with respect to the source-drain, so that the negative voltage formed by the capacitor CB1 without level loss due to the threshold voltage. Can be output. As a result, the output voltage VBB can be reduced to -VDD.
[0029]
The N-channel MOSFET M11 operates as a switch for connecting the two capacitors CB3 and CB5 in series, and together with the P-channel MOSFETs M13 and M15, forms a precharge path for the capacitor CB3 to VDD. The MOSFETs M13 and M15 and the MOSFETs M21 and M5 form a path for precharging the capacitor CB5 to VDD. Of the two MOSFETs M13 and M15 and the MOSFETs M5 and M21, the MOSFETs M13 and M5 are provided in order to constitute the original precharge circuit, respectively. Provided for mitigation.
[0030]
When a negative voltage is generated, the MOSFET M13 is supplied with a power supply voltage such as VDD on one end side and is supplied with a negative voltage −VDD formed by the capacitor CB2 on the other end side. Such a high voltage difference will occur. In order to alleviate such a high voltage, a MOSFET M15 is provided in series, and a ground potential of 0 V is applied to the gate of the MOSFET M15 so that each source and drain are shared by approximately VDD. Similarly, when the negative voltage is generated, a large voltage such as −2VDD is formed by the capacitor CB5 and applied to both ends of the MOSFET M5 of the precharge circuit. In order to alleviate such a high voltage, a MOSFET M21 is provided in series with the MOSFET M5, and -VDD is applied to its gate. As a result, approximately VDD is divided and applied between the source and drain of each MOSFET.
[0031]
The capacitor CB7, the MOSFET M17, and the MOSFET M19 are charge pump circuits that form -VDD applied to the gate of the voltage relaxation MOSFET M21. Although not particularly limited, the negative voltage -VDD is held by the capacitor CG. The gate voltage of the MOSFET M21 is constantly biased to -VDD.
[0032]
The MOSFET M3 is turned off at an early timing by receiving the high level output signal of the driving inverter circuit I2 that receives the other input pulse OSCB at the back gate (channel portion), thereby efficiently extracting the substrate potential. Similarly, the output signal of the driving inverter circuit I1 is supplied to the back gate of the MOSFET M1, thereby turning off the MOSFET M1 at an early timing when charging the capacitor CB1 and minimizing the leakage of the negative voltage VBB. .
[0033]
The control signal supplied to the gate of the MOSFET M2 corresponding to the other input pulse OSCB, the back gate voltage of the MOSFETs M4 and M1, the pulse signal formed by the inverter circuit I2 and the capacitors CB4 and CB6, and the input pulse A pulse signal formed based on OSC is used. In this case, as described above, the MOSFET M14 to which a high voltage having a voltage difference such as 2VDD between + V and −V is applied is provided with a voltage relaxation MOSFET M16 in series, and −2VDD is applied to both ends of the MOSFET M6. Are provided in series with a MOSFET M22 for voltage relaxation.
[0034]
FIG. 4 shows an internal voltage waveform diagram of the negative voltage generating circuit of FIG. The feature of this circuit is that MOSFETs M21, M22, M15, and M16 are provided in series as the breakdown voltage reducing elements for the MOSFETs M5, M6, M13, and M14 shown in FIG. 3, and the gate potentials of the MOSFETs M21 and M22 are set to the node N3 or N4 Is set to -VDD as it is boosted to -2VDD. The gate potentials of the MOSFETs M15 and M16 are always set to VSS (0V).
[0035]
As a result, as shown in the voltage waveform diagram of FIG. 4, the maximum voltage of this circuit is applied between the drain and source of the MOSFETs M5, M6, M13, and M14 in the absence of the MOSFETs M21, M22, M15, and M16. The voltage 2VDD is suppressed to VDD + | VTP | applied between the drains and sources of the MOSFETs M21, M22, M15, and M16. Here, | VTP | is the absolute value of the threshold voltage of MOSFETs M15, M16, M21, and M22. Here, the capacitor CG suppresses the fluctuation of the node N17 as in the embodiment of FIG. 1, and prevents an excessive voltage from being applied to the MOSFETs M21 and M22. Of course, there may not be a case where the MOSFETs M21 and M22 have a sufficient withstand voltage.
[0036]
FIG. 5 shows a circuit diagram of an embodiment of the triple boosted voltage generating circuit according to the present invention. FIG. 6 shows an internal voltage waveform diagram for explaining the operation. In this embodiment, a double boosted voltage 2VDD is formed by the CMOS inverter circuit I3 constituting the drive circuit and the capacitor CB5, and the triple boosted voltage is formed by the drive circuit (M27, M29, M31) operating at this voltage and the capacitor CB1. And 3VDD is held in the output capacitor CD through the P-channel rectifier MOSFET M2. A double boosted voltage 2VDD is formed by a CMOS inverter circuit I4 and a capacitor CB6 constituting a similar drive circuit, and a triple boosted voltage is formed by a drive circuit (M28, M30, M32) operating at this voltage and a capacitor CB2. The output capacitor CD holds 3VDD through the P-channel type rectifying MOSFET M2.
[0037]
The pulses F1B and F1 input to the two sets of circuits have an anti-phase relationship in which their active levels do not overlap with each other, and the two sets of circuits are operated in response to the input pulses to generate waveforms. As shown in the figure, an efficient charge pump operation is performed.
[0038]
The feature of this circuit is that MOSFETs M13, M14, M11, and M12 are provided as voltage relaxation elements for the MOSFETs M15, M16, M21, and M22 shown in FIG. 5, respectively, and the nodes N9 and N11 or N10 and N12 are boosted to 3VDD. In synchronization, the gate potentials of the MOSFETs M13, M14, M11, and M12 are set to 2VDD. As a result, the maximum voltage of this circuit is suppressed from 2 VDD to VDD + VTN applied between the drains and sources of the MOSFETs M11 to M13 when the MOSFETs M11 to M13 are not provided. It is done. Here, VTN is a threshold voltage of MOSFETs M11 to M13.
[0039]
Needless to say, if a capacitor is inserted between the node N17 and VDD or VSS as described above, the voltage fluctuation amount of the node is reduced, and the reliability of the MOSFETs M11 to M13 can be further increased. Further, as shown in the figure, the back gates of the MOSFETs M11 to M16 and M21 and M22 should be connected to VDD in order to speed up the rise of the nodes N9, N10, N11, and N12 when the power is turned on.
[0040]
As described above, the gate potential of the voltage relaxation MOSFET is directly or directly branched from a part of the nodes of the charge pump circuit generating a voltage pulse synchronized with the voltage between the drain and source of the MOSFET. To obtain it via another rectifying element. As a result, the gate potential generating circuit and the drive circuit for the charge pump circuit can be shared, so that the area occupied on the chip can be reduced. Further, since the boosting timing of the gate potential and the boosting timing of the drain potential are synchronized, it is not necessary to add a smoothing capacitor to stabilize the gate potential, and the occupied area on the chip can be reduced.
[0041]
FIG. 7 is an overall circuit block diagram of an embodiment of a system LSI to which the present invention is applied. The semiconductor integrated circuit device CHIP of the embodiment includes a plurality of circuit blocks as shown in the figure, that is, an input / output circuit I / O, a substrate bias control circuit VBBC, a control circuit ULC, a read only memory ROM, a D / A converter DAC, A It includes a / D converter ADC, an interrupt control circuit IVC, a system power management circuit SPMC having a clock generation circuit CGC, a central processing unit CPU, a static memory SRAM, a DMA controller DMAC, and a dynamic memory DRAM.
[0042]
These circuit blocks are coupled to an internal bus BUS and a control bus CBUS. They are mounted on a semiconductor substrate (not shown) that constitutes the semiconductor integrated circuit device. The system power management circuit SPMC has a function of controlling power consumed in each module mounted on the system LSI.
[0043]
The semiconductor integrated circuit device includes input / output external terminals Tio1 to Tion connected to the input / output circuit I / O, an external terminal T1 to which a reset signal resb such as a negative logic level is supplied, a control external terminal T2, and a first control terminal. A first operation control external terminal T3 to which the operation control signal cmq is supplied, a second operation control external terminal T4 to which the second operation control signal cpmq is supplied, and a clock external terminal to which the external clock signal clk is supplied T5 and a plurality of power supply external terminals T6, T7, T8 to which a plurality of power supply voltages (vdd, vccdr, vss) are supplied.
[0044]
Although not particularly limited, the power supply voltage vdd is a power supply voltage for the operation of the internal circuit block and takes a value such as 1.8 volts ± 0.15 volts. The power supply voltage vccdr is a power supply voltage set mainly for the input / output circuit I / O according to the input / output level required for the semiconductor integrated circuit device, and is 3.3 volts ± 0.3 volts. One of values such as 5 volts ± 0.25 volts and 1.8 volts ± 0.15 volts is taken. The potential vss is a circuit reference potential called a so-called ground potential.
[0045]
The illustrated semiconductor integrated circuit device constitutes a so-called ASIC (Application Specific Integrated Circuits), that is, an application specific IC. That is, most of the illustrated circuit blocks form so-called modules or macro cells as independent circuit functional units so as to facilitate the ASIC configuration. Each functional unit can be changed in scale and configuration. As the ASIC, among the illustrated circuit blocks, circuit blocks that are not required by the electronic system to be realized can be prevented from being mounted on the semiconductor substrate. Conversely, a functional unit circuit block (not shown) may be added.
[0046]
The semiconductor integrated circuit device is not particularly limited, but a semiconductor integrated circuit having a CMOS structure capable of a low power supply voltage so as to exhibit sufficient operating characteristics even under a low power supply voltage vdd such as 1.8 volts ± 0.15 volts. It is considered as a device.
[0047]
A dynamic memory mounted on a semiconductor integrated circuit device may be operated by the power supply voltage vdd. However, in the semiconductor integrated circuit device of this embodiment, a high power supply voltage generated from a voltage generation circuit operated by the power supply voltage vdd is used together with the power supply voltage vdd for the dynamic memory. In a dynamic memory, a circuit such as a row decoder for selecting a dynamic memory cell is operated with such a high power supply voltage, and a circuit for inputting / outputting a signal to / from the internal bus BUS of the semiconductor integrated circuit device is provided. It is operated by a power supply voltage such as a low power supply voltage vdd. This configuration increases the amount of charge as information given to the dynamic memory cell. Thereby, the information retention time characteristic of the dynamic memory can be improved. Similarly, by driving the sense amplifier by the overdrive method using the boosted voltage vbs as described above, a high-speed read operation can be performed.
[0048]
(Central processing unit CPU)
The central processing unit CPU is not particularly limited, but has the same configuration as a so-called microprocessor. That is, although the details are not shown in the figure, the central processing unit CPU decodes an instruction register therein, an instruction written in the instruction register, and forms various microinstructions or control signals, a microinstruction ROM, an arithmetic circuit, a general purpose It has input / output circuits such as a register (RG6, etc.), a bus driver coupled to the internal bus BUS, and a bus receiver.
[0049]
The central processing unit CPU reads an instruction stored in a read-only memory ROM or the like and performs an operation corresponding to the instruction. The central processing unit CPU captures external data input via the input / output circuit I / O, inputs / outputs data to / from the control circuit ULC, and commands from the read-only memory ROM and fixed data required for command execution. Data reading, supply of data to be D / A converted to the D / A converter DAC, reading of data A / D converted by the A / D converter, static memory SRAM, dynamic memory DRAM Data read / write to / from, DMA controller DMAC operation control, and the like are performed. The control bus CBUS is used for operation control of the circuit block shown in the figure by the central processing unit CPU, and is used to transmit a state instruction signal from a circuit block such as the DMA controller DMAC to the central processing unit CPU.
[0050]
The central processing unit CPU refers to the operation control signal set in the instruction register RG5 and the like in the interrupt control circuit IVC via the internal bus BUS and performs necessary processing. The central processing unit CPU receives the system clock signal C2 generated from the clock generation circuit CGC, and is operated with an operation timing and a period determined by the system clock signal C2.
[0051]
The central processing unit CPU includes a CMOS circuit, that is, a circuit composed of a pMOS and an nMOS. Although not particularly limited, the CMOS circuit constituting the central processing unit CPU includes a CMOS static logic circuit (not shown), a CMOS static circuit capable of static operation such as a CMOS static flip-flop, and a precharge of charge to a signal output node. And a CMOS dynamic circuit which performs signal output to the signal output node in synchronization with the system clock signal C2.
[0052]
When the supply of the system clock signal C2 from the clock generation circuit CGC is stopped, the central processing unit CPU is brought into an operation stop state accordingly. In the stop state, the output signal of the dynamic circuit is undesirably changed by an undesired leakage current generated in the circuit. A circuit such as a register circuit having a static flip-flop circuit configuration retains previous data even during a non-supply period of the system clock signal.
[0053]
In the non-supply period of the system clock signal C2, signal level transitions at various nodes in the static circuit inside the central processing unit CPU are stopped, and discharge or precharge at the output node in the dynamic circuit is stopped. . In this state, a relatively large current consumption such as an operating current consumed by the operating CMOS circuit, that is, a power supply line is applied so as to give a signal displacement to the stray capacitance and parasitic capacitance of various nodes and wirings connected to each node. The charge / discharge current is substantially zero. For this reason, the central processing unit CPU flows only a small current equal to the leakage current of the CMOS circuit, and enters a low power consumption state.
[0054]
(Interrupt control circuit IVC)
The interrupt control circuit IVC receives a reset signal such as a negative logic level at the external terminal T1, receives the first operation signal cmq through the external terminal T3, receives the second operation control signal cpmq through the external terminal T4, Further, a state instruction signal for instructing the operation state of the semiconductor integrated circuit device is output to the external terminal T2. The interrupt control circuit IVC has a register RG5 in which bits at respective positions are set corresponding to the reset signal resb, the operation control signals cmq, cpmq, and the state instruction signal.
[0055]
The state instruction signal in the register RG5 is updated by the central processing unit CPU via the internal bus BUS. The operation control signals cmq and cpmq set in the register RG5 via the external terminals T3 and T4 are referred to by the central processing unit CPU via the internal bus BUS as described above.
[0056]
Although not particularly limited, the interrupt control circuit IVC has a refresh address counter (not shown) for refreshing the dynamic memory therein. The refresh address counter in the interrupt control circuit IVC has the first and third modes designated by the first and second operation control signals cmq and cpmq, that is, the operation mode for the semiconductor integrated circuit device or the operation standby. If the mode is instructed, it is incremented based on the system clock signal from the clock generation circuit CGC to form refresh address information that is periodically updated.
[0057]
(Clock generation circuit CGC)
The clock generation circuit CGC receives the external clock signal clk via the external terminal T5, and forms a system clock signal C2 having a period corresponding to the external clock signal clk. In FIG. 12, although the signal line between the clock generation circuit CGC and the central control unit CPU is expressed in a simplified manner, the system clock signal C2 is a sequence of circuits (not shown) in the central control unit CPU. It should be understood that it consists of a multiphase signal, as well as a clock signal for a typical processor, for the purpose of operation.
[0058]
The generation of the system clock signal C2 by the clock generation circuit CGC is performed by the control signal C1 such as the mode signal MODE2 and the initial operation instruction signal INTL in response to the first and second operation control signals cmq and cpmq from the interrupt control circuit IVC and the center. It is controlled by a control signal C3 from the processing unit CPU. If a complete standby operation is instructed by the operation control signal cmq, the central processing unit CPU shifts to a complete standby operation including a write processing operation to the static memory SRAM of data to be statically held. Necessary processing operations are performed, and then a control signal C3 for stopping the system clock generation operation is generated from the central processing unit CPU to the clock generation circuit CGC.
[0059]
When an operation standby operation is instructed by the operation control signal cpmq, the central processing unit CPU includes a processing operation for writing data to be statically stored in the static memory SRAM, as in the case of the complete standby operation. A processing operation necessary for shifting to the operation standby operation is performed. In the subsequent operation in this case, unlike the case of the complete standby operation, a control signal C3 for selectively outputting a system clock signal is generated from the central processing unit CPU to the clock generation circuit CGC.
[0060]
That is, the supply of the system clock signal from the clock generation circuit CGC to the interrupt control circuit IVC and the dynamic memory DRAM is continued, and the supply of the system clock signal to the other circuit blocks is stopped. When the operation control signals cmq and cpmq are changed to a state instructing the operation of the circuit, the clock generation circuit CGC generates the system clock signal C2 corresponding to the external clock signal clk by the control signal C1 from the interrupt control circuit IVC corresponding thereto. Controlled to occur.
[0061]
(I / O circuit I / O)
The input / output circuit I / O receives a signal supplied from the outside via a desired external terminal among the external terminals Tio1 to Tion, and outputs a signal to be output to a desired terminal among the external terminals Tio1 to Tion. Receive via the internal bus BUS. The input / output circuit I / O has a control register RG4 and a data register (not shown) each formed of a CMOS static circuit.
[0062]
The control register RG4 is selected by the central processing unit CPU, and the central processing unit CPU performs control data for the input / output circuit I / O, for example, control data such as a data input / output instruction and a high output impedance state instruction. Is given. The data register is used for transferring data between the external terminals Tio1 to Tion and the internal bus BUS. When the bit widths of the external terminals Tio1 to Tion, that is, the number of terminals and the bit width of the internal bus BUS are different, the data register has a bit number corresponding to a large bit width, and the central processing unit CPU The number of bits is converted according to the operation control by.
[0063]
For example, when the number of external terminals Tio1 to Tion is a number such as 64, but the bit width of the internal bus BUS is a relatively large number such as 256 bits, the external terminals Tio1 to Tion have a 64-bit unit. Serial data sequentially supplied to Tion is sequentially supplied to the data register by serial-parallel data conversion control by the central processing unit CPU, and is converted into 256-bit data. Conversely, 256-bit data set in the data register from the internal bus BUS is divided into 64 bits and supplied sequentially to the external terminals Tio1 to Tion by the parallel-serial data conversion control by the central processing unit CPU. .
[0064]
A circuit for signal input and a circuit for signal output of the input / output circuit I / O are configured such that their input and output operations are controlled by a system clock signal. Therefore, when the system clock signal is not supplied, the input / output circuit I / O is put into a low power consumption state, similar to the central processing unit CPU.
[0065]
(Control circuit ULC)
The control circuit ULC is a control circuit provided as appropriate according to the needs of the electronic system. As the control circuit ULC, for example, in an electronic system to be realized such as motor servo control in a hard disk device, head tracking control, error correction processing, and compression / decompression processing of image and audio data in image and audio processing. It is provided accordingly. The operation of the ULC of the control circuit is controlled by the system clock signal in the same manner as the central processing unit CPU.
[0066]
(Read only memory ROM)
As described above, the read-only memory ROM stores instructions and fixed data to be read and executed by the central processing unit CPU.
[0067]
(D / A converter DAC)
The D / A converter DAC has a register RG2 that receives digital data to be converted into an analog signal supplied via the internal bus BUS, and forms an analog signal based on the digital data. The register RG2 is set with digital data by the control circuit ULC or the central processing unit CPU. The D / A conversion operations such as the D / A conversion start timing of the D / A converter DAC and the output timing of the D / A conversion result are controlled by the system clock signal. The analog signal formed by the D / A converter DAC is not particularly limited, but is supplied to desired terminals of the external terminals T1 to Tn via the internal bus BUS and the input / output circuit I / O. Here, the external terminals T1 to Tn are input / output terminals (pins), but they may be provided separately for input terminals and output terminals.
[0068]
Although not shown in detail, the D / A converter DAC has a reference voltage source or a reference current source that is used as a reference for an analog quantity to be obtained when a high-precision DA conversion is required. . Such a reference voltage source or reference current source is considered to constitute a kind of analog circuit, and has a risk of consuming a non-negligible current in the second mode and the third mode, that is, the complete standby mode and the operation standby. Have. Therefore, in order to enable reduction of current consumption in such a case, a MOSFET switch that switches off is set for the reference voltage source or the reference current source in the second mode and the third mode. The
[0069]
(A / D converter ADC)
The A / D converter ADC receives a desired terminal among the external terminals T1 to Tn, an analog signal supplied via the input / output circuit I / O, and the internal bus BUS, and receives the control circuit ULC or the central processing unit. The CPU controls the start of the A / D conversion, converts the analog signal into a digital signal under clock control according to the system clock signal C2, and sets the obtained digital signal in the register RG1.
[0070]
Similarly to the D / A converter DAC, the A / D converter ADC also has a reference voltage source or a reference voltage source that is used as a reference for a quantization level to be digitally converted when high-precision AD conversion is required. Have a reference current source. Such a reference voltage source or reference current source in the A / D converter ADC also has the risk of consuming a non-negligible current in full standby mode and in operating standby mode. Therefore, in that case, a MOSFET switch similar to the above is applied to such a reference voltage source or reference current source.
[0071]
(Static memory SRAM)
Although not shown in detail, the static memory SRAM is a memory cell composed of a CMOS static memory cell, that is, a CMOS latch circuit, that is, a CMOS latch circuit and a pair of transmission date MOSFETs for data input / output thereto. Have a cell. The CMOS static memory cell has a feature that it holds information statically and requires only a very small operating current for holding information.
[0072]
Such a static memory SRAM substantially constitutes a CMOS static random access memory. In other words, the static memory SRAM decodes a memory array composed of a plurality of CMOS static memory cells arranged in a matrix and a row address signal supplied via the internal bus BUS, thereby selecting a word line in the memory array. A row address decoding drive circuit for decoding, a column address decoding circuit for decoding a column address signal and thereby forming a column decoding signal, and selecting a data line in the memory array operated by the column decoding signal. Are connected to a common data line, an input / output circuit coupled to the common data line, and a read / write control circuit.
[0073]
A circuit such as an address decode drive circuit related to the memory array, that is, a memory array peripheral circuit is composed of a CMOS static circuit. Therefore, the static memory cell SRAM is placed in a relatively low power consumption state only for the information holding operation in which the read and write operations are not performed. The CMOS static memory has a feature to be considered that the memory cell size becomes relatively large and the overall size with respect to the storage capacity becomes relatively large, and it is relatively difficult to increase the storage capacity. is there.
[0074]
(DMA controller DMAC)
The operation of the DMA controller, that is, the direct memory access controller DMAC is controlled by the central processing unit CPU, and the data transfer via the internal bus BUS between the circuit blocks designated by the central processing unit CPU is performed. Instead of controlling. Details of the DMA controller DMAC can be made substantially the same as that of the DMA controller configured as an independent semiconductor integrated circuit device, and therefore will not be described in further detail. However, a central processing unit CPU is provided in the internal register RG7 and the like. Data transfer control is performed based on setting information such as transfer source information, transfer destination information, and data transfer amount information set by.
[0075]
(Dynamic memory DRAM)
The dynamic memory DRAM is composed of a small number of elements such that the memory cell, that is, the dynamic memory cell, typically includes an information storage capacitor for storing information in the form of electric charges and a selection MOSFET. A relatively small memory cell size can be achieved. Therefore, the dynamic type memory can have a relatively small overall size even with a large storage capacity. This dynamic memory DRAM will be described next.
[0076]
FIG. 8 shows a block diagram of an embodiment of a dynamic memory (hereinafter simply referred to as DRAM) mounted on a semiconductor integrated circuit device to which the present invention is applied. This DRAM constitutes, for example, one module or functional unit in the system LSI (semiconductor integrated circuit device).
[0077]
The illustrated DRAM is not particularly limited, but adopts a bank configuration so as to be adapted to a large storage capacity. The number of memory banks can be changed, for example, with the maximum number being 16. One memory bank, for example, the first memory bank bank1, includes a bit line precharge circuit (not shown), a timing generation circuit, and a column selector TC1, which are integrated with the memory cell array MA1, the sense amplifiers SA0 and SA1, and the sense amplifier. , A row decoder RD1, and a column switch circuit CS1.
[0078]
For these memory banks, an address bus / control bus ADCB for address signals and control signals is set, and a memory internal bus (I / O internal bus) IOB for data input / output is set. A common memory input / output circuit MI / O is provided for the buses ADCB and IOB. The memory input / output circuit MI / O has therein a port coupled to the internal bus BUS in FIG.
[0079]
The DRAM also has a substrate bias switching circuit VBBM coupled to the substrate bias control circuit VBBC via the wiring group VL & CL, an internal power supply circuit IMVC, internal operation control signals mq and pmq, a reset signal resb, and a control bus CBUS. The memory control circuit MMC that receives the various operation control signals and the power supply initialization circuit VINTC. The internal power supply circuit IMVC includes a charge pump circuit such as the booster circuit and the negative voltage generation circuit.
[0080]
In the above, according to the convenience of the design data management unit in the design automation for configuring the semiconductor integrated circuit device, a set of elements in a wider range can be regarded as having fewer elements. For example, the memory cell array (MA1), the sense amplifiers (SA1 and SA2), the row decoder (RD1), and the column switch (CS1) in one memory bank can be regarded as constituting one memory mat. The column selector (TC1) can be regarded as constituting a bank control circuit. In this case, each memory bank is considered to be simply composed of a memory mat and a bank control circuit.
[0081]
In the illustrated DRAM, the memory mat, its selection circuit, and the like are almost the same as those of a known DRAM configured as an independent CMOS type semiconductor integrated circuit device. Therefore, a detailed description of the internal configuration is avoided, but the outline is as follows.
[0082]
<Memory cell array MA1-MAn>
A memory cell array such as the memory cell array MA1 includes a plurality of dynamic memory cells arranged in a matrix, a plurality of word lines to which selection terminals of the corresponding memory cells are coupled, and data input / output terminals of the corresponding memory cells. And a plurality of bit lines coupled to each other.
[0083]
The selection MOSFET constituting the memory cell has a structure in which an N-type source region and an N-type drain region are formed in a P-type well region PWELL1 formed on a semiconductor substrate made of P-type single crystal silicon. . Although not particularly limited, the semiconductor substrate is electrically isolated from the semiconductor substrate by an N-type isolation semiconductor region having a relatively low impurity concentration. Such an isolation region is set to a positive potential like the power supply terminal vdd of the circuit. The N-type isolation semiconductor region acts to protect the P-type well region PWELL1 from undesirable carriers that are generated in the P-type semiconductor substrate due to α particles and the like.
[0084]
P-type well region PWELL1 in which the memory cells are formed is supplied with a negative substrate bias voltage vbb formed by internal power supply circuit IMVC in the DRAM. As a result, tailing current or leakage current of the selection MOSFET in the memory cell is reduced, and information leakage in the information storage capacitor in the memory cell is reduced.
[0085]
An information storage capacitor in the memory cell is formed on the P-type well region PWELL1 through an insulating film made of a silicon oxide film. One electrode of the information storage capacitor is electrically coupled to an electrode region that can be regarded as a source region of the selection MOSFET. The other electrode of each of the plurality of information storage capacitors for the plurality of memory cells is a common electrode called a so-called plate electrode. The plate electrode is given a predetermined potential vpl as a capacitive electrode.
[0086]
The information storage capacity is desired to have a relatively small size so as to reduce the size of the memory cell array, and also to have a large capacity value so as to have a long information holding time. For the information storage capacitor, the dielectric film sandwiched between the electrodes is selected from a material having a relatively large dielectric constant such as tantalum oxide or silicon oxide so as to have a large capacitance value, and per unit area. The thickness is extremely thin so as to increase the capacity. The plate electrode potential vpl for the plurality of information storage capacitors is set to an intermediate potential equal to half the power supply voltage vdd of the circuit formed by the voltage conversion circuit IMVC.
[0087]
As a result, when a high level such as the power supply voltage vdd level is supplied according to information to be stored in one electrode of the information storage capacitor, a low level equal to the circuit ground potential is applied to the one electrode. In any case of the supply, the plate electrode potential vpl is set to a potential almost half of the power supply voltage vdd. That is, the voltage applied to the dielectric film is limited to a small value such as approximately half of the power supply voltage vdd. As a result, the dielectric film can be reduced in its withstand voltage, and undesired leakage current can be reduced as the applied voltage is reduced, so that the thickness can be reduced to a critical thickness. Become.
[0088]
<Timing generation and column selector>
The timing generation and column selector such as the timing generation and column selector TC1 are controlled by the operation control signal from the global control circuit in the memory control circuit MCC, and activated by the bank selection signal supplied via the bus ADCB. Various internal timing signals for controlling the operation of various circuits such as a bit line precharge circuit for the bit lines of the memory cell array, a row decoder, a sense amplifier, and a column selector within itself are formed. The operation of the column selector in the timing generation and column selector is controlled by an internal timing signal, decodes the column address signal supplied via the bus ADCB, and operates the column switch circuit in the bank such as the column switch circuit CS1. A decode signal for generating the signal is formed.
[0089]
A row decoder such as the row decoder RD1 has its operation timing controlled by timing generation and a timing signal supplied from the column selector, decodes an address signal supplied via the bus ADCB, and a word line in the corresponding memory cell array. Select.
[0090]
The bit line precharge circuit is operated by a precharge timing signal at a timing before the row decoder is activated, and each bit line in the corresponding memory cell array is set to a level equal to approximately half the power supply voltage vdd. To precharge.
[0091]
<Sense amplifier>
The sense amplifiers such as the sense amplifiers SA0 and SA1 are operated by a timing signal such as TC1 and a sense amplifier timing signal generated from the column selector circuit after the row decoder is activated, and are selected by the row decoder. The signal given to the bit line by the cell, that is, the read signal is amplified. Each of the plurality of unit sense amplifiers corresponding to each bit line in the sense amplifier has substantially the same configuration as a well-known CMOS sense amplifier.
[0092]
Each unit sense amplifier has a pair of pMOSs whose gates and drains are cross-connected, and a pair of nMOSs whose gates and drains are similarly cross-connected. A pair of pMOS drains and a pair of nMOS drains are coupled to a corresponding pair of bit lines. The sources of the pair of pMOSs are connected in common, and an operating potential is applied through a switch MOSFET whose operation is controlled by a sense amplifier timing signal. Similarly, a pair of nMOS sources are connected in common, and an operating potential such as a circuit ground potential is applied through a switch MOSFET whose operation is controlled by a sense amplifier timing signal.
[0093]
As the operating voltage, for example, the power supply voltage vdd corresponding to the high level of the bit line and the boosted voltage vbs set to a higher voltage are used. A so-called overdrive system in which the sense amplifier performs an amplification operation with the boosted voltage vbs for a certain period until the sense amplifier starts an amplification operation and the potential of the bit line to be raised to a high level reaches a desired voltage. Is adopted. When the potential of the bit line reaches near the desired potential vdd, the operating voltage of the sense amplifier is switched to the power supply voltage vdd corresponding to the original high level of the bit line.
[0094]
The arrangement of the two sense amplifiers across the memory cell array means the following configuration. That is, a skip bit line among a plurality of bit lines of the memory cell array is coupled to the sense amplifier on one side of the memory cell array, and a plurality of bits of the memory cell array is connected to the sense amplifier on the other side of the memory cell array. The remaining free bit lines of the line are combined. This configuration reduces the pitch of the plurality of bit lines in the memory cell array when the plurality of MOSFETs constituting the sense amplifier must be arranged with a relatively large pitch according to the required size. It is effective.
[0095]
<Column switch circuit>
A column switch circuit such as the column switch circuit CS1 is operated by a selection signal output from a corresponding column selector. The column switch circuit selects a bit line designated by the column selector among the plurality of bit lines in the memory cell array and couples it to the memory internal bus IOB.
[0096]
<Memory input / output circuit M-IO>
The memory input / output circuit M-IO is coupled to the internal bus BUS of the semiconductor integrated circuit device, receives an address signal and a control signal from the internal bus BUS, and transmits them to the internal bus ADCB. The memory input / output circuit M-IO also inputs / outputs memory data between the bus BUS and the memory internal bus IOB.
[0097]
<Memory control circuit MCC>
The memory control circuit MCC receives the internal first and second operation control signals mq and pmq and the reset signal resb of the semiconductor integrated circuit device, and performs control operations according to these signals. The memory control circuit MCC is not particularly limited, but includes a first control logic circuit MSW that receives the first operation control signal mq and the second operation control signal pmq and generates the internal operation control signal bbcz in response thereto, and a first operation control. And a second control logic circuit VINT that receives the signal mq and the reset signal resb and generates a substantial initialization control signal intgb in response thereto.
[0098]
(Substrate bias switching circuit VBBM)
The substrate bias switching circuit VBBM receives various bias voltages vbp, vbn, vbpg, vbng and control signals vbcp, vbcn from the substrate bias control circuit VBBC via the line group VL & CL, and receives a control signal bbcz from the memory control circuit MCC. Then, the bias voltage is supplied to a required circuit portion in the DRAM under the operation control by the bias voltage and the control signal.
[0099]
(Voltage conversion circuit MVC)
The voltage conversion circuit IMVC receives the power supply voltage supplied between the power supply terminal VDD and the reference potential terminal VSS of the DRAM, and selects the substrate bias voltage vbb, the plate voltage vpl, and the word line for the memory cell array as described above. Internal voltages such as a boosted voltage vdh for setting the level and a boosted voltage vbs for overdriving the sense amplifier are formed. Although not particularly limited, the substrate bias voltage vbb for the memory cell array is formed in the circuit IMVC in the DRAM as a module. The circuit that generates the bias voltage vbb and the boosted voltages vdh and vbs at the negative potential level is devised to form a desired negative voltage even with a low power supply voltage as described above.
[0100]
The configuration in which the bias voltage vbb is independently formed as in this embodiment is such that the information signal read from the dynamic memory cell is at a minute level, and the potential variation of the p-type well region pwell1 is controlled so as not to disturb the minute level. It is advantageous in terms of suppression. Such a circuit for forming the bias voltage vbb has a generally small undesired leakage current flowing from the memory cell array to the p-type well region pwell1, and accordingly the output capability thereof may be relatively small. The power consumption itself can be sufficiently reduced.
[0101]
(Power supply initialization circuit VINTC)
The power supply initialization circuit VINTC initializes the DRAM circuit under the operation control by the memory control circuit MCC. The configuration example of the power supply initialization circuit VINTC and the details of the initialization operation will not be described in detail because they are not directly related to the present invention.
[0102]
In the above description, the term “MOS” is understood to have originally come to be referred to simply as a metal oxide semiconductor configuration. However, the MOS in the general name in recent years includes those in which the metal in the essential part of the semiconductor device is replaced with a non-metal electrical conductor such as polysilicon, or the oxide is replaced with another insulator. Yes. CMOS has also been understood to have broad technical implications in response to changes in how it pertains to MOS as described above. MOSFETs are not understood in a narrow sense as well, but have become meanings including configurations in a broad sense that can be substantially regarded as insulated gate field effect transistors. The CMOS, MOSFET, and the like of the present invention follow the general names.
[0103]
FIG. 9 shows a circuit diagram of an embodiment of the memory cell array and the word line selection circuit. In the same figure, an equalizing & precharging circuit for bit lines included in the memory array section is also drawn. In the memory mat of FIG. 1, one bank #j of the bank addresses # 0 to #n is exemplarily shown as a representative. Among a plurality of complementary bit lines and a plurality of word lines provided in bank (memory mat) #j, a pair of complementary bit lines BLm, / BLm and one bit line BLn, word lines WL0, WLm, WLm + 1, WLn are It is exemplarily shown as a representative.
[0104]
In the description of the memory cell provided at the intersection of the word line WL0 and the bit line BLm as an example, the gate of the address selection MOSFET Qm is connected to the word line. One source and drain of the MOSFET Qm is connected to the bit line BLm. The other source and drain of the MOSFET Qm are connected to a storage node Ns which is one electrode of the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared with the other electrode of the storage capacitor of the other memory cell, and the plate voltage VPL is applied.
[0105]
The memory cells as described above are arranged in a matrix at the intersection of the word line and one of the complementary bit lines. For example, in the word line WLm and the adjacent word line WLm + 1, a memory cell is provided at the intersection of the word line WLm and one of the complementary bit lines BLm, and the word line WLm + 1 and the complementary bit line A memory cell is provided at the intersection with the other bit line / BLm. Thus, in addition to alternately arranging memory cells on one and the other of the complementary bit lines for every odd and even number of word lines, a pair of two adjacent word lines is used for each of the two word lines. Two memory cells provided respectively may be alternately arranged on one and the other of the complementary bit lines.
[0106]
The complementary bit lines BLm, / BLm are provided with N-channel MOSFETs Q14 to Q16 that constitute an equalize & precharge circuit. The MOSFET Q14 short-circuits the high level and low level (or low level and high level) of the complementary bit lines BLm and / BLm to set the half potential. MOSFETs Q15 and Q16 are for preventing the half potential due to the short circuit of the complementary bit lines BLm and / BLm from fluctuating due to a leakage current or the like, and applying the half precharge voltage VMP to the complementary bit lines BLm and / BLm. Supply. The gates of these MOSFETs Q14 to Q16 are connected in common and supplied with a precharge & equalize signal BLEQj. That is, after the word line is reset from the selection level to the non-selection level, the signal BLEQj changes to the high level, the MOSFETs Q14 to Q16 are turned on, and the precharge and equalization operations of the complementary bit lines BLm and / BLm are performed. Let it be done.
[0107]
A plurality of word line drive circuits WD0 to WDn are provided corresponding to the plurality of word lines WL0 to WLn. In the drawing, a specific circuit of the word line driving circuit WDm corresponding to the word line WLm is exemplarily shown as a representative. The word line drive circuit WDm has a CMOS composed of a P-channel MOSFET Q6 whose source is connected to the boost power source VDH consisting of the booster circuit and an N-channel MOSFET Q7 whose source is connected to the ground potential of the circuit. An inverter circuit is used. The drains of the MOSFETs Q6 and Q7 are connected in common to form an output terminal, which is connected to the word line WLm. The gates of the MOSFETs Q6 and Q7 are connected in common to form an input terminal and supplied with a selection signal formed by a row (X) decoder RDEC.
[0108]
Between the input terminal of the CMOS inverter circuit (Q6 and Q7) and the boosted power source VDH, a P channel type MOSFET Q9 for precharging with its source-drain path connected, and a P channel type for non-selection latch. MOSFET Q8 is provided in parallel. The gate of the non-select latch P-channel MOSFET Q8 is connected to the output terminal of the CMOS inverter circuit (Q6 and Q7). A precharge signal WPH is supplied to the gate of the precharge P-channel MOSFET Q9. The signal generation circuit for generating the precharge signal WPH generates a high level signal WPH corresponding to the selected level of the word line and a low level signal WPH such as the ground potential of the circuit using the boosted power supply VDH as an operating voltage.
[0109]
The MOSFET Q14 is a level limiter MOSFET. When a sense amplifier (not shown) operates at the power supply voltage Vdd, the high level of the potential of the complementary bit line BLm or / BLm corresponds to the power supply voltage Vdd, and the potential of the boosted voltage VDH is formed at the power supply voltage Vdd + Vth. The Here, Vth is a threshold voltage of the address selection MOSFET Qm, and a high level signal such as the power supply voltage Vdd of the complementary bit line BLm or / BLm amplified by the amplification operation of the sense amplifier is applied to the capacitor Cs without any level loss. To be told.
[0110]
The effects obtained from the above embodiment are as follows. That is,
(1) By combining a plurality of charge pump circuits including a drive circuit for forming a pulse signal corresponding to the operating voltage and a capacitor charged up by the pulse signal formed by the driving circuit, a plurality of the operating voltages An internal power generation circuit having an internal node configured to have a double voltage difference, and the same conductivity as that of the MOSFET used for the voltage generation operation between the internal nodes where a potential difference of a multiple of the operation voltage is generated. Type MOSFET is inserted in series as a voltage relaxation MOSFET, and a voltage corresponding to the voltage generation operation is supplied to the gate of the voltage relaxation MOSFET and lower than the drain voltage by the operation voltage. To obtain a voltage multiple of the operating voltage and relax the voltage applied to the device, to maintain its reliability An effect is obtained that an internal voltage generation circuit can be obtained.
[0111]
(2) As the internal voltage generation circuit, a double booster circuit composed of a first drive circuit and a first charge pump circuit composed of a first capacitor is formed, and formed by the double booster circuit. The output of the capacitor of the second charge pump circuit is constructed while constituting a triple booster circuit composed of a second drive circuit using the boosted voltage as an operating voltage and a second charge pump circuit comprising a second capacitor. The first MOSFET for precharging the second capacitor to the operating voltage and the second MOSFET having the boosted voltage formed by the double boosted voltage applied to the gate are formed in series on the side and the operating voltage terminal. By connecting to, it is possible to obtain an effect that only a low voltage substantially corresponding to the operating voltage can be applied between the source and drain of each MOSFET.
[0112]
(3) As the internal voltage generation circuit, a plurality of capacitors are precharged corresponding to the operating voltage at the first timing, and the operating capacitors are connected in series to the operating voltage at the second timing. A MOSFET for precharging the capacitor between a node forming the multiple voltage and a ground potential, and between a power supply voltage and a series connection point of the capacitor. And a voltage relaxation MOSFET in which a voltage corresponding to the above operating voltage is applied to the gate is connected in series, so that a high voltage is formed and the operating voltage is substantially supported between the source and drain of each MOSFET. Thus, an effect that only a low voltage can be applied can be obtained.
[0113]
(4) The internal voltage generation circuit further includes a charge pump circuit that performs a precharge operation at a first timing and generates a negative voltage corresponding to the operation voltage at a second timing. The second capacitor and the second capacitor are precharged with a positive voltage corresponding to the operating voltage, and at the second timing, the first capacitor and the second capacitor are connected in series, and the ground potential is A negative voltage equivalent to twice the operating voltage is formed with reference to the control voltage to form a control signal for the P-channel type rectifier MOSFET, and the P-channel type rectifier MOSFET is preliminarily set at the first timing. The charge pump circuit is turned off by the charge voltage, and is turned on by the negative voltage corresponding to the double at the second timing. By performing the output operation of the negative voltage formed by the above, an effect that the negative voltage can be efficiently formed is obtained.
[0114]
(5) Provided between a plurality of word lines and a plurality of complementary bit line pairs, one of the word lines and one of the complementary bit lines, a gate is connected to the word line, and one source and drain correspond to each other. A dynamic type comprising an address selection MOSFET connected to the one complementary bit line and a storage capacitor in which the other source and drain of the address selection MOSFET are connected to one electrode and a predetermined voltage is applied to the other electrode. A plurality of pairs of P-channel MOSFETs constituting the amplifying unit on the operating voltage side, and the cross-connected gates and drains connected to the memory cells, the cross-connected gates and drains connected to the plurality of complementary bit line pairs, respectively. Are connected to the plurality of complementary bit line pairs, respectively, and a plurality of pairs of N-channel type constituting an amplification unit on the ground potential side In a dynamic RAM including a sense amplifier composed of a MOSFET, a dynamic RAM that operates stably to a low voltage by forming a selection level of a word line to which the gate of the address selection MOSFET is connected by the booster circuit. The effect is obtained that a semiconductor integrated circuit device with a built-in can be obtained.
[0115]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the booster circuit can be widely used not only for forming the word line selection level of the dynamic memory cell but also for those requiring a high voltage higher than the operating voltage. The negative voltage is used as an operating power source for an analog circuit such as an operational amplifier circuit that operates with a dual power source consisting of a positive voltage and a negative voltage, in addition to a back bias voltage applied to a substrate gate on which a dynamic memory cell is formed. May be. The present invention can be widely used for a semiconductor integrated circuit device having an internal node which has a potential difference which is multiplied by a plurality of times with respect to an operating voltage such as a power supply voltage by a charge pump circuit.
[0116]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a combination of a plurality of charge pump circuits each including a drive circuit that forms a pulse signal corresponding to the operation voltage and a capacitor that is charged up by the pulse signal formed by the drive circuit provides a multiple of the operation voltage. An internal power generation circuit having an internal node configured to have a voltage difference of the same, and the same conductivity type as the MOSFET used for the voltage generation operation between internal nodes where a potential difference of multiple times the operation voltage is generated The voltage relaxation MOSFET is inserted in series as a voltage relaxation MOSFET, and a voltage corresponding to the voltage generation operation is supplied to the gate of the voltage relaxation MOSFET, and a voltage lower than the drain voltage by the operation voltage is supplied. Obtain multiple times the operating voltage and relax the voltage applied to the device to maintain its reliability It is possible to obtain an internal voltage generation circuit to.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a boosted voltage generating circuit according to the present invention.
FIG. 2 is an internal voltage waveform diagram for explaining the operation of the booster circuit of FIG. 1;
FIG. 3 is a circuit diagram showing one embodiment of a negative voltage generating circuit according to the present invention.
4 is an internal voltage waveform diagram for explaining the operation of the negative voltage generating circuit of FIG. 3; FIG.
FIG. 5 is a circuit diagram showing one embodiment of a triple boosted voltage generating circuit according to the present invention.
6 is an internal voltage waveform diagram for explaining the operation of the triple boosted voltage generating circuit of FIG. 5. FIG.
FIG. 7 is an overall circuit block diagram showing an embodiment of a system LSI to which the present invention is applied.
FIG. 8 is a block diagram showing an embodiment of a dynamic RAM mounted on a semiconductor integrated circuit device to which the present invention is applied.
9 is a circuit diagram showing one embodiment of a memory cell array portion of the dynamic RAM of FIG. 8. FIG.
FIG. 10 is a circuit diagram showing an example of a boosted voltage generating circuit studied prior to the present invention.
FIG. 11 is a schematic circuit diagram showing the characteristic part of the boosted voltage generating circuit according to the present invention.
FIG. 12 is a circuit diagram showing another embodiment of the voltage doubler generating circuit according to the present invention.
[Explanation of symbols]
M1 to M26, MOSFET, OR1, OR2, NOR gate circuit, i1 to i10, inverter circuit, CB1 to CB8, CG, CD, capacitor, I1 to I8, inverter circuit,
IO ... I / O circuit, VBBC ... Substrate bias control circuit, ULC ... Control circuit, ROM ... Read only memory, DAC ... D / A converter, ADC ... A / D converter, IVC ... Interrupt control circuit, CGC ... Clock generation Circuit, CPU ... Central processing unit, SRAM ... Static memory, DMAC ... DMA controller, DRAM ... Dynamic memory, BUS ... Internal bus,
CLC ... logic circuit, VL & CL ... wiring group, MA ... memory array, SA ... sense amplifier, CS ... column switch, TC ... column secretor, RD ... row decoder, M-IO ... memory input / output circuit, VBBM ... substrate bias switching circuit, IMVC: internal power supply circuit, MMC: memory control circuit, VINTC: power supply initialization circuit, IMVC: voltage conversion circuit, ADCB: address, control bus.

Claims (8)

With a booster circuit,
The booster circuit
A first charge pump circuit that forms a boosted voltage that is twice the operating voltage using a first pulse corresponding to the operating voltage;
A second charge pump circuit that forms a boosted voltage twice the operating voltage using a second pulse corresponding to the operating voltage;
A third charge pump circuit that forms a boosted voltage that is three times the operating voltage using a double boosted voltage formed by the second charge pump circuit and a third pulse corresponding to the operating voltage;
A fourth charge pump circuit that forms a boosted voltage that is twice the operating voltage using a fourth pulse corresponding to the operating voltage;
A first switch MOSFET of a first conductivity type that transmits a boosted voltage twice that of the fourth charge pump circuit;
A third conductivity type third and fifth precharge MOSFETs in series form for precharging the third charge pump capacitance of the third charge pump circuit to the operating voltage;
The boost voltage of the first charge pump circuit includes a gate of a second conductivity type second precharge MOSFET that precharges a second charge pump capacitor provided in the second charge pump circuit to the operating voltage, and the third charge pump circuit. A fourth precharge MOSFET of the first conductivity type that precharges the gate of the third precharge MOSFET provided in the charge pump circuit and the fourth charge pump capacitor provided in the fourth charge pump circuit to the operating voltage. Supplied to each gate,
The boosted voltage of the second charge pump circuit is supplied to the gate of a first conductivity type first precharge MOSFET that precharges the first charge pump capacitor provided in the first charge pump circuit to the operating voltage,
A double boosted voltage is supplied to the gate of the fifth precharge MOSFET through the second switch MOSFET of the first conductivity type to which the output voltage of the third charge pump circuit is supplied to the gate,
The gate of the first switch MOSFET is supplied with the output voltage of the third charge pump circuit,
A semiconductor integrated circuit device in which a withstand voltage of each MOSFET constituting the booster circuit is not less than the operating voltage and not more than twice the operating voltage . In claim 1,
A semiconductor integrated circuit device having a diode-type MOSFET that causes a current to flow from the operating voltage side toward each gate at the gate of each of the first to fourth precharge MOSFETs . In claim 1 or 2,
A semiconductor integrated circuit device in which the operating voltage is supplied to a back gate of the fifth precharge MOSFET . In any of claims 1 to 3,
The third charge pump circuit includes:
Between the output voltage of the second charge pump circuit and the ground potential of the circuit, a first conductivity type first MOSFET and a first conductivity type first and second MOSFET are provided in series,
The operating voltage is supplied to the gates of the second conductivity type first MOSFET and the first conductivity type first MOSFET, and the third pulse is supplied to the gate of the first conductivity type second MOSFET,
A semiconductor integrated circuit device in which a double boosted voltage supplied to the third charge pump capacitor is formed from an interconnection point between the second conductivity type first MOSFET and the first conductivity type first MOSFET . In any of claims 1 to 4,
A plurality of word lines and a plurality of complementary bit line pairs;
A dynamic memory cell provided between the word line and one of the complementary bit lines ;
The output voltage of the booster circuit, when the word line is selected, semiconductors integrated circuit device which is supplied to the word line through a word driver. A first negative voltage generating circuit;
The first negative voltage generation circuit includes:
At the first timing, the first capacitor and the second capacitor are precharged to positive operating voltages, respectively, and the holding voltages of the first capacitor and the second capacitor are added at a second timing different from the first timing. A first charge pump circuit connected in series, supplying a ground potential of the circuit to one end on the high potential side, and forming a negative voltage corresponding to twice the operating voltage from the other end on the low potential side;
At the first timing, the third capacitor is precharged to the operating voltage, and at the second timing, the ground potential of the circuit is supplied to one end on the high potential side of the third capacitor, and the other end on the low potential side A second charge pump circuit for forming a negative voltage corresponding to the operating voltage;
A P-channel first switch MOSFET that transmits a negative voltage of the second charge pump circuit;
The gate of the first switch MOSFET is supplied with the output voltage of the first charge pump circuit,
In the first charge pump circuit, the precharge MOSFETs that supply the operating voltage to the second capacitor are P-channel type first and second precharge MOSFETs arranged in series, and the ground potential is connected to the second capacitor. Are pre-charge MOSFETs that are P-channel type third and fourth pre-charge MOSFETs,
The first and third precharge MOSFETs are each supplied with a control pulse that is turned on at a first timing to the gate,
The gate of the second precharge MOSFET is supplied with the circuit ground potential,
A negative voltage corresponding to the operating voltage is supplied to the gate of the fourth precharge MOSFET,
A semiconductor integrated circuit device in which a withstand voltage of each MOSFET constituting the negative voltage generating circuit is set to be not less than the above operating voltage and not more than twice the operating voltage . In claim 6,
A second negative voltage generating circuit having the same circuit configuration as the first negative voltage generating circuit;
The second negative voltage generation circuit performs an output operation at the first timing, performs a precharge operation at the second timing,
The output signal of the first negative voltage generation circuit is used as the control pulse used for the precharge operation of the second negative voltage generation circuit,
Using the output signal of the second negative voltage generation circuit as the control pulse used for the precharge operation of the first negative voltage generation circuit,
A semiconductor integrated circuit device in which outputs of the first and second negative voltage generating circuits are made common . In claim 7,
A plurality of word lines and a plurality of complementary bit line pairs;
Said word lines and provided between one of the complementary bit line, a gate is connected to the word line, one of a source, a drain corresponding the one connected address selected MOSFET and said complementary bit line A dynamic random access memory including a dynamic memory cell including a storage capacitor in which the other source and drain of the address selection MOSFET are connected to one electrode and a predetermined voltage is applied to the other electrode;
The output voltages of the first and second negative voltage generating circuit, the semi-conductor integrated circuit device is a substrate gate voltage of the address selection MOSFET.

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