JP3306048B2 - Dynamic semiconductor memory device and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to an improvement in a word line driving circuit section.

[0002]

2. Description of the Related Art In a DRAM having a memory cell composed of one transistor and one capacitor, a word line connected to the gate of a transfer gate MOS transistor is provided in order to completely transfer signals between the cell capacitor and the bit line. A potential boosted to a value higher than the “H” level of the bit line is applied. On the other hand, DRAMs are becoming more and more highly integrated due to miniaturization of elements. The miniaturization of this device is mainly performed according to the scaling rule. As a result, the gate oxide film of the transfer gate MOS transistor is, for example, 25 nm in 1 MDRAM and 16 MDR.
15 nm for AM and 10 nm for 64 MDRAM
The film gradually becomes thinner. Due to the thinning of the gate oxide film, a temporal destruction (Ti
me Dependent Dioxide Breakdown (TDDB) is a major problem. This problem will be specifically described with reference to the drawings.

FIG. 20 shows a word line drive of a conventional DRAM.
3 shows a configuration of a moving circuit unit. MOS transistor Q₁ ~ Q
₃ And capacitor C₂ Constitutes a word line booster circuit
ing. This booster circuit is a peripheral circuit part of a DRAM chip.
It is provided in. MOS transistor Q₁ Is the boost
Capacitor C₂ First, precharge the terminal N1
Type, n-channel charging transistor for
You. E-type, p-channel MOS transistor Q_Two 
And an E-type, n-channel MOS transistor Q _Three 
Is the boosting capacitor C₂Of the second terminal N_Two Control the potential of
And a driving circuit for controlling the driving circuit. MOS transistor
Star Q₁ Is the clock boosted by the charge pump circuit.
Φ₁ Is controlled by the step-up capacitor C_Two First
Terminal N₁ Power supply potential V_ccPre-charge. address
Before the clock φ_Two Is "H" level,
Is the first terminal N_Two Are kept at the “L” level. A
Dress is fixed and clock φ_Two From "H" level
When it changes to “L” level, the p-channel MOS transistor
Star C₂Is on, n-channel MOS transistor Q_Three But
Turned off, capacitor C₂Of the second terminal N_Two To
An “H” level potential is applied, and the first
Terminal N₁ , A boosted potential is obtained. This boosted potential is
Several decoder transformers are connected via the drive line WDRV.
A transistor (two MOS transistors Q in the figure)_Four , Q
_Five ) Via the selected word line W of the memory cell array.
L. As a result, a plurality of
Memory cell M₁ , M_Two,… Is selected and the selki
Capacitor and bit line BL₁, BL_TwoExchange of signals with
It is.

[0004] In such a word line driver circuit, a first terminal N ₁ of the boosting capacitor C ₂ is pre-charged to V _cc, a second terminal N ₂ is to be lifted from V _ss to V _cc . It represents the capacitance of the capacitor C ₂ in C _2, also C ₁ capacity of a single word line WL, the first capacitor C ₂
Word line drive line WD of the terminal N ₁ to word line WL
And C _3, including all the capacity of the capacitor and MOS transistor associated therewith the RV. Then, when the boosted potential is applied to word line WL, actual word line potential VWL
Is distributed charge capacity C ₂ is the capacitance C ₁ and _{C 3, VWL = (2C 2} + C 3) · V cc / (C 1 + C 2 + C
₃ ) Generally the capacitance C ₂ of the boosting capacitor is larger than the word line capacitance C _1, the power source potential _{V cc} dependence of the boosted potential VWL of the word _{line, (2C 2 + C 3)} / (C 1 + C 2 + C 3)> 1 In a relationship. On the other hand, the “H” level side of the bit line potential VBL is _Vcc . Therefore, the _Vcc dependency of the word line boosted potential is larger than that of the bit line.

FIG. 21 shows such _Vcc dependence of the word line boosted potential and the bit line potential. From the original purpose of word line potential boosting, at V _ccmin which is the lower limit of the chip operation guarantee range of the power supply potential, the word line boosted potential V _WL is higher than the bit line “H” level potential by the transfer gate MOS transistor (cell transistor). )
Must be higher by the threshold voltage V _T1 . 21st
The figure shows a case where V _WL = V _BL + V _T1 at Vccmin. When performing such a word line boosting, in the upper limit of the power supply potential V _CCmax guaranteed operating range of the chip as clear from FIG. 21, the word line boost voltage V _WL bit line "H" level potential V _BL Than (2C ₂ + C ₃ ) · V _ccmax / (C ₁ + C ₂ + C ₃ ) −V
_CCmax = Only higher _{(C 2 -C 1) · V} ccmax / (C 1 + C 2 + C 3). This is as follows: ΔV = (C ₂ −C ₁ ) · (V _ccmax −V _ccmin ) /
It means that it is extra high by (C ₁ + C ₂ + C ₃ ). This extra boosting of the word line potential gives a large stress to the gate oxide film of the cell transistor, and causes chip failure and reliability deterioration due to the TDDB.

On the other hand, _if the word line boosted potential is set to an optimal condition that the word line boosted potential is higher than the bit line potential by the threshold value at the upper limit _Vccmax of the power supply potential, as apparent from FIG. _{At ccmin} , the "H" level potential writing to the bit line is not sufficiently performed. Assuming that the TDDB limit is, for example, 5 V, the shaded region in FIG. 21 is a region where the write operation margin is sufficient.

Further, in the conventional word line driving circuit system,
There are also the following problems. That is, the maximum electric field effective for the actual TDDB is V _WL / T _{OX according} to the relationship between the word line potential V _WL and the gate oxide film thickness T _OX of the cell transistor.
Is a function of For this reason, although the TDDB varies due to the variation in the gate oxide film thickness due to the process conditions, the word line drive circuit does not compensate for it. Also, if the threshold value of the cell transistor also fluctuates due to variations in the process conditions, especially if it fluctuates to the higher side, "H" level writing to the memory cell cannot be performed sufficiently. No compensation is made for such a threshold variation.

[0008]

As described above, the conventional D
In comprise RAM, due to the large V _cc dependence of the word line boost voltage, it is impossible to achieve both the reliability ensuring a sufficient "H" level write and V _CCmax in V _Ccmin, The gate oxide film There is a problem that the word line boosted potential is not compensated for variations in process conditions such as thickness and threshold.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a DRAM having a word line driving circuit capable of performing sufficient "H" level writing without applying an unnecessarily high electric field to a gate oxide film.

The present invention is also directed to a DRAM having a word line drive circuit for compensating TDDB fluctuation and fluctuation of "H" level write margin with respect to fluctuation of process conditions.
The purpose is to provide.

[0011]

According to the present invention, there is provided a method of controlling a dynamic type semiconductor device having first and second word line boosted potential generating circuits for applying a boosted potential to a selected word line. Operates using the output potential of the step-down potential generating circuit for stepping down the external power supply potential as a power supply, and the step-down potential generating circuit does not depend on the power supply potential output from the first reference potential generating circuit. 1 reference potential output as input, comparing the first reference potential output with the output potential of the step-down potential generation circuit,
The step-down potential is generated, and the word line boost potential is compared with the reference potential using the step-down power supply potential as a reference potential, and when the word line boost potential becomes a predetermined value or less,
A second word line boosting circuit for boosting a word line boosted potential, wherein the first reference potential generating circuit uses a threshold voltage of a MOS transistor on the same chip, so that gate insulation can be performed independently of a power supply voltage; A reference potential having a portion proportional to the film thickness is generated. In the MOS transistor, the absolute value of the threshold portion proportional to the gate insulating film thickness is larger than the absolute value of the threshold portion not proportional to the gate insulating film thickness. A method of controlling a dynamic semiconductor memory device having a threshold value is provided.

The present invention relates to a semiconductor device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit is connected to a selected word line. A step-up capacitor having a terminal and a second terminal as a drive terminal, and a first terminal being kept at a first potential (V ₁ ) while the second terminal is kept at “L” level. In charging means, at the time of charging, a potential boosted to a value equal to or higher than a value obtained by adding a threshold to the first potential due to capacitive coupling is input to a gate, a drain is connected to an external power supply potential (V _CC ), and a source is A charging circuit having an NMOS transistor (Q ₁ ) connected to a first terminal, and a dependence on the variation of an external power supply potential (V _CC ) in a predetermined power supply voltage range as the second potential (V ₂ ) Step-down potential generating circuit (2) that generates a small potential
0 ₁ ) and changing the second terminal from the “L” level state to the second
And a capacitor driving circuit for obtaining a boosted potential at the first terminal by raising the potential to a potential (V ₂ ).

The present invention relates to a semiconductor device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit is connected to a selected word line. A step-up capacitor (C ₂ ) having a first terminal and a second terminal as a drive terminal, and the first capacitor connected to the first terminal while the second terminal is held at “L” level.
Is a means for pre-charging the terminal of the first potential to the first potential (V ₁ ). At the time of charging, a potential boosted to a value higher than a value obtained by adding a threshold to the first potential by capacitive coupling is input to the gate, and the drain is externally An NMOS transistor (Q ₁ ) connected to a power supply potential (V _CC ) and having a source connected to the first terminal
A step-down potential generating circuit (20 ₁ ) that generates a potential that is less dependent on fluctuations in an external power supply potential (V _CC ) within a predetermined power supply voltage range as the second potential (V ₂ ); A capacitor driving circuit that obtains a boosted potential at the first terminal by raising the second terminal from the “L” level state to a second potential (V ₂ ), wherein the potential generating the second potential is provided. The generation circuit has a flat first power supply function that does not depend on the external power supply potential in a predetermined operation state.
The reference potential generated from the first reference potential generating circuit for generating the reference potential is compared with the reference potential generated from the second potential generating circuit using the external power supply potential as a power supply. A second potential independent of a power supply potential is generated, and the first reference potential is equal to M
The MOS transistor is generated based on the threshold value of the OS transistor, and the MOS transistor has a threshold value whose absolute value in proportion to the gate insulating film thickness is larger than the absolute value of the threshold value portion not proportional to the gate insulating film thickness A dynamic semiconductor memory device characterized by having:

According to the present invention, in a semiconductor memory device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, the word line boosted potential generating circuit compensates for a potential variation due to a leak of the word line. A potential compensating circuit for controlling the operation of a ring oscillator for driving a charge pump circuit by detecting a potential fluctuation of the boosted potential, and detecting the potential of the word line boosted potential at a predetermined operation without depending on an external power supply potential. And the boosted potential is compared and detected, and the reference potential is the MOS
Since the MOS transistor is generated with reference to the threshold value of the transistor, the absolute value of the threshold value portion proportional to the gate insulating film thickness of the MOS transistor is not dependent on the power supply voltage. Provided is a dynamic semiconductor memory device having a threshold larger than the threshold value.

According to the present invention, in a semiconductor memory device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, the word line boosted potential generating circuit compensates for a potential variation due to a leak of the word line. A potential compensating circuit for controlling the operation of a ring oscillator for driving a charge pump circuit by detecting a potential fluctuation of the boosted potential, and detecting the potential of the word line boosted potential at a predetermined operation without depending on an external power supply potential. And the boosted potential is compared and detected, and the potential of the word line boosted potential is detected by changing a detected potential level between when the charge pump is operating and when the charge pump is stopped.

The present invention relates to an MO formed on an on-chip.
A potential corresponding to the threshold value of the S transistor is generated as a first reference potential, the first reference potential is used as an input to a differential amplifier, and the output potential of the operational amplifier is set to a gate of a PMOS transistor using an external power supply potential as a source. And a second reference potential (V ₁ ) is generated by comparing the reference potential according to the output from the drain of the PMOS with the first reference potential and performing feedback and amplification so as to be equal. The potential according to the second reference potential (V ₁ ) and the potential according to the internal power supply potential (V _WL ) are input to a current mirror type differential amplifier and feedback is performed so that they are equal to each other. A semiconductor memory device that generates a potential is provided.

According to the present invention, the _Vcc is applied to the word line boosting circuit.
By using a potential having a small dependency, preferably a potential having no dependency on Vcc, it is possible to guarantee TDDB when _Vcc is high, and to sufficiently write "H" level when _Vcc is low. Can be done.

Further, according to the present invention, as a result of the word line boosted potential fluctuating following the change in the gate oxide film thickness of the transfer gate MOS transistor, the word always reaches the TDDB limit even if the gate oxide film thickness changes. The effect that the line can be boosted can be obtained. As a result, the read speed of the DRAM can be increased, and a maximum operation margin can always be obtained. Further, even if the threshold value of the transfer gate MOS transistor fluctuates due to the variation in the process conditions, the word line boosted potential fluctuates in accordance with the variation, so that insufficient "H" level writing does not occur.
Furthermore, at a high power supply potential equal to or higher than the TDDB limit, a word line boosted potential depending on the power supply potential can be obtained.
It can be effectively used for the acceleration test of M.

Further, according to the present invention, word line leak compensation is performed, and an optimum word line boosted potential can always be obtained.

[0020]

Embodiments of the present invention will be described below.

FIG. 1 shows a main structure of a word line driving circuit of a DRAM according to one embodiment. FIG. 2 shows a potential generating circuit used in the word line boosting circuit shown in FIG. 1, and FIG. 3 shows a charge pump circuit. FIG. 3 is a block diagram showing the overall configuration of the DRAM.

As shown in FIG. 3, the DRAM of this embodiment is
Are a row address buffer 1 and a column address buffer 2 for taking in an external address, control circuits 3 and 4 for controlling and driving these address buffers 1 and 2, a column decoder 5 for decoding a taken-in address.
A row decoder 6, a memory cell array 8 in which memory cells of one transistor / one capacitor driven by outputs of these decoders are arranged, a word line booster circuit 7 for applying a boosted potential to a selected word line, and a memory cell array 8
Amplifier and I / O gate 9 for exchanging data with input / output buffer 10, input buffer 10 for latching input / output data,
An output buffer 11 is included. Although not shown in the figure,
It has a substrate bias generation circuit and a refresh counter for self-refreshing the memory cell array.
These main components are not different from the conventional DRAM. Further, if necessary, a serial address counter for generating a serial address in the column direction may be provided for performing serial access.

The word line driving circuit section including the word line boosting circuit 7 is configured as shown in FIG. The basic configuration is the same as that of the conventional one shown in FIG. 20, and accordingly, portions corresponding to FIG. 20 are denoted by the same reference numerals as in FIG. Word line boosting circuit 7, the boosting capacitor C _2, n-channel MOS transistor Q ₁ constituting a charging circuit for pre-charging the first terminal N ₁ of the boosting capacitor C2, and a second terminal N p-channel MO constituting the capacitor driving circuit for driving the ₂
S transistor Q ₂ and n-channel MOS transistor Q ₃
Having. Different from the conventional, first prepared potential generating circuit 20 ₁ and the second potential generating circuit 20 _2, the first terminal of the boost capacitor from each generating an internal voltage having no power supply voltage dependent The point is that the first potential V ₁ for precharging N ₁ and the second potential V ₂ at the “H” level applied to the second terminal N ₂ are generated. These potential generating circuit ₂₀ 1, 20 _2, the control signal phi _1, with phi ₂ of the generator, included in the fourth diagram of RAS-related control circuit 3.

The first potential generating circuit 201 for generating the first potential V ₁ in FIG. ₁ is constructed, for example, as shown in FIG. That is, by three diodes connected n-channel MOS transistor Q ₁₁ to Q ₁₃ connected in series circuit of the load resistance R _1, the reference potential generating circuit is configured. The output of this reference potential generating circuit is an operational amplifier O
It is input to the inverting input terminal of P. P-channel MOS transistors Q ₁₄ and dividing resistor R _a to gate inputs the output of the amplifier OP, R _b are connected in series between the power supply potential V _cc ground potential. The connection point between the resistors _Ra and _Rb is the operational amplifier O
It is connected to the non-inverting input terminal of P.

[0025] From the first reference potential generating circuit potential generating circuit 20 ₁ is not dependent on the supply voltage V _cc, the reference potential V _c determined mainly by the threshold voltage of the MOS transistor Q ₁₁ to Q ₁₃ obtained . And the reference potential V _c, the resistance R _a, and the difference between the voltage dividing point potential of R _b is amplified, the first potential V
_{As 1} , _a potential of V ₁ = V _c · (R _a + R _b ) / R _b is obtained.

[0026] for the second potential generating circuit 20 ₂ to obtain a second potential V _2, using the same circuit configuration as Figure 2.
In this case, when using the equal first potential V ₁ and a second potential V ₂ may share one potential generating circuit.

The control signal φ _{1 applied} to the gate of the charging MOS transistor Q ₁ of the word line boosting circuit 7 is such that when the first potential V ₁ is lower than the power supply potential _Vcc below the threshold value of the transistor Q ₁ V _cc may be used. When the first potential V ₁ is higher than this, the power source potential V _cc signal boosted from is used by as the control signal φ1 for example a charge pump circuit. FIG. 3 shows a configuration example of the charge pump circuit. This charge pump circuit includes charge storage capacitors C ₁₁ and C ₁₂ , an n-channel MOS transistor Q ₁₅ for charging the capacitor C ₁₁ , and diode-connected n-channel MOS transistors Q ₁₆ and Q ₁₇ for charge transfer. It consists of. Complementary clock signals φ _R , φ _R obtained from, for example, a ring oscillator are applied to one ends of the capacitors C ₁₁ and C ₁₂ .

The control signal φ ₁ boosted by this charge pump circuit is applied to the charging MOS transistor Q ₁ shown in FIG.
By being input to the gate, without lowering the threshold voltage at the charging MOS transistor Q, thus the first potential V ₁ is the pre-charging the first terminal N ₁ of the boosting capacitor C ₂ You.

The operation of boosting the word line in this embodiment will be described. FIG. 5 is a timing chart. Before address is determined, the control signal phi ₂ is "H" level, thus the second terminal N ₂ of the capacitor C ₂ is at "L" level.
At this time, the charging MOS transistor Q ₁ is controlled by the boosted control signal clock φ ₁ as described above, and the first potential V ₁ is applied to the first terminal N ₁ of the boosting capacitor C ₂ >
Pre-charge. If the address is to the control signal phi ₂ confirm changes to the "L" level from "H" level, p-channel MOS transistor Q ₂ is turned on, n-channel MOS transistor Q ₃ is turned off, the capacitor C ₂ 2 the terminal N ₂ second potential V ₂ given the boosted potential is obtained to the first terminal N ₁ by capacitive coupling. This boosted potential is applied to clocks φ ₃ and φ ₄ via word line drive line WDRV.
Is supplied to the selected word line WL of the memory cell array 8 through the decoder transistors Q ₄ , Q _5, etc. Thereby, a plurality of memory cells M ₁ , M ₂ ,... Along the word line WL are selected, and signals are exchanged between the cell capacitors and the bit lines.

As in the conventional case, the capacitance of the word line is C₁, War
Between the output terminal of the gate booster circuit 7 and the selected word line.
The accompanying capacity is C_ThreeThen, in this embodiment, the word
Line boost potential V_WLIs V_WL= V₁・ (C_Two+ C_Three) / (C₁+ C_Two+ C_Three) + V_Two・
C_Two / (C₁+ C_Two+ C_Three). First potential V₁And the second potential V_TwoAre equal
Is the boosted word line potential V _WLIs V_WL= V₁・ (2C_Two+ C_Three ) / (C₁+ C_Two+ C_Three).

FIG. 6 shows the power supply potential dependence of the boosted word line potential VWL according to this embodiment. As is apparent from the above equation, in this embodiment, the word line boosted potential V
_WL is determined by the first electric potential V ₁ and the second electric potential V ₂ that is independent of the power supply potential V _cc, shows a constant value in the operation guaranteed range _{V ccmin} ~V _ccmax power supply potential. Accordingly, sufficient "H" level writing can be _performed at the lower limit _Vccmin of the power supply potential, and an unnecessary high electric field is prevented from being applied to the gate oxide film of the cell transistor at the upper limit _Vccmax .

In the above embodiment, the word line booster circuit
First potential V used₁And the second potential V_TwoBoth power supply potential
, But one of them is the power supply potential
V _ccIt may be. For example, FIG.
The second potential V of the_TwoInstead of power supply potential V
_ccFIG. 8 also shows the first potential V
Power supply potential V instead of 1_ccThis is the case where is used. Fig. 7
Of the word line boosted potential V_WLIs V_WL= V₁・ (C_Two+ C_Three) / (C₁+ C_Two+ C_Three) + V_cc
・ C_Two / (C₁+ C_Two+ C_Three). In the case of the booster circuit of FIG.
Rank V_WLIs V_WL= V_cc・ (C_Two+ C_Three) / (C₁+ C_Two+ C_Three) + V_Two
・ C_Two / (C₁+ C_Two+ C_Three).

In any case, the word line boosted potential VWL
, The power supply potential dependency is not zero, but the slope is smaller than one. FIG. 9 shows the power supply potential dependency of these word line boosted potentials in correspondence with FIG. Also in these cases, compared with the case where the word line boosted potential has the power supply potential dependency as shown in FIG.
It is possible to achieve both the relaxation of the electric field of the gate oxide film at x and the sufficient "H" level writing at Vccmin.

Next, a method for changing manufacturing process conditions is described.
An embodiment in which the compensation of the boosted potential of the ground line is performed
You. The main configuration of the word line drive circuit is shown in the previous embodiment.
It is the same as FIG. In this embodiment, the word line
First potential V applied to booster circuit 7₁Generating potential
The circuit is configured as shown in FIG. As shown,
First and second two reference potential generating circuits 21₁, 21₂Use
Can be. First reference potential generation circuit 21₁Is a certain level
At a power supply potential higher than
A first reference potential proportional to the gate oxide of the transistor
V_c1Is to occur. Second reference potential generation
Circuit 21₂ Is the power supply potential and the cell transistor threshold
The second reference potential V corresponding to a large value variation_c2What causes
It is. Specific examples of these configurations will be described later. First group
Quasi-potential generation circuit 21₁ The output of the first amplifier circuit 22₁ 
Is input to First amplifier circuit 22₁ Is the operational amplifier O
P ₁And this amplifier OP₁チ with the output of as the gate input
Channel MOS transistor Q₂₁₁And voltage dividing resistor R
_a1, R_b1Are connected in series. to this
More first amplifier circuit 22₁ From the first reference potential V_c1To
A proportional output potential is obtained. Second reference potential generation circuit
21₂The output of the second amplifier circuit 22₂Is input to
This second amplifier circuit 22₁Is the operational amplifier OP_TwoAnd this
Amplifier OP_TwoP-channel M whose output is the gate input
OS transistor Q₂₁₂ And voltage dividing resistor R_a2, R
_b2Are connected in series. Resistance R_a2And R
_b2Is the operational amplifier OP_Two To non-inverting input terminal
It is connected. These first and second amplifier circuits 22₁You
And 22₂Output terminal is connected to wired OR connection 23
And the two amplifier circuits 22₁, 22₂ Output potential of
The higher potential is taken out.

[0035] Figure 11 (a) ~ (f) is a first configuration example of a reference potential generating circuit 21 _1. FIG. 11 (a) shows a load resistor R ₂ and three diode-connected n-channel MOs.
S transistor Q ₃₁ to Q ₃₃ are serially connected between the power supply potential V _cc and ground potential. Here, the three-stage MOS transistors Q _{31 to} Q ₃₃ are n-channel MOS transistors using n-type polycrystalline silicon gate electrodes without channel ion implantation, or the thresholds of the gate transistors are increased by performing channel ion implantation. An n-channel MOS transistor made to be approximately proportional to the film thickness is used. The resistance value of the load resistor R ₂ is made sufficiently larger than that of the MOS transistor Q ₃₁ to Q _33. The output terminal at this time, in a range exceeding the sum of the threshold of the power supply potential V _cc of certain level or three-stage MOS transistor Q ₃₁ to Q _33, the total value of the threshold is a first reference potential Obtained as V _c1 . The details are as follows.

[0036] Normally, the threshold voltage of the no n-channel MOS transistor of the channel ion implantation of the n-type gate _{electrode, V T = -V FB + 2φ} F + γ (φ F + V SUB) is represented by 1/2 · _{T OX} You. Here, V _FB is a flat band voltage, φ
_F is the Fermi level, γ is a proportional constant, V _SUB is the substrate bias voltage, and T _OX is the gate oxide film thickness. And n
Channel M without channel ion implantation of gate electrode
The OS _{transistor, | -V FB + 2φ F |} «γ (φ F + V SUB) from a 1/2 · _{T OX,} the threshold voltage _{V T,} the gate oxide film thickness T
_It is almost proportional to _OX . This is V _T (T
_OX ). The reference potential generating circuit thus FIG. 11 (a), the power supply potential Vcc certain value or more, it is possible to obtain the first reference potential V _c1 proportional to the gate oxide film thickness TOX regardless of the power supply potential.

FIG. 11 (b) shows M in FIG. 11 (a).
Only the substrate bias condition of the OS transistor is different. Even if the substrate bias is different, only the value of (φ _F + V _SUB ) ^1/2 is different in the above-described threshold voltage equation, and the proportional relation to the gate oxide film thickness does not change. Therefore, for example, according to the configuration of FIG. 11 (b), the relationship V _T ′ (T _OX ) of FIG. 13 is obtained.
Thus when the load resistance R ₂ is large, FIG. 11 (a)
By the reference potential generation circuit shown in (b), a potential V _c1 = K · T _OX (K is a proportional constant) proportional to the gate oxide film thickness T _OX (1) is obtained as the first reference potential V _c1. . This relationship is not directly related to the number of stages of MOS transistors, thus also using one of the MOS transistors Q _31, as shown in FIG. 11 (c), the reference potential generating circuit having a similar function is obtained. In the above reference potential generating circuit, since the n-channel MOS transistor does not perform channel ion implantation, there is little variation with respect to process conditions (ion implantation conditions and temperature) other than the gate oxide film thickness, and the gate oxide film thickness T _OX. A stable reference potential proportional to the reference potential can be generated. Preferably, at V _c1 = K · T _OX , the proportionality constant K is set to 0.6 or more.

On the other hand, in FIGS. 11 (a) to 11 (c), an n-channel MOS transistor which has been subjected to channel ion implantation may be used. In that case, the ion implantation conditions are selected such that the deviation ΔV _FB of the flat band due to the ion implantation satisfies −V _FB + ΔV _FB + 2φ _F ０0. This makes it possible to generate a reference potential substantially proportional to the gate oxide film thickness even when using a MOS transistor in which channel ion implantation has been performed. In n-channel MOS transistor of the p-type gate electrode is also because the threshold voltage is represented by _{V T = V FB + 2φ F} + γ (φ F + V SUB) 1/2 · T OX, also performs a channel ion implantation , V _FB −ΔV _FB + 2φ _F ０0. Even when such a MOS transistor is used, a reference potential proportional to the gate oxide film thickness can be obtained.

[0039] FIG. 11 (d) is an example in which a p-channel MOS transistor Q ₃₄ is not performed channel ion implantation of p-type gate electrode. In this case, the threshold voltage of the MOS transistor Q34 _{is, V T = -V FB + 2φ} F -γ (φ F + V SUB) becomes 1/2 · _{T OX.} If T _OX is sufficiently large, | −V _FB + 2φ _F | ≪γ (φ _F + V _SUB ) ^1/2 · T _OX , so that a reference potential proportional to the gate oxide film thickness can also be obtained. As in the case of using an n-channel MOS transistor without channel ion implantation of the n-type gate electrode, a p-channel MOS transistor without channel ion implantation of the p-type gate electrode has a thickness other than the gate oxide film if process conditions are determined. , A reference potential having a stable gate oxide film thickness dependency can be generated.

On the other hand, a p-channel MOS having an n-type gate electrode
For the transistor, Without channel ion implantation, the threshold voltage _{V T = V FB + 2φ F} -γ (φ F + V SUB) becomes 1/2 · _{T OX.} This relative thickness of the gate oxide film, is shown as a straight line -V _T2 shown in FIG. 13, not proportional to the gate oxide film thickness. In this case as well, if a deviation ΔV _FB of the flat band voltage is generated by implanting boron into the channel ions, for example, | V _FB + 2φ _F −ΔV _FB | An electric potential can be obtained. Also, when a p-channel MOS transistor is used, similarly to the case of an n-channel MOS transistor, a plurality of stages can be connected in series to form a reference potential generating circuit.

FIGS. 11 (e) and 11 (f) show n-channel MOSFETs at the load resistance R2 in the configuration of FIG. 11 (c).
It uses an OS transistor Q ₃₅ and a p-channel MOS transistor Q ₃₆ . The MOS transistors Q ₃₅ and Q ₃₆ for load resistance use those satisfying the condition of channel width / channel length≪1 in order to make the resistance sufficiently high. Thus, a first reference potential Vc1 proportional to the gate oxide film thickness can be obtained as in the case of FIG. 11 (c).

[0042] Figure 12 (a) ~ (d) is a second configuration example of a reference potential generating circuit 21 ₂ in FIG. 10. Fig. 12 (a)
, The n-channel MOS transistor Q ₄₁ is
This is a MOS transistor formed under the same process conditions and the same shape as the transistor, which is diode-connected and connected in series between the power supply potential _Vcc and the ground potential together with the resistors R ₃ and R ₄ . Resistance values of the resistors R _3, R ₄ shall be sufficiently larger than that of the MOS transistor Q _41.

The reference potential _{V c2} of the output potential obtained at this time, that is, the second, when the threshold voltage of the MOS transistor Q ₄₁ and _{VTC, V c2 = (V cc} -V TC) R 3 / (R 3 + R _{4) + V TC = {R} 3 / (R 3 + R 4)} become _{(V cc + V TC R 3} / R 4) ... (2).

From the equation (2), the second reference potential Vc2
Is a value that depends on the power supply potential Vcc and varies according to the variation of the gate threshold voltage VTC of the MOS transistor.

[0045] Figure 12 (b) are those having different substrate bias condition of the MOS transistor Q ₄₁ of Figure 12 (a). This is because only the threshold voltage of the MOS transistor is different, and the relationship of equation (2) does not change. Fig. 12
(c) is an arrangement of a resistor R ₄ and MOS transistor Q ₁₂ obtained by reversed with Figure 12 (a), the reference potential obtained is not changed. FIG. 12 (d) is an example in which a plurality of MOS transistors are connected in parallel to obtain the same reference potential as in FIG. 12 (a). Since the MOS transistor used for the memory cell is extremely fine, the process condition is the same as that of the cell transistor, and a plurality of larger MOS transistors are formed and connected in parallel in this manner, so that the equation (2) can be obtained. A second reference potential Vc2 represented can be obtained.

Next, returning to FIG. 10, the operation will be described in detail.
explain. First reference potential generation circuit 21 as described above
₁And second reference potential generating circuit 21₂The number obtained from
1 reference potential V_c1And the second reference potential V_c2Is
Amplifying circuit 22₁, 22 ₂Amplified by sand
That is, the first amplifier circuit 22₁Output potential V_a1Is (1)
Multiplying the value of the equation by the amplification factor, V_a1= ｛(R_a1+ R_b1) / R_b1｝ KT_OX ... (3) On the other hand, the second amplifier circuit 22₂ Output potential V_a2
Is obtained by multiplying the value of equation (2) by the amplification factor, and V_a2= ｛(R_a2+ R_b2) / R_b2｝ ｛R₃ / (R₃ + R₄)｝ (V_cc+ V_TCR₃ / R₄) (4)

FIG. 14A shows the power supply potential dependency of these output potentials V _a1 and V _a2 . Output potential V
_a1 is the level above which there is a power source potential _{V cc} regardless of the power source potential _{V cc,} shows a constant value which depends only on the gate oxide film thickness _{T OX.} The output potential _Va2 is _equal to the power supply potential _Vcc and M
This shows a value depending on the threshold value of the OS transistor. These two output potentials are connected by a wired OR connection 23.
The higher value is output with priority, and eventually the first
4 An output of the potential V1 as shown in FIG.

The word line boosted potential VWL obtained by applying the thus obtained potential V1 to the word line boosting circuit 7 in FIG. 1 is as follows. First, (3) the potential V _a1 is charged to the boost capacitor alone by equation this is considered a case that is applied to the word line, when ignoring the capacitance C3 of the word line drive line WDRV, V _{WL = {2C 1} / (C ₁ + C ₂ )｝ ｛(R _a1 + R _b1 ) / R _b1 ｝ KT _OX (5) Similarly, considering only the potential Va2 according to the equation (4), V _WL = {2C ₁ / (C ₁ + C ₂ )} (R _a2 + R _b2 ) / R _b2 ｝ {R ₃ / (R ₃ + R ₄ )} to become _{(V cc + V TC R 3} / R 4) ... (6). Therefore, as a whole, the larger of equations (5) and (6) is given as the word line boosted potential.

FIG. 15 shows the power supply potential dependency of the word line boosted potential obtained as described above. Polygonal line V ₁ of the drawing is that of FIG. 14 (b), thereby the word line boosting potential VWL obtained is represented by the broken line as also FIG. The maximum is V ₁ = V _cc , C ₁
Of · _{C 2} at the time, it is VWL = _{2V cc.} Linear portion of the power source potential V _cc is small range of the word line boost voltage V _WL represented by a polygonal line L ₁ is this, FIG. 14 (a)
Corresponding to the portion which increases in proportion to the limited without the power supply potential Vcc by the threshold of potential V _a1. Flat part L ₂
Corresponds to _a flat portion of the potential Va in FIG. 14A, that is, _a portion that depends only on the gate oxide film thickness _{TOX of the} MOS transistor. Further, the straight line L in the region where the power supply potential _Vcc is high
₃ is the potential _{Va2 in} FIG.
This corresponds to a portion depending on the threshold value of the OS transistor.

The effect of this embodiment will be described below. Now, assuming that the maximum electric field of the TDDB is Emax, {2C ₁ / (C ₁ + C ₂ )} (R _a1 + R _b1 ) / R _b1 ｝ K
= If Emax, from (5), and _V WL = Emax · _{T OX.} That is, the word line boosted potential V _WL shown in FIG.
Flat portion _{L 2} of the constant a becomes in TDDB limit despite fluctuations in the power source potential _{V cc,} and the gate oxide film thickness _{T OX}
Becomes a value that varies in proportion to this variation. Therefore, in addition to the effect of the previous embodiment, the word line boosted potential is automatically compensated for the influence of the variation of the gate oxide film thickness due to the process variation. _Also, C 1 · _{C 2,} and 2Vcc <When a Emax · _{T OX} is a limit 2V word line boosting voltage boost circuit
_cc . In summary, even if the variation of the gate oxide film thickness _{T OX} occurs, the word line boost voltage _{V WL,} when _{2V cc> Emax · T OX,} V WL
= 2Vcc until, at the time of _{2V cc ≦ Emax · T OX,} V
_WL = Emax · _{T OX} certain to become. Thereby, TDD
The "H" level writing margin to the memory cell and the operation margin of the power supply potential are sufficient without causing the reliability deterioration due to B, and the reading speed is increased by the sufficient increase of the word line potential. In addition, compensation for automatically keeping the word line boosted potential at the TDDB limit is automatically performed for variations in process conditions.

On the other hand, in the equation (6), {2C ₁ / (C ₁ + C ₂ )} (R _a2 + R _b2 ) /
When _{R b2} {R 3 / (} R 3 + R 4)} = 1 to (6) becomes _{V WL = V cc + V T} CR 3 / R 4 ... (7). When the value of R ₃ / R ₄ is changed, (R _a2 + R
By changing _b2 ) / _Rb2 , the condition of the above equation (7) can be set. Here, "H" of the memory cell is actually
The word line potential required for level writing is
The threshold voltage of the transistor as VT1, a _{V WL = V cc + V T1} ... (8). The MOS transistor Q ₄₁ and the cell transistor shown in example used in reference potential generating circuit in a word line boosting circuit Figure 12 (a), the process conditions and the shape as described above are the same, the substrate bias only Are different.
Now, the substrate bias of the cell transistor is V _SUB1 = V _cc + V, where the well potential of the cell array is V _BB.
BB . The substrate bias of the MOS transistor Q41 in the reference potential generating circuit of the word line boosting circuit is shown in FIG.
In the case of the circuit configuration of (a), V _SUB2 = (V _cc −V _TC ) R ₃ / (R ₃ + R ₄ ). Therefore, V _SUB1 > V _SUB2 and
As a result, _VTC < _VT1 . The difference between this threshold is compensated by _{R 3 / R 4, V T1} ~V TC if R ₃ / R _4, as the minimum required word line potential to the "H" level write, _V WL = V can be obtained _{cc + V TC R 3 / R} 4 ~V cc + V T1. In FIGS. 12 (b) and 12 (c), the same relationship can be set since only the substrate bias changes.

By satisfying the above relationship,
"H" level writing to the memory cell is guaranteed, and the word line boosted potential is automatically compensated even when the threshold value of the cell transistor fluctuates due to process conditions.

Further, when the acceleration test of the DRAM is performed by forcibly increasing the power supply potential _Vcc , the word line boosting potential V of FIG.
It can be utilized straight portion L ₃ of the _WL.

As described above, the word line boosted potential according to this embodiment follows a locus of L ₁ → L ₂ → L _{3 with} respect to the rise of the power supply potential as shown in FIG. Then, this locus and the minimum level _Vcc + V of "H" level writing
The hatched area in FIG. 15 surrounded by _T1 is a range where a sufficient write operation margin can be obtained. As is clear from the comparison with the conventional operation margin area shown by oblique lines in FIG. 21, the margin is greatly improved.

As described above, the present invention relates to a DRAM
Basically, a constant value independent of the power supply potential is used as the word line boost potential. However, in this case, the word line potential actually fluctuates due to leakage. This leak mainly occurs from the diffusion layer of the MOS transistor connected to the word line. Therefore, in the present invention, it is desirable to perform word line leak compensation. An embodiment of a DRAM provided with such a leak compensation circuit will be described below. As the word line driving circuit, any of the embodiments described above may be used, and the following description is limited to the leak compensation circuit section.

FIG. 16 is a block diagram showing a structure of a word line leak compensation circuit section. As shown in the figure, the leak compensation circuit section includes a word line potential _VWL and a reference potential VWL.
A comparison detection circuit 31 for comparing and detecting _REF is provided. The output of the detection circuit 31 makes the ring oscillator 3
2 is ON / OFF controlled, and this ring oscillator 32
The charge pump circuit 33 used in the word line boosting circuit is controlled by the output of the charge pump circuit 33.

FIG. 17 shows a specific example of the configuration of the comparison detection circuit 31. This comparison detection circuit includes n-channel MOS transistors Q ₅₃ and Q ₅₄ whose sources are commonly connected, p-channel MOS transistors Q ₅₅ and Q ₅₅ for supplying current to these transistors.
The main component is a current mirror type CMOS differential amplifier circuit composed of Q ₅₆ and switching n-channel MOS transistors Q ₅₇ and Q ₅₈ connected in series to a common source of the MOS transistors Q ₅₃ and Q ₅₄ . MOS transistor Q ₅₇ is controlled by the control signal VSW, MOS transistor Q ₅₈ is controlled by a separate control signal VM. The word line potential VWL is divided by the resistors r ₁ and r ₂ and input to the signal input terminal of the differential amplifier circuit, that is, the gate of the MOS transistor Q ₅₃ , and is input to the reference potential input terminal, that is, the gate of the MOS transistor Q ₅₄ . Is configured such that the reference potential V _REF is input after being divided by the resistors r ₃ and r ₄ . Switching n-channel MOS transistors Q ₅₁ , Q ₅₂ controlled by a control signal V _{SW for} turning on / off the input are inserted in series with these voltage dividing resistors r ₁ , r ₂ and r ₃ , r ₄ , respectively. ing. The output of the CMOS differential amplifier circuit is a p-channel MOS
Via the transistor Q _59, is taken out as a ring oscillator control signal V _RO via the output buffer. MOS
The drain of the transistor Q ₅₉ is connected to the power supply _{V cc,}
The source is grounded through the switching n-channel MOS transistor Q ₆₁ which is controlled by a control signal V _M. between the gate and drain of the p-channel MOS transistors Q _59, p-channel MOS transistor Q ₆₀ which is controlled by a control signal _{V SW} is provided.

In such a leak compensation circuit, the word line potential _VWL is set to the potential of the word line actually selected in the cell array or the pseudo word line set under the same load condition as the word line in the cell array. And the potential obtained from this is used. The reference potential V _REF for example, utilizes an internal potential V ₁ obtained from the first potential generating circuit 20 ₁ for use in the booster circuit part in the embodiment of Figure 1. And when it is below a certain value the word line potential V _WL, so that the ring oscillator control signal V _RO becomes "H" level, the value of the voltage dividing resistors r ₁ ~r ₄ is set.

FIG. 18 shows an example of the configuration of a ring oscillator controlled by a control signal _VRO obtained from the comparison detection circuit of FIG. That is, a circuit as shown is provided inside a ring oscillator configured by connecting a plurality of CMOS inverters in a ring shape.

The operation of the word line leak compensation according to this embodiment is as follows. The comparison detection circuit 31 in FIG.
Control signal _{V SW} and _{V M} is between "L" level, is kept in an inactive state. At this time, the output stage is a p-channel MO
S transistor Q ₆₀ is turned on deli, which p-channel MOS transistor Q ₅₉ by is held off the gate and drain are short-circuited. The n-channel MOS transistor Q ₆₁ is off. Therefore, ring oscillator control signal _VRO is at "L" level. At this time, in the ring oscillator 32 shown in FIG. 18, the p-channel MOS transistor Q ₇₄ and the n-channel MOS transistor Q ₇₃ are both off, and do not oscillate.

Control signal V_SWAnd V_MIs "H" level
, The comparison detection circuit 31 is activated. And wa
Line potential V_WLAt a higher value than a set value
Means that the output of the differential amplifier circuit is at "H" level,
Output stage p-channel MOS transistor Q₅₉Is off
Is kept. At this time, the n-channel MOSFET Q61 is turned off.
Control signal VRO is still at the “L” level.
To be kept. Word line potential V_WLIs less than or equal to the set value
, The output of the differential amplifier circuit becomes “L” level.
As a result, the output stage p-channel MOS transistor Q₅₉
Turns on. p channel MOS transistor Q₅₉No
Resistance and n-channel MOS transistor Q ₆₁On-resistance of
If a certain relationship is set in advance, the p-channel MOS transistor
Transistor Q₅₉Is turned on, the output control signal V
_ROBecomes "H" level. This control signal V_ROof
The transition to the “H” level causes the ring oscillation in FIG.
The oscillator 32 is activated to start oscillation, and
Signal φR and / φR are obtained. This allows the charge point
When the amplifier circuit 33 is driven, the word line booster circuit operates,
The lowered word line is boosted.

As described above, according to this embodiment, the word line can always be set to a desired value while compensating for the decrease due to the leak of the word line. Therefore, as described above, the reliability of the DRAM of the present invention using a constant word line boosted potential independent of the power supply potential is improved. Further, unnecessary power consumption can be reduced by operating the ring oscillator for word line boosting on and off instead of always operating as in the bit line embodiment.

FIG. 19 is a circuit diagram of the comparison detection circuit shown in FIG.
9 is a comparison detection circuit according to an embodiment modified in the form of a crab. I.e.
The voltage dividing resistor r in FIG.₂And the resistance r
₂₁, R₂₂And between their connection point and ground potential
Channel MOS transistor Q ₆₂And output this
Control signal V_ROIs controlled by

According to this embodiment, the operation of leak compensation is
A certain dead zone is formed. That is, the word line potential V
_WLIs higher than a predetermined value, and the output control signal V_ROIs “L”
During the level, the MOS transistor Q₆₂Is off and this
, The voltage dividing ratio on the word line potential VWL side is r₁/ (R
₂₁+ R₂₂). In other words, it is input to the differential amplifier circuit
Potential is V_WL・ (R₂₁+ R₂₂) / (R₁+ R₂₁+
r₂₂). When this falls below a certain value, the comparison detection
Road works and control signal V_{R O}= “H” level, phosphorus
Guoscillator works. And the control signal V_ROIs “H” level
When the bell, MOS transistor Q₆₂Is turned on
The word line potential V _WLOf the input side is r₁/ R
₂₁Becomes At this time, the potential input to the differential amplifier circuit
Is V_WL・ R₂₁/ (R₁+ R₂₁+ R₂₂). Therefore the ring oscillator worked and dropped
Word line potential V_WLRecovery to some extent,
Since the road does not have sufficient “H” level input,
Alternatively, the ring oscillator continues to operate.

As described above, according to this embodiment, the threshold value of the leak compensation circuit differs between when the word line potential decreases and when the word line potential increases, and a dead zone occurs in the leak compensation circuit. Therefore, a situation in which the word line potential oscillates due to leak compensation is prevented.

[0066]

As described in detail above, according to the present invention, it is possible to ensure the TDDB when the power supply potential _Vcc is high, and to write the "H" level when the power supply potential _Vcc is low. It is possible to provide a DRAM having a word line driver circuit which can be sufficiently performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a word line drive circuit section in a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a first potential generation circuit in FIG. 1;

FIG. 3 is a diagram showing a configuration of a charge pump circuit for driving the word line booster circuit of FIG. 1;

FIG. 4 is a block diagram showing an overall configuration of a DRAM according to an embodiment;

FIG. 5 is a timing chart for explaining the operation of the word line drive circuit of FIG. 1;

FIG. 6 is a diagram showing power supply potential dependence of a word line boosted potential obtained by an example.

FIG. 7 is a diagram showing a word line booster circuit of another embodiment.

FIG. 8 is a diagram showing a word line booster circuit according to still another embodiment.

FIG. 9 is a diagram showing the power supply potential dependency of the word line boosted potential obtained by the embodiment of FIGS. 7 and 8;

FIG. 10 is a diagram showing a configuration of a first potential generation circuit in a DRAM of another embodiment.

FIG. 11 is a diagram showing a configuration example of a first reference potential generation circuit in FIG. 10;

12 is a diagram showing a configuration example of a second reference potential generation circuit in FIG.

FIG. 13 is a graph showing the dependency of the threshold voltage of a MOS transistor on the thickness of a gate oxide film.

FIG. 14 is a diagram showing output potential characteristics of the potential generating circuit of FIG.

FIG. 15 is a diagram showing the power supply potential dependency of the word line potential in the embodiment using the potential generating circuit of FIG. 10;

FIG. 16 is a diagram showing a word line leak compensation circuit in a DRAM according to still another embodiment.

FIG. 17 is a diagram showing a configuration example of a comparison detection circuit in FIG. 16;

FIG. 18 is a diagram showing a configuration example of a ring oscillator.

FIG. 19 is a diagram showing a comparison detection circuit obtained by modifying the configuration of FIG. 17;

FIG. 20 is a diagram showing a word line drive circuit of a conventional DRAM.

FIG. 21 is a diagram showing the power supply potential dependency of the word line boosted potential.

[Description of Signs] 1 ... Row address buffer, 2 ... Column address buffer, 3 ... RAS control circuit, 4 ... CAS control circuit, 5 ... Column decoder, 6 ... Row decoder, 7 ... Word line booster circuit, 8 ... memory cell array, 9 ... sense amplifier, 10 ... input buffer, 11 ... output buffer, 20 ₁ ... first potential generating circuit, 20 ₂ ... second potential generating circuit, 21 ₁ ... first Reference potential generation circuit, 21 ₂ ... second reference potential generation circuit, 22 ₁ ... first amplification circuit, 22 ₂ ... second amplification circuit, 23 ... wired OR connection, 31 ... comparison detection circuit, 32 ... ring oscillator , 33 ... Charge pump circuit

Continuation of the front page (56) References JP-A-4-38786 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/407

Claims (14)

(57) [Claims] 1. A method for controlling a dynamic semiconductor device having first and second word line boosted potential generating circuits for applying a boosted potential to a selected word line, wherein at least the first word line boosted potential generating circuit includes: An output potential of a step-down potential generating circuit for stepping down an external power supply potential is operated as a power supply, and the step-down potential generating circuit receives a first reference potential output independent of the power supply potential output from the first reference potential generating circuit as an input. Comparing the first reference potential output with the output potential of the step-down potential generation circuit to generate the step-down potential; and comparing the word line boost potential with the reference potential using the step-down power supply potential as a reference potential. A second word line boosting circuit for boosting the word line boosted potential when the word line boosted potential becomes equal to or lower than a predetermined value; By using the threshold value of the MOS transistors on one chip, and generates a reference potential having a component which varies in proportion to the gate insulating film thickness without depending on the power supply voltage, the MOS transistor, the threshold value The gate
To the extent that is approximately proportional to the oxide film thickness, characterized by having a sufficiently large threshold than the absolute value of the portion which the value of the threshold unit amount in proportion to the thickness of the gate insulating film is not proportional to the thickness of the gate insulating film A method for controlling a dynamic semiconductor memory device. 2. A method of controlling a dynamic semiconductor device having first and second word line boosted potential generating circuits for applying a boosted potential to a selected word line, wherein at least the first word line boosted potential generating circuit includes: An output potential of a step-down potential generating circuit for stepping down an external power supply potential is operated as a power supply, and the step-down potential generating circuit receives a first reference potential output independent of the power supply potential output from the first reference potential generating circuit as an input. Comparing the first reference potential output with the output potential of the step-down potential generation circuit to generate the step-down potential; and comparing the word line boost potential with the reference potential using the step-down power supply potential as a reference potential. A second word line boosting circuit for boosting the word line boosted potential when the word line boosted potential becomes equal to or lower than a predetermined value; By using the threshold value of the MOS transistor on one chip, a reference potential having a component that varies in proportion to the gate insulating film thickness without depending on the power supply voltage is generated, and the threshold value of the MOS transistor is set to Vt = K · Tox + 2ΦF−VFB (in the case of NMOS) = − K · Tox + 2ΦF + VFB (in the case of PMOS) (where K is a proportional constant, Tox is the gate insulating film thickness, and ΦF
Substantially ratio Fermi level, VFB when expressed as the flat band voltage), the threshold is the gate oxide film thickness
Enough to example, 2ΦF-VFB control method for a dynamic semiconductor memory device, wherein the absolute value (for NMOS) or 2ΦF + VFB (For PMOS) is well under small than the value of the other terms. 3. The word line boosting circuit according to claim 1, wherein the second word line boosting circuit comprises a charge pump, and the detected potential of the word line boosted potential is changed between when the charge pump is operating and when the charge pump is stopped. 3. The method for controlling a semiconductor memory device according to claim 2. 4. A semiconductor device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit has a first terminal connected to the selected word line. Means for boosting a capacitor having a second terminal as a driving terminal; and means for precharging the first terminal to a first potential while the second terminal is held at the “L” level. At the time of charging, a potential boosted to a value equal to or higher than a first potential plus a threshold value due to capacitive coupling is input to the gate, a drain is connected to the external power supply potential, and a source is connected to the first terminal. A step-down potential generating circuit that generates, as the second potential, a potential that is less dependent on fluctuations in the external power supply potential in a predetermined power supply voltage range; A capacitor driving circuit for obtaining a boosted potential at the first terminal by raising the potential from the L "level state to a second potential; and a potential generating circuit for generating the second potential, wherein an operation state for charging the capacitor And an output reference potential from a first reference potential generation circuit for generating a flat first reference potential independent of an external power supply potential and a reference potential generated from the second potential generation circuit using the external power supply potential as a power supply. And generating a second potential independent of an external power supply potential generated by matching them, wherein the first reference potential is generated based on a threshold value of a MOS transistor on the semiconductor memory device, In the MOS transistor , the threshold is the gate.
To the extent that is approximately proportional to the oxide film thickness, characterized by having a sufficiently large threshold than the absolute value of the portion which the value of the threshold unit amount in proportion to the thickness of the gate insulating film is not proportional to the thickness of the gate insulating film A method for controlling a dynamic semiconductor memory device. 5. A semiconductor device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit has a first terminal connected to the selected word line; Means for boosting a capacitor having a second terminal as a driving terminal; and means for precharging the first terminal to a first potential while the second terminal is held at the “L” level. At the time of charging, a potential boosted to a value equal to or higher than a first potential plus a threshold value due to capacitive coupling is input to the gate, a drain is connected to the external power supply potential, and a source is connected to the first terminal. A step-down potential generating circuit that generates, as the second potential, a potential that is less dependent on fluctuations in the external power supply potential in a predetermined power supply voltage range; A capacitor driving circuit for obtaining a boosted potential at the first terminal by raising the potential from the L "level state to a second potential; and a potential generating circuit for generating the second potential, wherein an operation state for charging the capacitor And an output reference potential from a first reference potential generation circuit for generating a flat first reference potential independent of an external power supply potential and a reference potential generated from the second potential generation circuit using the external power supply potential as a power supply. And generating a second potential independent of an external power supply potential generated by matching them, wherein the first reference potential is generated based on a threshold value of a MOS transistor on the semiconductor memory device, and Vt = K · Tox + 2ΦF−VFB (in the case of NMOS) = − K · Tox + 2ΦF + VFB (in the case of PMOS) (where K is a proportional constant, T ox is the gate insulating film thickness, ΦF
Substantially ratio Fermi level, VFB when expressed as the flat band voltage), the threshold is the gate oxide film thickness
Enough to example, 2ΦF-VFB control method for a dynamic semiconductor memory device, wherein the absolute value (for NMOS) or 2ΦF + VFB (For PMOS) is well under small than the value of the other terms. 6. A semiconductor device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit has a first terminal connected to the selected word line, A boosting capacitor having a second terminal as a drive terminal; and an NMOS transistor for precharging the first terminal to a first potential while the second terminal is held at “L” level. A capacitor driving circuit that raises the second terminal from an “L” level state to an external power supply potential that is a second potential to obtain a boosted potential at the first terminal; and generates the first potential. A potential generation circuit configured to generate a flat first reference potential independent of an external power supply potential in an operation state of charging the capacitor; And a reference potential generated from these potentials is compared to generate a first potential independent of an external power supply potential generated by matching them. The first reference potential is a threshold of a MOS transistor on the semiconductor memory device. The MOS transistor has a portion that increases in proportion to a gate insulating film thickness by being generated based on a value.
To the extent that is approximately proportional to the oxide film thickness, characterized by having a sufficiently large threshold than the absolute value of the portion which the value of the threshold unit amount in proportion to the thickness of the gate insulating film is not proportional to the thickness of the gate insulating film A method for controlling a dynamic semiconductor memory device. 7. A potential compensating circuit for controlling an operation of a ring oscillator for driving a charge pump circuit by detecting a potential change of a boosted potential in order to compensate for a potential change caused by a leak of the word line. Claims 4 to 6
13. The semiconductor memory device according to claim 1. 8. The potential detection of the word line boosted potential is performed by comparing a potential independent of an external power supply potential and the boosted potential during a predetermined operation.
7. The semiconductor memory device according to claim 1. 9. The method according to claim 4, wherein the detection of the potential of the word line boosting potential is performed by comparing a step-down power supply potential as a power supply of the word line boosting circuit with the boosted potential. 3. The semiconductor memory device according to claim 1. 10. The semiconductor memory device according to claim 7, wherein said sensed potential of said word line boosted potential is changed between a charge pump operation and a charge pump stop. 11. A semiconductor memory device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit compensates for a potential change due to a leak of the word line. A potential compensating circuit that controls the operation of a ring oscillator that drives a charge pump circuit by detecting a potential change in the boosted potential, wherein the potential detection of the word line boosted potential includes a potential that does not depend on an external power supply potential during a predetermined operation. detected by comparing the boosted potential by comparison detection circuit, the reference potential regardless of the supply voltage by generating, based on the threshold of the MOS transistor on the semiconductor memory device, the MOS transistor is to the Threshold is the gate
To the extent you approximately proportional to the oxide film thickness, the thickness of the gate insulating film having a sufficiently larger threshold value that the absolute value of the portion which the value of the threshold unit amount in proportion to the thickness of the gate insulating film is not proportional to the thickness of the gate insulating film A dynamic semiconductor memory device having a potential component that increases in proportion to the following. 12. A semiconductor memory device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit compensates for a potential change due to a leak of the word line. A potential compensating circuit that controls the operation of a ring oscillator that drives a charge pump circuit by detecting a potential change in the boosted potential, wherein the potential detection of the word line boosted potential includes a potential that does not depend on an external power supply potential during a predetermined operation. The boosted potential is compared and detected by a comparison detection circuit, and the reference potential is generated with reference to the threshold value of the MOS transistor on the semiconductor memory device. Vt = K · Tox + 2ΦF−VFB (for NMOS) = − K · Tox + 2ΦF + VFB (for PMOS) (where K is Proportional constant, Tox is gate insulating film thickness, ΦF
Substantially ratio Fermi level, VFB when expressed as the flat band voltage), the threshold is the gate oxide film thickness
Enough to example, 2ΦF-VFB control method for a dynamic semiconductor memory device, wherein the absolute value (for NMOS) or 2ΦF + VFB (For PMOS) is well under small than the value of the other terms. 13. A semiconductor memory device having a word line boosted potential generating circuit for applying a boosted potential to a selected word line, wherein the word line boosted potential generating circuit compensates for a potential change due to a leak of the word line. A potential compensating circuit that controls the operation of a ring oscillator that drives a charge pump circuit by detecting a potential change in the boosted potential, wherein the potential detection of the word line boosted potential includes a potential that does not depend on an external power supply potential during a predetermined operation. A semiconductor memory device wherein the boosted potential is compared and detected by a comparison detection circuit, and the detection of the potential of the word line boosted potential varies between a charge pump operation time and a charge pump stop time. 14. The reference potential regardless of the supply voltage by generating, based on the threshold of the MOS transistor on the semiconductor memory device, also the MOS transistor, the threshold is the gate oxide film thickness Is almost proportional to
That extent, the threshold unit fraction of a value proportional to the gate insulating film thickness
Dynamic of claim 13 but which is characterized by having a portion which increases in proportion to the thickness of the gate insulating film having a sufficiently <br/> greater threshold than the absolute value of the portion which is not proportional to the gate insulating film thickness Semiconductor storage device.