JP4104939B2 - Multiprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiprocessor system in which, when data is transferred between a plurality of processors, the time required for data transfer between the processors can always be made smaller than a predetermined maximum time.
[0002]
[Prior art]
When data is freely transferred between a plurality of processors, first, a method of providing a signal line for transferring data between the processors can be considered. In this method, since independent signal lines exist between processors that need to be transferred, data can be freely transferred at any time. However, if data transfer is performed at high speed using a large number of processors, the total number of signal lines between the processors becomes enormous. Especially when a plurality of processors are mounted on one LSI, an extremely large wiring area is required. Because it is necessary, it is not realistic.
[0003]
Therefore, as a practical multiprocessor system that can be applied to a large number of processors, for example, a system using a ring bus as described in JP-A-2001-156817 has been proposed. In this system, when data from another processor coming through the ring bus is destined for itself, the data is received from the ring bus and received. On the other hand, when sending data to another processor, the data is sent after confirming that the ring bus is free. If there is other data on the ring bus, transmission is waited until the ring bus is free.
[0004]
[Problems to be solved by the invention]
However, in the conventional multiprocessor system described above, when the ring bus is used for data transfer between other processors when data is transmitted, a waiting time is required until the ring bus is free. Especially in situations where there is a lot of transfer data on the ring bus, this waiting time becomes large and the time required for the transfer between processors cannot be estimated correctly, and in some cases the transfer must be given up. There was a problem that the situation was possible.
The present invention has been made in consideration of the above points, and an object of the present invention is to provide a multiprocessor system in which the time required for data transfer between processors can be made smaller than a predetermined maximum time.
[0005]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a signal ring bus for transmitting a request signal for requesting transmission, a response signal for the request signal, a data ring bus for transmitting data, and a timing signal for transmitting timing signals. A ring bus, a timing generation unit that transmits the timing signal having a finite timing value to the timing ring bus, and a plurality of processors each including a bus control unit, Each of the processors includes a processor core, a dual-port memory that can be read and written independently from the processor core side and the bus control unit side, a transmission request register that stores transmission instruction contents, and a reception response that stores reception instruction contents A register, a transmission request flag that is set and reset in accordance with writing to and reading from the transmission request register, and a reception response flag that is set and reset in accordance with writing to and reading from the reception response register. The bus control unit is configured by a FIFO-structured memory that stores the transmission instruction content to which a transmission permission bit capable of random writing is added, and is stored in the transmission request register when the transmission request flag is set. The transmission request content is stored as the request instruction content and then the transmission request It consists of a transmission queue that resets the lag, a FIFO memory that stores the contents of the reception instruction with a dual port memory address and transfer end bit that can be randomly written, and checks the transfer end bit in order and sets When the reception response flag is reset, the reception instruction register and the dual port memory address are stored in the reception response register, and then the reception queue for setting the reception response flag and a predetermined transmission timing value are stored. The transmission control memory for storing, the reception control memory for storing a predetermined reception timing value, and the contents of the transmission instruction stored in the transmission queue are read out, and based on this, the request signal is generated and sent to the signal ring bus Request signal transmission control unit for transmission, and reception instruction contents stored in the reception queue A read signal, a dual port memory address for storing received data is allocated and written to the reception queue, the response signal is generated and transmitted to the signal ring bus, and the signal ring bus from the signal ring bus When receiving a request signal, the signal is stored in the reception queue, and when a response signal is received from the signal ring bus, a signal reception control unit that enables a corresponding transmission permission bit of the transmission queue; and When the transmission permission bit is enabled, the transmission timing value is known from the transmission control memory, and when the timing value of the timing ring bus matches the timing value, the data for the data from the corresponding address of the dual port memory A data transmission controller for transmitting data to the ring bus, and a receiver from the reception control memory. Knowing the imming value, when the timing value of the timing ring bus coincides with the reception timing value, the data is received from the data ring bus and stored in the corresponding address of the dual port memory. And a data reception control unit that sets a transfer end bit corresponding to the reception queue after receiving the data. It is comprised as follows.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a multiprocessor system of the present invention. FIG. 1 shows a case where data is transferred between six processors. In FIG. 1, 111, 112, 113, 114, 115, 116 are processors, 121, 122, 123, 124, 125, 126 are bus control units, 13 is a timing generation unit, 14 is a signal ring bus, and 15 is data. A ring bus 16 is a timing ring bus.
[0007]
FIG. 2 is a diagram for explaining data transfer in the multiprocessor system of the present invention. In FIG. 2, 211, 212, 213, 214, 215, and 216 represent each processor position including each bus control unit. An arrow indicates a data transfer path, and a number in <> indicates a timing value of the timing ring bus when data is transferred through the data transfer path. In FIG. 2, the numbers in <> of each data transfer path are set so that the numbers do not overlap in all the data transfer paths input to and output from each processor position. This is because it is assumed that the bus control unit does not transmit and receive data to the data ring bus at each processor position. On the other hand, the same number can be set for the input data transfer path and the output data transfer path.
[0008]
Hereinafter, the operation of the data transfer method of the multiprocessor system of the present invention will be described in detail with reference to FIG. 1 and FIG. The timing generation unit 13 generates a cyclic timing value and transmits it to the timing ring bus 16. In FIG. 2, it is assumed that the timing value takes a cyclic value that increases by 1 from 0 to 7 and then returns to 0.
[0009]
The operation will be described by taking the processor 111 and the bus control unit 121 as an example. In FIG. 2, it corresponds to the processor location 211. When data is to be transferred from the processor 111 to the processor 112, the processor 111 instructs the bus control unit 121 to transmit a request signal. The bus control unit 121 receives a command from the processor 111, generates a request signal, confirms that the signal ring bus 14 is empty, and transmits the request signal to the signal ring bus 14. If the signal ring bus 14 is not vacant with a signal from another processor, the signal ring bus 14 waits for vacancy and then transmits. The request signal includes information such as a destination address corresponding to the processor 112, a transmission source address corresponding to the processor 111, and a data length.
[0010]
The bus control unit 122 constantly monitors the signal ring bus 14 and receives a request signal addressed to itself. The bus control unit 122 extracts information from the request signal, prepares to receive data, generates a response signal, confirms that the signal ring bus 14 is empty, and then responds to the signal ring bus 14. Send a signal. If the signal ring bus 14 is not vacant with a signal from another processor, the signal ring bus 14 waits for vacancy and then transmits. The response signal includes a destination address corresponding to the processor 111, a transmission source address corresponding to the processor 112, information indicating transmission permission, and the like.
[0011]
The bus control unit 121 constantly monitors the signal ring bus 14, and receives a response signal addressed to itself. Then, the bus control unit 121 extracts information from the response signal, confirms information indicating transmission permission, and then starts data transmission. As shown in FIG. 2, the data is transmitted to the data ring bus 15 when the timing value of the timing ring bus 16 coincides with a value determined in advance for the data transfer path. In this case, transmission is possible when the timing value is zero. If the data length is 2 or more, the next data is transmitted when the next 0 comes after the timing value has been completed.
[0012]
The bus control unit 122 receives data from the data ring bus 15 when the timing value of the timing ring bus 16 is zero. If the data length is 2 or more, the next data is received when the next 0 comes after the timing value has been completed. When data corresponding to the data length known as the request signal information is received, the data reception process is terminated, and the processor 112 is informed that the data reception has been completed. The processor 112 can perform necessary processing using the received data.
[0013]
In the multiprocessor system of the present invention, it is necessary to transmit the request signal and the response signal to the signal ring bus 14 after confirming that the signal ring bus 14 is free. However, when preparation for data transfer is completed by this, subsequent transfer to the data ring bus 15 does not need to check for vacancy, and is executed only on the timing value of the predetermined timing ring bus 16 as a condition. it can. Further, since data transmission to the data ring bus 15 can be executed in a pipelined manner in parallel with transmission of request signals and response signals to the signal ring bus 14, data transfer is performed at a preset speed. Can do. In FIG. 2, only one value is set as a timing value at which data can be transferred through each data transfer path. However, a plurality of values can be set. Can improve the data transfer speed.
[0014]
FIG. 3 is a block diagram showing an example of a configuration example of the processor and the bus control unit in the multiprocessor system of the present invention. In FIG. 3, 31 is a processor, 32 is a bus control unit, 311 is a processor core, 312 is a dual port memory (hereinafter abbreviated as DP memory), 313 is a reception response register, 314 is a transmission request register, and 315 is a reception Response flag, 316 is a transmission request flag, 321 is a transmission queue, 322 is a reception queue, 323 is a transmission control memory, 324 is a reception control memory, 325 is a data transmission control unit, 326 is a data reception control unit, and 327 is a request signal transmission A control unit 328 is a response signal transmission control unit, and 329 is a signal reception control unit. Hereinafter, the operation of the bus control unit in the multiprocessor system of the present invention will be described in detail with reference to FIG. 3, FIG. 1, and FIG. Similar to the above description, the processor 111 and the bus control unit 121 in FIG. 1 will be described as an example.
[0015]
For example, when it is desired to transfer data from the processor 111 (corresponding to the processor 31 in FIG. 3) to the processor 112, the processor core 311 checks the state of the transmission request flag 316. The transmission request flag 316 is a 1-bit flag having two states of set and reset, and is set when there is a transmission request, and reset when there is no transmission request. If the transmission request flag 316 is reset, the processor core 311 stores information necessary for generating a request signal such as a destination address and a data length corresponding to the processor 112 and transmission data in the transmission request register 314. The DP memory address is stored, and then the transmission request flag 316 is set. If the transmission request flag 316 is set, the preceding transmission request has not been processed yet, and the processor core 311 must wait for processing.
[0016]
The bus control unit 121 (corresponding to the bus control unit 32 in FIG. 3) monitors the transmission request flag 316, and if it is set, reads the content of the transmission request register 314 and stores the content in the transmission queue 321. The transmission request flag 316 is reset. The transmission queue 321 is an irregular FIFO-structured memory to which transmission permission bits that can be randomly written are added, and the contents other than the transmission permission bits can be read in order from the previously stored contents.
[0017]
The request signal transmission control unit 327 reads the content written first from the transmission queue 321, generates a request signal, confirms the availability of the signal ring bus 14, and then sends the request signal to the signal ring bus 14. Send. If the signal ring bus 14 is not vacant with a signal from another processor, the signal ring bus 14 waits for vacancy and then transmits. If there is no content to be read in the transmission queue 321, the request signal transmission control unit 327 waits for the content to be read to be stored.
[0018]
In the bus control unit 122 (corresponding to the bus control unit 32 in FIG. 3), the signal reception control unit 329 constantly monitors the signal ring bus 14, and receives a request signal addressed to itself. The contents are stored in the reception queue 322. The reception queue 322 is a memory having an irregular FIFO structure to which a DP memory address capable of random writing and a transfer end bit are added. Except for the DP memory address and the transfer end bit, the contents stored in order are stored in order. Can be read.
[0019]
The response signal transmission control unit 328 reads the content stored first in the reception queue 322, and if an area for storing the received data is allocated to the DP memory 312, writes the DP memory address, and sends the response signal. After generating and confirming the availability of the signal ring bus 14, a response signal is transmitted to the signal ring bus 14. If the signal ring bus 14 is not vacant with a signal from another processor, the signal ring bus 14 waits for vacancy and then transmits. In addition, the response signal transmission control unit 328 notifies the data reception control unit 326 of the DP memory address for storing the received data. If the DP memory 312 cannot allocate an area for storing the received data, the response signal transmission control unit 328 waits for processing.
[0020]
In the bus control unit 121 (corresponding to the bus control unit 32 in FIG. 3), the signal reception control unit 329 constantly monitors the signal ring bus 14, and receives a response signal addressed to itself. Then, after extracting information from the response signal and confirming information indicating transmission permission, the corresponding transmission permission bit of the transmission queue 321 is permitted.
[0021]
The data transmission control unit 325 sequentially reads the transmission permission bits in the transmission queue 321 and, if they are permitted, starts data transmission from the DP memory address corresponding to the transmission queue 321. If the transmission permission bit is not permitted, the data transmission control unit 325 waits for processing. The data transmission control unit 325 knows a transmission timing value at which predetermined data can be transmitted from the transmission control memory 323, and transmits the data to the data ring bus 15 when the timing value of the timing ring bus matches the transmission timing value. To do. In this case, 0 is stored in the transmission control memory 323 as a transmission timing value for the destination address 112, and transmission is possible when the timing value of the timing ring bus 16 is zero. If the data length is 2 or more, the next data is transmitted from the next DP memory address when the next zero comes after the timing value has been completed.
[0022]
In the bus control unit 122 (corresponding to the bus control unit 32 in FIG. 3), the data reception control unit 326 knows 0 as the reception timing value for the transmission source address 111 from the reception control memory 324 and determines the timing ring bus 16. When the timing value is 0, data is received from the data ring bus 15 and stored in the DP memory address notified from the response signal transmission control unit 328 of the DP memory 312. If the data length is 2 or more, the next data is received when the timing value is cycled and the next 0 arrives, and the DP memory address is updated and stored in the DP memory 312. When data corresponding to the data length known as the request signal information is received, the data reception process is terminated, and the corresponding transfer end bit of the reception queue 322 is set.
[0023]
The reception queue 322 checks the transfer end bit in order, and if it is set, checks the state of the reception response flag 315. The reception response flag 315 is a 1-bit flag having two states of set and reset, and is set when there is a reception response, and is reset when there is no reception response. If the reception response flag 315 is reset, the reception queue 322 stores the transmission source address, the data length, and the DP memory address corresponding to the processor 111 in the reception response register 313, and then sets the reception response flag 315. . If the reception response flag 315 is set, the reception queue 322 has to wait for processing because the preceding reception response has not yet been processed.
[0024]
In the processor 112 (corresponding to the processor 31 in FIG. 3), the processor core 311 examines the state of the reception response flag 315, and if it is set, reads the content of the reception response register 313 and reads the DP memory address. And the data length are used to read the information transferred from the DP memory 312. Thereafter, the processor core 311 can perform necessary processing after resetting the reception response flag 315.
[0025]
Since the processor 31 in FIG. 3 uses the DP memory 312 to store the transmitted and received data, transmission and reception cannot be performed at the same timing. However, it is also possible to perform transmission and reception simultaneously by providing separate DP memories dedicated for transmission and reception, or by providing a dedicated circuit that can transmit and receive simultaneously instead of DP memory. Is possible. In this case, the same number can be set for each processor position in FIG. 2 for the data transfer path to be input and the data transfer path to be output, so that the efficiency of data transfer can be improved.
[0026]
FIG. 4 is a block diagram showing a second embodiment of the multiprocessor system of the present invention. FIG. 4 shows a case where data is transferred between six processors as an example, as in FIG. In FIG. 4, 41 is a left signal ring bus, 42 is a right signal ring bus, 43 is a left data ring bus, and 44 is a right data ring bus, and the same components as those in FIG. Has been.
[0027]
FIG. 5 is a diagram for explaining the state of data transfer in the second embodiment of the multiprocessor system of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals. The number in <> indicates the timing value of the timing ring bus when data is transmitted and received through the data transfer path using the right data ring bus. The number in [] indicates the timing value of the timing ring bus when data is transmitted through the data transfer path using the left data ring bus, and the number in {} indicates the left data ring bus. The timing value of the timing ring bus when data is received through the used data transfer path is shown. However, in FIG. 5, it is assumed that the timing ring bus flows in the same clockwise direction as the right data ring bus. In FIG. 5, the numbers in <>, [], and {} of each data transfer path are set so that the numbers do not overlap in all data transfer paths that are input to and output from each processor position. Yes. This is because it is assumed that the bus control unit does not transmit and receive data to the data ring bus at each processor position. On the other hand, the same number can be set for the input data transfer path and the output data transfer path.
[0028]
In the second embodiment of the multiprocessor system of the present invention, the signal ring bus and the data ring bus are divided into two counterclockwise and clockwise ring buses, so that the ring bus closest in distance can be selected. It is a thing. By doing so, the average data transfer distance is shortened, and the transfer efficiency can be improved. For example, when the processor 111 wants to transfer data to the processor 112, the processor 111 instructs the bus control unit 121 to transmit a request signal. In response to an instruction from the processor 111, the bus control unit 121 generates a request signal, selects the nearer right signal ring bus 42, confirms the availability of the right signal ring bus, and then performs the right signal use. A request signal is transmitted to the ring bus 42. If the right signal ring bus 42 is not empty due to a signal from another processor, transmission is performed after waiting for the signal to become empty. The request signal includes information such as a destination address corresponding to the processor 112, a transmission source address corresponding to the processor 111, and a data length.
[0029]
The bus control unit 122 always monitors the left and right signal ring buses 41 and 42, and receives a request signal addressed to itself. Then, the bus control unit 122 extracts information from the request signal, prepares to receive the data, generates a response signal, confirms the vacancy of the near left signal ring bus 41, and then performs the left signal use. Transmit to the ring bus 41. If the left signal ring bus 41 is not free due to a signal from another processor, transmission is performed after waiting for the signal to be free. The response signal includes a destination address corresponding to the processor 111, a transmission source address corresponding to the processor 112, information indicating transmission permission, and the like.
[0030]
The bus control unit 121 always monitors the left and right signal ring buses 41 and 42, and receives a response signal addressed to itself. Then, the bus control unit 121 extracts information from the response signal, confirms information indicating transmission permission, and then starts data transmission. As shown in FIG. 5, when the timing value of the timing ring bus 16 coincides with a value determined in advance for the data transfer path, the data is transmitted to the closer right data ring bus 44. In this case, transmission is possible when the timing value is zero. If the data length is 2 or more, the next data is transmitted when the next 0 comes after the timing value has been completed.
[0031]
The bus control unit 122 receives data from the right data ring bus 44 when the timing value of the timing ring bus 16 is zero. If the data length is 2 or more, the next data is received when the next 0 comes after the timing value has been completed. When data corresponding to the data length known as the request signal information is received, the data reception process is terminated, and the processor 112 is informed that the data reception has been completed. The processor 112 can perform necessary processing using the received data.
[0032]
In the multiprocessor system of the present invention shown in FIG. 4, both the signal ring bus and the data ring bus are divided into the left-handed and right-handed ring buses, but directly affects the data transfer efficiency. It is also possible to separate only the data ring bus. In FIG. 5, only one value is set as a timing value at which data can be transferred through each data transfer path. However, a plurality of values can be set. Can improve the data transfer speed.
[0033]
FIG. 6 is a block diagram showing a configuration example of the processor and the bus control unit in the second embodiment of the multiprocessor system of the present invention. In FIG. 6, 61 is a bus control unit, 611 is a transmission queue, 612 is a reception queue, 613 is a transmission control memory, 614 is a reception control memory, 615 is a data transmission control unit, 616 is a data reception control unit, and 617 is a request signal. A transmission control unit, 618 is a response signal transmission control unit, 619 is a signal reception control unit, 620 is a left buffer, and 621 is a right buffer. The same components as those in FIG. 3 are denoted by the same reference numerals.
[0034]
For example, when it is desired to transfer data from the processor 111 (corresponding to the processor 31 in FIG. 6) to the processor 112, the processor core 311 checks the state of the transmission request flag 316, and if this is reset, the transmission request register In 314, a destination address corresponding to the processor 112, information necessary for generating a request signal such as a data length, and a DP memory address in which transmission data is stored are stored, and then a transmission request flag 316 is set. If the transmission request flag 316 is set, the preceding transmission request has not been processed yet, and the processor core 311 must wait for processing.
[0035]
The bus control unit 121 (corresponding to the bus control unit 61 in FIG. 6) monitors the transmission request flag 316, and if it is set, reads the content of the transmission request register 314 and stores the content in the transmission queue 611. The transmission request flag 316 is reset. The request signal transmission control unit 617 reads the content written first from the transmission queue 611, refers to the content of the transmission control memory 613, and selects the right signal ring bus 42 closer to the destination address 112. Then, the request signal transmission control unit 617 generates a request signal, confirms that the right signal ring bus 42 is empty, and then transmits the request signal to the right signal ring bus 42. If the right signal ring bus 42 is not empty due to a signal from another processor, transmission is performed after waiting for the signal to become empty. Further, if there is no content to be read in the transmission queue 611, the request signal transmission control unit 617 waits for the content to be read to be stored.
[0036]
In the bus control unit 122 (corresponding to the bus control unit 61 in FIG. 6), the left buffer 620 and the right buffer 621 constantly monitor the left signal ring bus 41 and the right signal ring bus 42, respectively. When the right buffer 621 receives a request signal addressed to itself, the right buffer 621 receives it. The signal reception control unit 619 constantly monitors the status of the left buffer 620 and the right buffer 621, receives the request signal in the right buffer 621, receives this request signal, and stores the content in the reception queue 612.
[0037]
The response signal transmission control unit 618 reads the content stored first in the reception queue 612, and when the area for storing the data to be received is allocated to the DP memory 312, writes the DP memory address, The ring bus 41 for the left signal that is closer to the destination address 111 is selected. Then, the response signal transmission control unit 618 generates a response signal, confirms that the left signal ring bus 41 is empty, and then transmits the response signal to the left signal ring bus 41. If the left signal ring bus 41 is not free due to a signal from another processor, transmission is performed after waiting for the signal to be free. In addition, the response signal transmission control unit 618 notifies the data reception control unit 616 of the DP memory address for storing the received data. If the DP memory 312 cannot allocate an area for storing received data, the response signal transmission control unit 618 waits for processing.
[0038]
In the bus control unit 121 (corresponding to the bus control unit 61 in FIG. 6), the left buffer 620 and the right buffer 621 constantly monitor the left signal ring bus 41 and the right signal ring bus 42, respectively. The left buffer 620 receives a response signal addressed to the left buffer 620. The signal reception control unit 619 constantly monitors the status of the left buffer 620 and the right buffer 621, receives the response signal in the left buffer 620, receives the response signal, extracts information from the response signal, and indicates transmission permission. After confirming the information, the corresponding transmission permission bit of the transmission queue 611 is permitted.
[0039]
The data transmission control unit 615 sequentially reads the transmission permission bits of the transmission queue 611, and when it is permitted, starts data transmission from the corresponding DP memory address of the transmission queue 611. If the transmission permission bit is not permitted, the data transmission control unit 615 waits for processing. The data transmission control unit 615 knows from the transmission control memory 613 a transmission timing value at which predetermined data can be transmitted, and when the timing value of the timing ring bus 16 matches the transmission timing value, the data transmission control unit 615 sends the data to the timing ring bus 16. Send the transmission timing value. In this case, 0 is stored in the transmission control memory 613 as the transmission timing value for the destination address 112, and transmission is possible when the timing value of the timing ring bus 16 is zero. If the data length is 2 or more, the next data is transmitted from the next DP memory address when the next zero comes after the timing value has been completed.
[0040]
In the bus control unit 122 (corresponding to the bus control unit 61 in FIG. 6), the data reception control unit 616 knows 0 as the reception timing value for the transmission source address 111 from the reception control memory 614, and When the timing value is 0, data is received from the data ring bus 15 and stored in the DP memory address notified from the response signal transmission control unit of the DP memory 312. If the data length is 2 or more, the next data is received when the timing value is cycled and the next 0 arrives, and the DP memory address is updated and stored in the DP memory 312. When data corresponding to the data length known as the request signal information is received, the data reception process is terminated, and the corresponding transfer end bit of the reception queue 612 is set.
[0041]
The reception queue 612 checks the transfer end bit in order, and if it is set, checks the state of the reception response flag 315. If the reception response flag 315 is reset, the reception queue 612 stores the transmission source address, the data length, and the DP memory address corresponding to the processor 111 in the reception response register 313, and then sets the reception response flag 315. . If the reception response flag 315 is set, the reception queue 612 has to wait for processing because the preceding reception response has not yet been processed.
[0042]
In the processor 112 (corresponding to the processor 31 in FIG. 6), the processor core 311 examines the state of the reception response flag 315, and if it is set, reads the contents of the reception response register 313 and reads the DP memory address. And the data length are used to read the information transferred from the DP memory 312. Thereafter, the processor core 311 can perform necessary processing after resetting the reception response flag 315.
[0043]
Since the processor 31 in FIG. 6 uses the DP memory 312 to store the transmitted and received data, transmission and reception cannot be performed at the same timing. However, it is possible to perform transmission and reception at the same time by providing a DP memory dedicated for transmission and reception, or by providing a dedicated register circuit that can transmit and receive simultaneously instead of the DP memory. Is possible. In this case, the same number can be set for each processor position in FIG. 5 for the data transfer path to be input and the data transfer path to be output, thereby improving the efficiency of data transfer.
[0044]
The embodiments of the multiprocessor system have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Of course.
【The invention's effect】
As described above in detail, according to the present invention, data transfer using the data ring bus can be executed only on the timing value of the predetermined timing ring bus. Therefore, it is possible to provide a multiprocessor system in which the time required for data transfer between processors can be made smaller than a predetermined maximum time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a multiprocessor system of the present invention.
FIG. 2 is a diagram for explaining a state of data transfer in the first embodiment of the multiprocessor system of the present invention.
FIG. 3 is a block diagram illustrating a first configuration example of a processor and a bus control unit in the multiprocessor system according to the first embodiment of this invention.
FIG. 4 is a block diagram showing a second embodiment of the multiprocessor system of the present invention.
FIG. 5 is a diagram for explaining a state of data transfer in the second embodiment of the multiprocessor system of the present invention;
FIG. 6 is a block diagram illustrating a second configuration example of a processor and a bus control unit in a multiprocessor system according to a second embodiment of this invention.
[Explanation of symbols]
111, 112, 113, 114, 115, 116: processor, 121, 122, 123, 124, 125, 126: bus control unit, 13: timing generation unit, 14: signal ring bus, 15: data ring bus, 16: ring bus for timing, 211, 212, 213, 214, 215, 216: processor position, 31: processor, 32: bus control unit, 311: processor core, 312: dual port memory, 313: reception response register 314: Transmission request register, 315: Reception response flag, 316: Transmission request flag, 321: Transmission queue, 322: Reception queue, 323: Transmission control memory, 324: Reception control memory, 325: Data transmission control unit, 326: Data reception control unit, 327: request signal transmission control unit, 328: response signal Communication control unit, 329: signal reception control unit, 41: left signal ring bus, 42: right signal ring bus, 43: left data ring bus, 44: right data ring bus, 61: bus control unit, 611 : Transmission queue, 612: reception queue, 613: transmission control memory, 614: reception control memory, 615: data transmission control unit, 616: data reception control unit, 617: request signal transmission control unit, 618: response signal transmission control unit 619: Signal reception control unit 620: Left buffer 621: Right buffer

Claims (2)

A signal ring bus for transmitting a request signal for requesting transmission and a response signal for the request signal, a data ring bus for transmitting data, a timing ring bus for transmitting timing signals, and the timing ring bus A timing generation unit that transmits the timing signal composed of the timing value of the plurality of processors, and a plurality of processors each including a bus control unit,
Each of the processors includes a processor core, a dual-port memory that can be read and written independently from the processor core side and the bus control unit side, a transmission request register that stores transmission instruction contents, and a reception response that stores reception instruction contents A register, a transmission request flag that is set and reset in accordance with writing to and reading from the transmission request register, and a reception response flag that is set and reset in accordance with writing to and reading from the reception response register. And
The bus control unit
It is composed of a memory having a FIFO structure for storing the transmission instruction content to which a transmission permission bit capable of random writing is added, and when the transmission request flag is set, the transmission instruction content stored in the transmission request register is the request instruction. A transmission queue that resets the transmission request flag after storing as content;
It is composed of a dual-port memory address that can be written randomly and a FIFO-structured memory that stores the contents of the reception instruction with a transfer end bit added. When the transfer end bit is sequentially checked and set, the reception response flag is reset A reception queue that sets the reception response flag after storing the reception instruction content and the dual port memory address in the reception response register;
A transmission control memory for storing a predetermined transmission timing value;
A reception control memory for storing a predetermined reception timing value;
A request signal transmission control unit that reads the transmission instruction content stored in the transmission queue, generates the request signal based on the transmission instruction content, and transmits the request signal to the signal ring bus;
A response signal that reads the contents of the reception instruction stored in the reception queue, assigns a dual-port memory address for storing the received data, writes it to the reception queue, generates the response signal, and transmits it to the signal ring bus A transmission control unit;
When receiving the request signal from the signal ring bus, the signal is stored in the reception queue, and when a response signal is received from the signal ring bus, the signal reception control for permitting the corresponding transmission permission bit of the transmission queue. And
When the transmission permission bit of the transmission queue is enabled, the transmission timing value is known from the transmission control memory, and when the timing value of the timing ring bus matches the timing value, the corresponding of the dual port memory A data transmission control unit for transmitting data from the address to the data ring bus;
The reception timing value is obtained from the reception control memory, and when the timing ring bus timing value matches the reception timing value, the data is received from the data ring bus and stored in the corresponding address of the dual port memory. And a data reception control unit that sets a transfer end bit corresponding to the reception queue after receiving all the data . The data ring bus is composed of a left data ring bus and a right data ring bus through which data flows counterclockwise and clockwise, and a data ring bus having a shorter distance to a processor to which data is transferred Configured to select
The signal ring bus is composed of a left signal ring bus and a right signal ring bus through which signals flow counterclockwise and clockwise, and the request signal or the response signal is closer to the destination processor. Configure to select the signal ring bus,
When the request signal or the response signal is received from the left signal ring bus, the bus controller stores the request signal or the response signal, and the request signal or the response from the right signal ring bus. when receiving the signal, adding the right buffer you store the request signal or said response signal,
In addition to the transmission timing value, the transmission control memory selects either the left signal ring bus or the right signal ring bus, or the left data ring bus or the right data ring bus. To store bus selection information for
The reception control memory selects one of the left signal ring bus and the right signal ring bus, or the left data ring bus and the right data ring bus, in addition to the reception timing value. To store bus selection information for
The request signal transmission control unit selects one of the left signal ring bus and the right signal ring bus based on the bus selection information in the transmission control memory, and then requests the selected signal ring bus. Send a signal,
The response signal transmission control unit selects either the left signal ring bus or the right signal ring bus based on the bus selection information in the reception control memory, and then responds to the selected signal ring bus. Send a signal,
The signal reception control unit checks the left buffer or the right buffer and performs processing on the signal if the signal is stored,
The data transmission control unit transmits data after selecting either the left data ring bus or the right data ring bus based on the bus selection information of the transmission control memory,
The data reception control unit receives data after selecting either the left data ring bus or the right data ring bus based on the bus selection information in the reception control memory. The multiprocessor system according to claim 1.

Images