JP4089609B2 - Electronic device package and method of manufacturing electronic device package - Google Patents

Description

  The present invention relates to an electronic device package including an electronic device in a sealed internal space and a manufacturing method thereof.

  Conventionally, as a technique for protecting semiconductor elements, surface acoustic wave elements, and other various electronic elements from the effects of moisture, oxygen, etc. present in the atmosphere, the electronic elements are stored inside the container and the container is sealed. A technique for sealing an electronic element is known. For electronic device devices that are sealed by placing such electronic devices in the internal space, various technologies have been proposed to improve the air tightness (sealing performance) inside the container and prevent the entry of moisture and the like more reliably. Has been. For example, an opening of a ceramic substrate having a cavity (concave portion) on which an electronic element is mounted on the bottom surface is covered with a metal lid, and the ceramic substrate and the metal lid are joined and sealed using solder, glass powder, or the like. Has been done.

On the other hand, a technique for sealing an electronic element by sealing a gap between the electronic element mounted by flip chip bonding and the substrate is also used. For example, in Patent Document 1, in the manufacture of a surface acoustic wave device, a surface acoustic wave chip flip-chip connected to a package substrate is sealed with a low melting point glass and sealed with a resin. A technique for obtaining higher airtightness is disclosed.
JP 2003-110402 A

  By the way, when it is sealed with a low melting point glass as disclosed in Patent Document 1 or when a member constituting a container is joined with solder or glass powder, high airtightness can be obtained, Heat treatment for melting low melting glass or solder at high temperature is required, and it is not suitable for sealing electronic devices with low heat resistance. In particular, electronic devices such as compound semiconductors have low heat resistance, and thus are highly likely to be damaged by high-temperature heating.

  In addition, when the inside of the container is hermetically sealed by such heat treatment, it is difficult to use a resin or the like as a material because a member such as a lid that forms the container is also required to have heat resistance. Also, there is a limit to reducing the container cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to house an electronic element in an enclosed space at a low temperature (preferably 150 ° C. or less) in an electronic element package.

The invention according to claim 1 is an electronic element package for sealing an electronic element, a first container member and a second container member that form a space in which the electronic element is accommodated, and the space. The first container member and the second container member are provided with a metal layer formed by metal bonding with gold, and the first container member or the second container member is formed of a resin, After the metal layer irradiates energy waves to the metal part on the adhesion part of the first container member and the metal part on the adhesion part of the second container member in a reduced pressure or inert gas environment, An electronic device package characterized by being formed by bringing metal parts into contact with each other is used.

The invention according to claim 2 uses the electronic device package according to claim 1 , wherein the metal layer formed of gold is formed by plating.

Invention of Claim 3 is a manufacturing method of an electronic element package, Comprising: Before or after the process of mounting an electronic element in a 1st container member, and the process of mounting the said electronic element, either is resin. A step of disposing the first container member and the second container member as formed in a reduced pressure or inert gas environment, and a metal part formed of gold on an adhesion site of the first container member; Irradiating a metal part formed of gold on an adhesion site of the second container member with an energy wave; the metal part of the first container member; and the metal part of the second container member; And a step of forming a sealed space in which the electronic device is housed. The method of manufacturing an electronic device package is characterized by comprising:

Invention of Claim 4 is a manufacturing method of the electronic element package of Claim 3 , Comprising: In the process of forming the said space, the said 1st container member and the said 2nd container member are more than room temperature An electronic device package manufacturing method characterized by being set to 150 ° C. or lower is used.

  In the present invention, the first container member and the second container member can be bonded at a low temperature to store the electronic element in the sealed space.

  According to the second and sixth aspects of the invention, the reliability of sealing the space in which the electronic element is stored is improved.

  In the invention of claim 3, the manufacturing cost of the electronic device package can be reduced.

  FIG. 1 is a cross-sectional view showing a configuration of an electronic element package 1 according to an embodiment of the present invention. The electronic element package 1 is a package in which a semiconductor element 71 as an electronic element is sealed (that is, a package in which an electronic element is provided in a sealed space), and a substrate 9 having a cavity (concave portion) 99. (A so-called “cavity substrate”), a semiconductor element 71 mounted on the bottom surface of the cavity 99, and a space (hereinafter referred to as “the cavity substrate”) in which the semiconductor element 71 is accommodated by being attached to the substrate 9 by closing the opening of the cavity 99. It is referred to as an “internal space”).

  The substrate 9 and the lid member 2 are formed of a resin such as plastic. The substrate 9 is a multilayer substrate in which electrodes and the like are formed on the bottom surface of the cavity 99 on which the semiconductor element 71 is mounted and on the back surface (surface opposite to the internal space 90). The semiconductor element 71 is a so-called bare IC chip, and a metal bump 72 formed on a land on the lower surface of the semiconductor element 71 is electrically bonded to an electrode on the bottom surface of the cavity 99 of the substrate 9, whereby the substrate 9. To be implemented. The electrodes on the front and back surfaces of the bottom surface are appropriately electrically connected to each other, and the electronic device package 1 is mounted on another external substrate from the substrate 9 side, whereby the external substrate and the semiconductor element 71 are electrically connected. The

  In the electronic device package 1, the internal space 90 is sealed by bonding the substrate 9 and the lid member 2 with the metal layer 3 formed of gold (Au). The metal layer 3 is formed by joining a substrate metal part 31 provided on the substrate 9 side and a lid metal part 32 provided on the lid member 2 side.

  FIG. 2 is a diagram illustrating a manufacturing process of the electronic element package 1. When the electronic device package 1 is manufactured, first, the respective adhesion portions of the substrate 9 and the lid member 2, that is, the end surface of the opening of the cavity 99 of the substrate 9 (the surface facing the lid member 2), and Gold plating is applied to a region to which the substrate 9 is bonded on the lower surface (the surface on the internal space 90 side) of the lid member 2 to form the substrate metal portion 31 and the lid metal portion 32 (step S11).

  Subsequently, the substrate 9, the lid member 2, and the semiconductor element 71 are arranged in the chamber of the bonding apparatus, and the inside of the chamber is decompressed by a vacuum pump connected to the chamber. When the inside of the chamber is in a reduced pressure state (preferably in a vacuum state), a fast atom beam (hereinafter referred to as “FAB”) of argon (Ar) is applied to the bump 72 and the electrode on the bottom surface of the cavity 99. Irradiation is performed to clean the surfaces of the bumps 72 and the electrodes (that is, unnecessary materials on the surface are removed and the surface is activated). Thereafter, the bumps 72 are brought into contact with the electrodes of the substrate 9 to join the bumps 72 and the electrodes, and the semiconductor element 71 is mounted on the substrate 9 (step S12).

  The semiconductor element 71 may be mounted by other methods, for example, ultrasonic vibration while the semiconductor element 71 is pressed toward the bottom surface of the cavity 99 in a state where the bump 72 and the electrode of the substrate 9 are in contact with each other. The bumps 72 and the electrodes may be bonded and mounted by applying. Moreover, you may carry out via an anisotropic conductive resin film (or paste) and a nonelectroconductive resin film (or paste). The bump 72 may be formed on the electrode of the substrate 9. There may be a plurality of semiconductor elements 71 (other electronic elements may be used as described later) to be mounted.

  Next, the substrate metal part 31 of the substrate 9 and the lid metal part 32 of the lid member 2 are irradiated with FAB, and the surfaces of the substrate metal part 31 and the lid metal part 32 are cleaned (step S13). At this time, the temperature of the substrate metal part 31 of the substrate 9 and the lid metal part 32 of the lid member 2 is set to room temperature or higher and 150 ° C. or lower, and is heated by laser light irradiation or the like when heating is necessary.

  Thereafter, the substrate metal part 31 and the lid metal part 32 are brought into contact with each other under a reduced pressure (vacuum) environment in the chamber, so that the substrate metal part 31 and the lid metal part 32 are joined to each other to form the metal layer 3. Is formed. As described above, the substrate 9 and the lid member 2 are bonded together by the metal layer 3, and the internal space 90 in which the semiconductor element 71 is accommodated is sealed in a reduced pressure (vacuum) state, whereby the electronic element package 1 is manufactured (step S14). ). The substrate 9 and the lid member 2 may be bonded together under an inert gas environment. In this case, an inert gas is sealed in the internal space 90 together with the semiconductor element 71. Further, the inside of the chamber may be depressurized at the time of sealing in an inert gas environment (from atmospheric pressure to 1 Pa (pascal) to 10 Pa may be reduced).

  As described above, in the electronic element package 1, the substrate 9 and the lid member 2 are bonded at a lower temperature (preferably room temperature or higher and 150 ° C. or lower) compared to normal solder or glass powder bonding, and the semiconductor element 71. The internal space 90 in which is stored is sealed. As a result, even the semiconductor element 71 having low heat resistance can be stored in the sealed space at a low temperature without being damaged by heat. In addition, an inexpensive resin substrate 9 and lid member 2 having low heat resistance compared to ceramic, metal, etc. can be used, and the manufacturing cost of the electronic element package 1 can be reduced. Furthermore, since the internal space 90 is in a reduced pressure (vacuum) state or an inert gas atmosphere, the semiconductor element 71 can be protected from the influence of moisture, oxygen, etc. existing in the atmosphere. Performance degradation can be suppressed.

  In the electronic element package 1, the substrate metal part 31 and the lid metal part 32 are bonded by a strong bonding force between atoms, so that the substrate 9 and the lid member 2 are bonded with high reliability and have high airtightness. An internal space 90 is formed. In addition, since the substrate metal part 31 and the cover metal part 32 are made of gold, a chemically stable (not easily chemically changed) metal layer 3 can be obtained, and the sealing reliability of the internal space 90 is improved. The

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to the said embodiment, A various change is possible. For example, the substrate 9 and the lid member 2 are preferably formed of a resin from the viewpoint of manufacturing cost reduction, but may be formed of other materials such as metal or ceramic. The metal layer 3 is preferably formed of gold from the viewpoint of improving the reliability of sealing the internal space 90, but may be formed of other various metals.

  Each of the substrate 9 and the lid member 2 is a lid member having a flat plate-like substrate and a recess that covers the side and upper side (opposite side of the substrate 9) of the semiconductor element 71 mounted on the substrate. Also good. Further, the internal space 90 may be formed by bonding a substrate having a cavity structure and a lid member so as to close each other's opening.

  The temperature of the substrate metal part 31 and the cover metal part 32 at the time of bonding between the substrate 9 and the lid member 2 is the range shown in the above embodiment from the viewpoint of reducing the influence of heat on the semiconductor element 71 mounted on the substrate 9. However, it is not limited to the above range. For example, when the semiconductor element 71 having relatively high heat resistance is mounted on the substrate 9, the temperature may be higher than the above range. .

  In the above embodiment, argon is used as the FAB, but other atoms such as nitrogen and hydrogen can also be used as the FAB. Further, instead of the FAB, the substrate metal part 31 and the lid metal part 32 may be cleaned by other energy waves such as an ion beam.

  The manufacturing method of the electronic device package 1 is suitable for sealing various types of electronic devices other than semiconductor devices, particularly electronic devices having low heat resistance and low moisture resistance.

Sectional drawing which shows the structure of the electronic element package which concerns on one embodiment Diagram showing manufacturing process of electronic device package

Explanation of symbols

1 Electronic Device Package 2 Lid Member 3 Metal Layer 9 Substrate 31 Substrate Metal Part 32 Lid Metal Part 71 Semiconductor Element 90 Internal Space S11 to S14 Steps

Claims (4)

An electronic device package,
An electronic element;
The first container member and the second container member that form a space in which the electronic element is accommodated, and the first container member and the second container member are metal-bonded with gold to seal the space And a metal layer formed of
The first container member or the second container member is formed of a resin;
After the metal layer irradiates an energy wave to the metal part on the adhesion part of the first container member and the metal part on the adhesion part of the second container member in a reduced pressure or inert gas environment, An electronic element package formed by bringing both metal parts into contact with each other. 2. The electronic device package according to claim 1, wherein the metal layer made of gold is formed by plating. A method for manufacturing an electronic device package, comprising:
Mounting the electronic element on the first container member;
Before or after the step of mounting the electronic element, the step of placing the first container member and the second container member, either of which is made of resin, under reduced pressure or an inert gas environment;
Irradiating an energy wave to a metal part formed of gold on an adhesion part of the first container member and a metal part formed of gold on an adhesion part of the second container member;
Joining the metal part of the first container member and the metal part of the second container member by bringing them into contact with each other to form a sealed space in which the electronic element is housed;
An electronic element package manufacturing method comprising: It is a manufacturing method of the electronic device package according to claim 3 ,
In the step of forming the space, the method of manufacturing an electronic device package, wherein the first container member and the second container member are set to room temperature to 150 ° C.

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